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Commit 0242909a authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'cris_move' of git://www.jni.nu/cris 

* 'cris_move' of git://www.jni.nu/cris:
  [CRIS] Move header files from include to arch/cris/include.
  [CRISv32] Remove warning in io.h
parents 0a6d2fac 556dcee7
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Showing with 124 additions and 1746 deletions
arch/cris/Makefile
View file @ 0242909a
......@@ -23,12 +23,16 @@ mach-$(CONFIG_ETRAXFS) := fs
ifneq ($(arch-y),)
SARCH := arch-$(arch-y)
inc := -Iarch/cris/include/arch-$(arch-y) -Iarch/cris/include/arch-$(arch-y)/arch
else
SARCH :=
inc :=
endif
ifneq ($(mach-y),)
MACH := mach-$(mach-y)
inc += -Iarch/cris/include/$(SARCH)/$(MACH)/
inc += -Iarch/cris/include/$(SARCH)/$(MACH)/mach
else
MACH :=
endif
......@@ -39,9 +43,9 @@ OBJCOPYFLAGS := -O binary -R .note -R .comment -S
CPPFLAGS_vmlinux.lds = -DDRAM_VIRTUAL_BASE=0x$(CONFIG_ETRAX_DRAM_VIRTUAL_BASE)
KBUILD_AFLAGS += -mlinux -march=$(arch-y) -Iinclude/asm/arch/mach -Iinclude/asm/arch
KBUILD_CFLAGS += -mlinux -march=$(arch-y) -pipe -Iinclude/asm/arch/mach -Iinclude/asm/arch
KBUILD_AFLAGS += -mlinux -march=$(arch-y) $(inc)
KBUILD_CFLAGS += -mlinux -march=$(arch-y) -pipe $(inc)
KBUILD_CPPFLAGS += $(inc)
ifdef CONFIG_FRAME_POINTER
KBUILD_CFLAGS := $(subst -fomit-frame-pointer,,$(KBUILD_CFLAGS)) -g
......@@ -73,7 +77,7 @@ all: zImage
zImage Image: vmlinux
$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@
archprepare: $(SRC_ARCH)/.links $(srctree)/include/asm-$(ARCH)/.arch FORCE
archprepare: $(SRC_ARCH)/.links FORCE
# Create some links to make all tools happy
$(SRC_ARCH)/.links:
......@@ -95,17 +99,6 @@ endif
@ln -sfn ../$(SARCH)/kernel/asm-offsets.c $(SRC_ARCH)/kernel/asm-offsets.c
@touch $@
# Create link to sub arch includes
$(srctree)/include/asm-$(ARCH)/.arch: $(wildcard include/config/arch/*.h)
@echo ' SYMLINK include/asm-$(ARCH)/arch -> include/asm-$(ARCH)/$(SARCH)'
@rm -f $(srctree)/include/asm-$(ARCH)/arch/mach
@rm -f $(srctree)/include/asm-$(ARCH)/arch
@ln -sf $(SARCH) $(srctree)/include/asm-$(ARCH)/arch
ifdef CONFIG_ETRAX_ARCH_V32
@ln -sf $(MACH) $(srctree)/include/asm-$(ARCH)/arch/mach
endif
@touch $@
archclean:
$(Q)if [ -e arch/$(ARCH)/boot ]; then \
$(MAKE) $(clean)=arch/$(ARCH)/boot; \
......@@ -116,8 +109,7 @@ CLEAN_FILES += \
$(MACHINE)/boot/compressed/decompress.bin \
$(MACHINE)/boot/compressed/piggy.gz \
$(MACHINE)/boot/rescue/rescue.bin \
$(SRC_ARCH)/.links \
$(srctree)/include/asm-$(ARCH)/.arch
$(SRC_ARCH)/.links
MRPROPER_FILES += \
$(SRC_ARCH)/drivers \
......
arch/cris/arch-v10/boot/compressed/head.S
View file @ 0242909a
......@@ -9,7 +9,7 @@
*/
#define ASSEMBLER_MACROS_ONLY
#include <asm/arch/sv_addr_ag.h>
#include <arch/sv_addr_ag.h>
#define RAM_INIT_MAGIC 0x56902387
#define COMMAND_LINE_MAGIC 0x87109563
......
arch/cris/arch-v10/boot/compressed/misc.c
View file @ 0242909a
......@@ -20,7 +20,7 @@
#include <linux/types.h>
#include <asm/arch/svinto.h>
#include <arch/svinto.h>
/*
* gzip declarations
......
arch/cris/arch-v10/boot/rescue/head.S
View file @ 0242909a
......@@ -65,7 +65,7 @@
#ifdef CONFIG_ETRAX_AXISFLASHMAP
#define ASSEMBLER_MACROS_ONLY
#include <asm/arch/sv_addr_ag.h>
#include <arch/sv_addr_ag.h>
;; The partitiontable is looked for at the first sector after the boot
;; sector. Sector size is 65536 bytes in all flashes we use.
......
arch/cris/arch-v10/boot/rescue/kimagerescue.S
View file @ 0242909a
......@@ -6,7 +6,7 @@
*/
#define ASSEMBLER_MACROS_ONLY
#include <asm/arch/sv_addr_ag.h>
#include <arch/sv_addr_ag.h>
#define CODE_START 0x40004000
#define CODE_LENGTH 784
......
arch/cris/arch-v10/boot/rescue/testrescue.S
View file @ 0242909a
......@@ -6,7 +6,7 @@
*/
#define ASSEMBLER_MACROS_ONLY
#include <asm/arch/sv_addr_ag.h>
#include <arch/sv_addr_ag.h>
.text
......
arch/cris/arch-v10/drivers/axisflashmap.c
View file @ 0242909a
......@@ -26,7 +26,7 @@
#include <asm/axisflashmap.h>
#include <asm/mmu.h>
#include <asm/arch/sv_addr_ag.h>
#include <arch/sv_addr_ag.h>
#ifdef CONFIG_CRIS_LOW_MAP
#define FLASH_UNCACHED_ADDR KSEG_8
......
arch/cris/arch-v10/drivers/ds1302.c
View file @ 0242909a
......@@ -24,10 +24,10 @@
#include <asm/uaccess.h>
#include <asm/system.h>
#include <asm/arch/svinto.h>
#include <arch/svinto.h>
#include <asm/io.h>
#include <asm/rtc.h>
#include <asm/arch/io_interface_mux.h>
#include <arch/io_interface_mux.h>
#include "i2c.h"
......
arch/cris/arch-v10/drivers/gpio.c
View file @ 0242909a
......@@ -23,11 +23,11 @@
#include <linux/interrupt.h>
#include <asm/etraxgpio.h>
#include <asm/arch/svinto.h>
#include <arch/svinto.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/irq.h>
#include <asm/arch/io_interface_mux.h>
#include <arch/io_interface_mux.h>
#define GPIO_MAJOR 120 /* experimental MAJOR number */
......
arch/cris/arch-v10/drivers/i2c.c
View file @ 0242909a
......@@ -25,10 +25,10 @@
#include <asm/etraxi2c.h>
#include <asm/system.h>
#include <asm/arch/svinto.h>
#include <arch/svinto.h>
#include <asm/io.h>
#include <asm/delay.h>
#include <asm/arch/io_interface_mux.h>
#include <arch/io_interface_mux.h>
#include "i2c.h"
......
arch/cris/arch-v10/drivers/sync_serial.c
View file @ 0242909a
......@@ -26,11 +26,11 @@
#include <asm/irq.h>
#include <asm/dma.h>
#include <asm/io.h>
#include <asm/arch/svinto.h>
#include <arch/svinto.h>
#include <asm/uaccess.h>
#include <asm/system.h>
#include <asm/sync_serial.h>
#include <asm/arch/io_interface_mux.h>
#include <arch/io_interface_mux.h>
/* The receiver is a bit tricky beacuse of the continuous stream of data.*/
/* */
......
arch/cris/arch-v10/kernel/crisksyms.c
View file @ 0242909a
#include <linux/module.h>
#include <asm/io.h>
#include <asm/arch/svinto.h>
#include <arch/svinto.h>
/* Export shadow registers for the CPU I/O pins */
EXPORT_SYMBOL(genconfig_shadow);
......
arch/cris/arch-v10/kernel/debugport.c
View file @ 0242909a
......@@ -19,7 +19,7 @@
#include <linux/delay.h>
#include <linux/tty.h>
#include <asm/system.h>
#include <asm/arch/svinto.h>
#include <arch/svinto.h>
#include <asm/io.h> /* Get SIMCOUT. */
extern void reset_watchdog(void);
......
arch/cris/arch-v10/kernel/dma.c
View file @ 0242909a
......@@ -7,7 +7,7 @@
#include <linux/errno.h>
#include <asm/dma.h>
#include <asm/arch/svinto.h>
#include <arch/svinto.h>
/* Macro to access ETRAX 100 registers */
#define SETS(var, reg, field, val) var = (var & ~IO_MASK_(reg##_, field##_)) | \
......
arch/cris/arch-v10/kernel/entry.S
View file @ 0242909a
......@@ -23,7 +23,7 @@
#include <linux/linkage.h>
#include <linux/sys.h>
#include <asm/unistd.h>
#include <asm/arch/sv_addr_ag.h>
#include <arch/sv_addr_ag.h>
#include <asm/errno.h>
#include <asm/thread_info.h>
#include <asm/asm-offsets.h>
......
arch/cris/arch-v10/kernel/fasttimer.c
View file @ 0242909a
......@@ -24,7 +24,7 @@
#include <asm/rtc.h>
#include <asm/arch/svinto.h>
#include <arch/svinto.h>
#include <asm/fasttimer.h>
#include <linux/proc_fs.h>
......
arch/cris/arch-v10/kernel/head.S
View file @ 0242909a
......@@ -10,7 +10,7 @@
#define ASSEMBLER_MACROS_ONLY
/* The IO_* macros use the ## token concatenation operator, so
-traditional must not be used when assembling this file. */
#include <asm/arch/sv_addr_ag.h>
#include <arch/sv_addr_ag.h>
#define CRAMFS_MAGIC 0x28cd3d45
#define RAM_INIT_MAGIC 0x56902387
......
arch/cris/arch-v10/kernel/io_interface_mux.c
View file @ 0242909a
......@@ -11,9 +11,9 @@
#include <linux/module.h>
#include <linux/init.h>
#include <asm/arch/svinto.h>
#include <arch/svinto.h>
#include <asm/io.h>
#include <asm/arch/io_interface_mux.h>
#include <arch/io_interface_mux.h>
#define DBG(s)
......
arch/cris/arch-v10/kernel/kgdb.c
View file @ 0242909a
......@@ -176,7 +176,7 @@
#include <asm/setup.h>
#include <asm/ptrace.h>
#include <asm/arch/svinto.h>
#include <arch/svinto.h>
#include <asm/irq.h>
static int kgdb_started = 0;
......
arch/cris/arch-v10/kernel/process.c
View file @ 0242909a
......@@ -14,7 +14,7 @@
#include <linux/err.h>
#include <linux/fs.h>
#include <linux/slab.h>
#include <asm/arch/svinto.h>
#include <arch/svinto.h>
#include <linux/init.h>
#ifdef CONFIG_ETRAX_GPIO
......
arch/cris/arch-v10/kernel/time.c
View file @ 0242909a
......@@ -14,7 +14,7 @@
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <asm/arch/svinto.h>
#include <arch/svinto.h>
#include <asm/types.h>
#include <asm/signal.h>
#include <asm/io.h>
......
arch/cris/arch-v10/kernel/traps.c
View file @ 0242909a
......@@ -10,7 +10,7 @@
#include <linux/ptrace.h>
#include <asm/uaccess.h>
#include <asm/arch/sv_addr_ag.h>
#include <arch/sv_addr_ag.h>
void
show_registers(struct pt_regs *regs)
......
arch/cris/arch-v10/mm/fault.c
View file @ 0242909a
......@@ -13,7 +13,7 @@
#include <linux/mm.h>
#include <asm/uaccess.h>
#include <asm/pgtable.h>
#include <asm/arch/svinto.h>
#include <arch/svinto.h>
#include <asm/mmu_context.h>
/* debug of low-level TLB reload */
......
arch/cris/arch-v10/mm/init.c
View file @ 0242909a
......@@ -12,7 +12,7 @@
#include <asm/mmu.h>
#include <asm/io.h>
#include <asm/mmu_context.h>
#include <asm/arch/svinto.h>
#include <arch/svinto.h>
extern void tlb_init(void);
......
arch/cris/arch-v10/mm/tlb.c
View file @ 0242909a
......@@ -12,7 +12,7 @@
#include <asm/tlb.h>
#include <asm/mmu_context.h>
#include <asm/arch/svinto.h>
#include <arch/svinto.h>
#define D(x)
......
arch/cris/arch-v32/boot/compressed/head.S
View file @ 0242909a
......@@ -7,7 +7,7 @@
#define ASSEMBLER_MACROS_ONLY
#include <hwregs/asm/reg_map_asm.h>
#include <asm/arch/mach/startup.inc>
#include <mach/startup.inc>
#define RAM_INIT_MAGIC 0x56902387
#define COMMAND_LINE_MAGIC 0x87109563
......@@ -17,7 +17,7 @@
.globl input_data
.text
start:
_start:
di
;; Start clocks for used blocks.
......
arch/cris/arch-v32/drivers/mach-a3/gpio.c
View file @ 0242909a
......@@ -33,7 +33,7 @@
#include <asm/io.h>
#include <asm/system.h>
#include <asm/irq.h>
#include <asm/arch/mach/pinmux.h>
#include <mach/pinmux.h>
#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
#include "../i2c.h"
......
arch/cris/arch-v32/drivers/mach-a3/nandflash.c
View file @ 0242909a
......@@ -18,7 +18,7 @@
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <asm/arch/memmap.h>
#include <arch/memmap.h>
#include <hwregs/reg_map.h>
#include <hwregs/reg_rdwr.h>
#include <hwregs/pio_defs.h>
......
arch/cris/arch-v32/drivers/mach-fs/nandflash.c
View file @ 0242909a
......@@ -18,7 +18,7 @@
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <asm/arch/memmap.h>
#include <arch/memmap.h>
#include <hwregs/reg_map.h>
#include <hwregs/reg_rdwr.h>
#include <hwregs/gio_defs.h>
......
arch/cris/arch-v32/drivers/pci/bios.c
View file @ 0242909a
#include <linux/pci.h>
#include <linux/kernel.h>
#include <asm/arch/hwregs/intr_vect.h>
#include <arch/hwregs/intr_vect.h>
void __devinit pcibios_fixup_bus(struct pci_bus *b)
{
......
arch/cris/arch-v32/kernel/cache.c
View file @ 0242909a
#include <linux/module.h>
#include <asm/io.h>
#include <asm/arch/cache.h>
#include <asm/arch/hwregs/dma.h>
#include <arch/cache.h>
#include <arch/hwregs/dma.h>
/* This file is used to workaround a cache bug, Guinness TR 106. */
......
arch/cris/arch-v32/kernel/crisksyms.c
View file @ 0242909a
#include <linux/module.h>
#include <linux/irq.h>
#include <asm/arch/dma.h>
#include <asm/arch/intmem.h>
#include <asm/arch/mach/pinmux.h>
#include <asm/arch/io.h>
#include <arch/dma.h>
#include <arch/intmem.h>
#include <mach/pinmux.h>
#include <arch/io.h>
/* Functions for allocating DMA channels */
EXPORT_SYMBOL(crisv32_request_dma);
......
arch/cris/arch-v32/kernel/debugport.c
View file @ 0242909a
......@@ -9,7 +9,7 @@
#include <hwregs/reg_map.h>
#include <hwregs/ser_defs.h>
#include <hwregs/dma_defs.h>
#include <asm/arch/mach/pinmux.h>
#include <mach/pinmux.h>
struct dbg_port
{
......
arch/cris/arch-v32/kernel/entry.S
View file @ 0242909a
......@@ -24,8 +24,8 @@
#include <asm/thread_info.h>
#include <asm/asm-offsets.h>
#include <asm/arch/hwregs/asm/reg_map_asm.h>
#include <asm/arch/hwregs/asm/intr_vect_defs_asm.h>
#include <hwregs/asm/reg_map_asm.h>
#include <hwregs/asm/intr_vect_defs_asm.h>
;; Exported functions.
.globl system_call
......
arch/cris/arch-v32/kernel/head.S
View file @ 0242909a
......@@ -11,11 +11,11 @@
* -traditional must not be used when assembling this file.
*/
#include <hwregs/reg_rdwr.h>
#include <asm/arch/memmap.h>
#include <arch/memmap.h>
#include <hwregs/intr_vect.h>
#include <hwregs/asm/mmu_defs_asm.h>
#include <hwregs/asm/reg_map_asm.h>
#include <asm/arch/mach/startup.inc>
#include <mach/startup.inc>
#define CRAMFS_MAGIC 0x28cd3d45
#define JHEAD_MAGIC 0x1FF528A6
......
arch/cris/arch-v32/kernel/kgdb.c
View file @ 0242909a
......@@ -174,10 +174,10 @@
#include <asm/ptrace.h>
#include <asm/irq.h>
#include <asm/arch/hwregs/reg_map.h>
#include <asm/arch/hwregs/reg_rdwr.h>
#include <asm/arch/hwregs/intr_vect_defs.h>
#include <asm/arch/hwregs/ser_defs.h>
#include <arch/hwregs/reg_map.h>
#include <arch/hwregs/reg_rdwr.h>
#include <arch/hwregs/intr_vect_defs.h>
#include <arch/hwregs/ser_defs.h>
/* From entry.S. */
extern void gdb_handle_exception(void);
......
arch/cris/arch-v32/kernel/kgdb_asm.S
View file @ 0242909a
......@@ -5,7 +5,7 @@
* port exceptions for kernel debugging purposes.
*/
#include <asm/arch/hwregs/intr_vect.h>
#include <arch/hwregs/intr_vect.h>
;; Exported functions.
.globl kgdb_handle_exception
......
arch/cris/arch-v32/kernel/pinmux.c
View file @ 0242909a
......@@ -11,10 +11,10 @@
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/spinlock.h>
#include <asm/arch/hwregs/reg_map.h>
#include <asm/arch/hwregs/reg_rdwr.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/hwregs/pinmux_defs.h>
#include <arch/hwregs/reg_map.h>
#include <arch/hwregs/reg_rdwr.h>
#include <arch/pinmux.h>
#include <arch/hwregs/pinmux_defs.h>
#undef DEBUG
......
arch/cris/arch-v32/kernel/ptrace.c
View file @ 0242909a
......@@ -17,7 +17,7 @@
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/processor.h>
#include <asm/arch/hwregs/supp_reg.h>
#include <arch/hwregs/supp_reg.h>
/*
* Determines which bits in CCS the user has access to.
......
arch/cris/arch-v32/kernel/signal.c
View file @ 0242909a
......@@ -18,8 +18,8 @@
#include <asm/processor.h>
#include <asm/ucontext.h>
#include <asm/uaccess.h>
#include <asm/arch/ptrace.h>
#include <asm/arch/hwregs/cpu_vect.h>
#include <arch/ptrace.h>
#include <arch/hwregs/cpu_vect.h>
extern unsigned long cris_signal_return_page;
......
arch/cris/arch-v32/lib/nand_init.S
View file @ 0242909a
......@@ -22,11 +22,11 @@
##
##=============================================================================
#include <asm/arch/hwregs/asm/reg_map_asm.h>
#include <asm/arch/hwregs/asm/gio_defs_asm.h>
#include <asm/arch/hwregs/asm/pinmux_defs_asm.h>
#include <asm/arch/hwregs/asm/bif_core_defs_asm.h>
#include <asm/arch/hwregs/asm/config_defs_asm.h>
#include <arch/hwregs/asm/reg_map_asm.h>
#include <arch/hwregs/asm/gio_defs_asm.h>
#include <arch/hwregs/asm/pinmux_defs_asm.h>
#include <arch/hwregs/asm/bif_core_defs_asm.h>
#include <arch/hwregs/asm/config_defs_asm.h>
;; There are 8-bit NAND flashes and 16-bit NAND flashes.
;; We need to treat them slightly different.
......
arch/cris/arch-v32/mach-a3/dma.c
View file @ 0242909a
......@@ -2,7 +2,7 @@
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <asm/arch/mach/dma.h>
#include <mach/dma.h>
#include <hwregs/reg_map.h>
#include <hwregs/reg_rdwr.h>
#include <hwregs/marb_defs.h>
......
arch/cris/arch-v32/mach-a3/io.c
View file @ 0242909a
......@@ -12,7 +12,7 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <asm/io.h>
#include <asm/arch/mach/pinmux.h>
#include <mach/pinmux.h>
#include <hwregs/gio_defs.h>
struct crisv32_ioport crisv32_ioports[] = {
......
arch/cris/arch-v32/mach-fs/cpufreq.c
View file @ 0242909a
......@@ -2,9 +2,9 @@
#include <linux/module.h>
#include <linux/cpufreq.h>
#include <hwregs/reg_map.h>
#include <asm/arch/hwregs/reg_rdwr.h>
#include <asm/arch/hwregs/config_defs.h>
#include <asm/arch/hwregs/bif_core_defs.h>
#include <arch/hwregs/reg_rdwr.h>
#include <arch/hwregs/config_defs.h>
#include <arch/hwregs/bif_core_defs.h>
static int
cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,
......
arch/cris/arch-v32/mach-fs/dma.c
View file @ 0242909a
......@@ -10,7 +10,7 @@
#include <hwregs/strmux_defs.h>
#include <linux/errno.h>
#include <asm/system.h>
#include <asm/arch/mach/arbiter.h>
#include <mach/arbiter.h>
static char used_dma_channels[MAX_DMA_CHANNELS];
static const char *used_dma_channels_users[MAX_DMA_CHANNELS];
......
arch/cris/arch-v32/mach-fs/io.c
View file @ 0242909a
......@@ -12,8 +12,8 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <asm/io.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/hwregs/gio_defs.h>
#include <mach/pinmux.h>
#include <hwregs/gio_defs.h>
#ifndef DEBUG
#define DEBUG(x)
......
arch/cris/arch-v32/mach-fs/vcs_hook.c
View file @ 0242909a
......@@ -5,8 +5,8 @@
#include "vcs_hook.h"
#include <stdarg.h>
#include <asm/arch-v32/hwregs/reg_map.h>
#include <asm/arch-v32/hwregs/intr_vect_defs.h>
#include <arch-v32/hwregs/reg_map.h>
#include <arch-v32/hwregs/intr_vect_defs.h>
#define HOOK_TRIG_ADDR 0xb7000000 /* hook cvlog model reg address */
#define HOOK_MEM_BASE_ADDR 0xa0000000 /* csp4 (shared mem) base addr */
......
arch/cris/arch-v32/mm/init.c
View file @ 0242909a
......@@ -16,8 +16,8 @@
#include <asm/mmu.h>
#include <asm/io.h>
#include <asm/mmu_context.h>
#include <asm/arch/hwregs/asm/mmu_defs_asm.h>
#include <asm/arch/hwregs/supp_reg.h>
#include <arch/hwregs/asm/mmu_defs_asm.h>
#include <arch/hwregs/supp_reg.h>
extern void tlb_init(void);
......
arch/cris/arch-v32/mm/tlb.c
View file @ 0242909a
......@@ -9,8 +9,8 @@
#include <asm/tlb.h>
#include <asm/mmu_context.h>
#include <asm/arch/hwregs/asm/mmu_defs_asm.h>
#include <asm/arch/hwregs/supp_reg.h>
#include <arch/hwregs/asm/mmu_defs_asm.h>
#include <arch/hwregs/supp_reg.h>
#define UPDATE_TLB_SEL_IDX(val) \
do { \
......
include/asm-cris/arch-v10/io.h → arch/cris/include/arch-v10/arch/io.h
View file @ 0242909a
#ifndef _ASM_ARCH_CRIS_IO_H
#define _ASM_ARCH_CRIS_IO_H
#include <asm/arch/svinto.h>
#include <arch/svinto.h>
/* Etrax shadow registers - which live in arch/cris/kernel/shadows.c */
......
include/asm-cris/arch-v10/irq.h → arch/cris/include/arch-v10/arch/irq.h
View file @ 0242909a
......@@ -5,7 +5,7 @@
#ifndef _ASM_ARCH_IRQ_H
#define _ASM_ARCH_IRQ_H
#include <asm/arch/sv_addr_ag.h>
#include <arch/sv_addr_ag.h>
#define NR_IRQS 32
......
include/asm-cris/arch-v32/cache.h → arch/cris/include/arch-v32/arch/cache.h
View file @ 0242909a
#ifndef _ASM_CRIS_ARCH_CACHE_H
#define _ASM_CRIS_ARCH_CACHE_H
#include <asm/arch/hwregs/dma.h>
#include <arch/hwregs/dma.h>
/* A cache-line is 32 bytes. */
#define L1_CACHE_BYTES 32
......
include/asm-cris/arch-v32/cryptocop.h → arch/cris/include/arch-v32/arch/cryptocop.h
View file @ 0242909a
......@@ -122,7 +122,7 @@ struct strcop_crypto_op{
/********** The API to use from inside the kernel. ************/
#include <asm/arch/hwregs/dma.h>
#include <arch/hwregs/dma.h>
typedef enum {
cryptocop_alg_csum = 0,
......
include/asm-cris/arch-v32/io.h → arch/cris/include/arch-v32/arch/io.h
View file @ 0242909a
......@@ -43,7 +43,7 @@ extern struct crisv32_iopin crisv32_led_net1_red;
static inline void crisv32_io_set(struct crisv32_iopin *iopin, int val)
{
long flags;
unsigned long flags;
spin_lock_irqsave(&iopin->port->lock, flags);
if (val)
......@@ -57,7 +57,7 @@ static inline void crisv32_io_set(struct crisv32_iopin *iopin, int val)
static inline void crisv32_io_set_dir(struct crisv32_iopin* iopin,
enum crisv32_io_dir dir)
{
long flags;
unsigned long flags;
spin_lock_irqsave(&iopin->port->lock, flags);
if (dir == crisv32_io_dir_in)
......
include/asm-cris/atomic.h → arch/cris/include/asm/atomic.h
View file @ 0242909a
......@@ -6,7 +6,7 @@
#include <linux/compiler.h>
#include <asm/system.h>
#include <asm/arch/atomic.h>
#include <arch/atomic.h>
/*
* Atomic operations that C can't guarantee us. Useful for
......
include/asm-cris/bitops.h → arch/cris/include/asm/bitops.h
View file @ 0242909a
......@@ -18,7 +18,7 @@
#error only <linux/bitops.h> can be included directly
#endif
#include <asm/arch/bitops.h>
#include <arch/bitops.h>
#include <asm/system.h>
#include <asm/atomic.h>
#include <linux/compiler.h>
......
include/asm-cris/bug.h → arch/cris/include/asm/bug.h
View file @ 0242909a
#ifndef _CRIS_BUG_H
#define _CRIS_BUG_H
#include <asm/arch/bug.h>
#include <arch/bug.h>
#endif
include/asm-cris/byteorder.h → arch/cris/include/asm/byteorder.h
View file @ 0242909a
......@@ -4,7 +4,7 @@
#ifdef __GNUC__
#ifdef __KERNEL__
#include <asm/arch/byteorder.h>
#include <arch/byteorder.h>
/* defines are necessary because the other files detect the presence
* of a defined __arch_swab32, not an inline
......
include/asm-cris/cache.h → arch/cris/include/asm/cache.h
View file @ 0242909a
#ifndef _ASM_CACHE_H
#define _ASM_CACHE_H
#include <asm/arch/cache.h>
#include <arch/cache.h>
#endif /* _ASM_CACHE_H */
include/asm-cris/checksum.h → arch/cris/include/asm/checksum.h
View file @ 0242909a
......@@ -3,7 +3,7 @@
#ifndef _CRIS_CHECKSUM_H
#define _CRIS_CHECKSUM_H
#include <asm/arch/checksum.h>
#include <arch/checksum.h>
/*
* computes the checksum of a memory block at buff, length len,
......
include/asm-cris/delay.h → arch/cris/include/asm/delay.h
View file @ 0242909a
......@@ -7,7 +7,7 @@
* Delay routines, using a pre-computed "loops_per_second" value.
*/
#include <asm/arch/delay.h>
#include <arch/delay.h>
/* Use only for very small delays ( < 1 msec). */
......
include/asm-cris/dma.h → arch/cris/include/asm/dma.h
View file @ 0242909a
......@@ -3,7 +3,7 @@
#ifndef _ASM_DMA_H
#define _ASM_DMA_H
#include <asm/arch/dma.h>
#include <arch/dma.h>
/* it's useless on the Etrax, but unfortunately needed by the new
bootmem allocator (but this should do it for this) */
......
include/asm-cris/elf.h → arch/cris/include/asm/elf.h
View file @ 0242909a
......@@ -45,7 +45,7 @@ typedef unsigned long elf_fpregset_t;
#define ELF_DATA ELFDATA2LSB
#define ELF_ARCH EM_CRIS
#include <asm/arch/elf.h>
#include <arch/elf.h>
/* The master for these definitions is {binutils}/include/elf/cris.h: */
/* User symbols in this file have a leading underscore. */
......
include/asm-cris/io.h → arch/cris/include/asm/io.h
View file @ 0242909a
......@@ -2,7 +2,7 @@
#define _ASM_CRIS_IO_H
#include <asm/page.h> /* for __va, __pa */
#include <asm/arch/io.h>
#include <arch/io.h>
#include <linux/kernel.h>
struct cris_io_operations
......
include/asm-cris/irq.h → arch/cris/include/asm/irq.h
View file @ 0242909a
#ifndef _ASM_IRQ_H
#define _ASM_IRQ_H
#include <asm/arch/irq.h>
#include <arch/irq.h>
static inline int irq_canonicalize(int irq)
{
......
include/asm-cris/mmu.h → arch/cris/include/asm/mmu.h
View file @ 0242909a
......@@ -5,6 +5,6 @@
#ifndef _CRIS_MMU_H
#define _CRIS_MMU_H
#include <asm/arch/mmu.h>
#include <arch/mmu.h>
#endif
include/asm-cris/page.h → arch/cris/include/asm/page.h
View file @ 0242909a
#ifndef _CRIS_PAGE_H
#define _CRIS_PAGE_H
#include <asm/arch/page.h>
#include <arch/page.h>
#include <linux/const.h>
/* PAGE_SHIFT determines the page size */
......
include/asm-cris/pgtable.h → arch/cris/include/asm/pgtable.h
View file @ 0242909a
......@@ -12,7 +12,7 @@
#include <linux/sched.h>
#include <asm/mmu.h>
#endif
#include <asm/arch/pgtable.h>
#include <arch/pgtable.h>
/*
* The Linux memory management assumes a three-level page table setup. On
......
include/asm-cris/processor.h → arch/cris/include/asm/processor.h
View file @ 0242909a
......@@ -13,7 +13,7 @@
#include <asm/system.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include <asm/arch/processor.h>
#include <arch/processor.h>
struct task_struct;
......
include/asm-cris/ptrace.h → arch/cris/include/asm/ptrace.h
View file @ 0242909a
#ifndef _CRIS_PTRACE_H
#define _CRIS_PTRACE_H
#include <asm/arch/ptrace.h>
#include <arch/ptrace.h>
#ifdef __KERNEL__
......
arch/cris/include/asm/spinlock.h 0 → 100644
View file @ 0242909a
#include <arch/spinlock.h>
include/asm-cris/system.h → arch/cris/include/asm/system.h
View file @ 0242909a
#ifndef __ASM_CRIS_SYSTEM_H
#define __ASM_CRIS_SYSTEM_H
#include <asm/arch/system.h>
#include <arch/system.h>
/* the switch_to macro calls resume, an asm function in entry.S which does the actual
* task switching.
......
include/asm-cris/thread_info.h → arch/cris/include/asm/thread_info.h
View file @ 0242909a
......@@ -16,7 +16,7 @@
#ifndef __ASSEMBLY__
#include <asm/types.h>
#include <asm/processor.h>
#include <asm/arch/thread_info.h>
#include <arch/thread_info.h>
#include <asm/segment.h>
#endif
......
include/asm-cris/timex.h → arch/cris/include/asm/timex.h
View file @ 0242909a
......@@ -7,7 +7,7 @@
#ifndef _ASM_CRIS_TIMEX_H
#define _ASM_CRIS_TIMEX_H
#include <asm/arch/timex.h>
#include <arch/timex.h>
/*
* We don't have a cycle-counter.. but we do not support SMP anyway where this is
......
include/asm-cris/tlb.h → arch/cris/include/asm/tlb.h
View file @ 0242909a
......@@ -3,7 +3,7 @@
#include <linux/pagemap.h>
#include <asm/arch/tlb.h>
#include <arch/tlb.h>
/*
* cris doesn't need any special per-pte or
......
include/asm-cris/uaccess.h → arch/cris/include/asm/uaccess.h
View file @ 0242909a
......@@ -54,7 +54,7 @@
#define __access_ok(addr,size) (__kernel_ok || __user_ok((addr),(size)))
#define access_ok(type,addr,size) __access_ok((unsigned long)(addr),(size))
#include <asm/arch/uaccess.h>
#include <arch/uaccess.h>
/*
* The exception table consists of pairs of addresses: the first is the
......
include/asm-cris/unistd.h → arch/cris/include/asm/unistd.h
View file @ 0242909a
......@@ -336,7 +336,7 @@
#define NR_syscalls 327
#include <asm/arch/unistd.h>
#include <arch/unistd.h>
#define __ARCH_WANT_IPC_PARSE_VERSION
#define __ARCH_WANT_OLD_READDIR
......
include/asm-cris/user.h → arch/cris/include/asm/user.h
View file @ 0242909a
......@@ -4,7 +4,7 @@
#include <linux/types.h>
#include <asm/ptrace.h>
#include <asm/page.h>
#include <asm/arch/user.h>
#include <arch/user.h>
/*
* Core file format: The core file is written in such a way that gdb
......
arch/cris/mm/ioremap.c
View file @ 0242909a
......@@ -12,7 +12,7 @@
#include <linux/vmalloc.h>
#include <linux/io.h>
#include <asm/pgalloc.h>
#include <asm/arch/memmap.h>
#include <arch/memmap.h>
/*
* Generic mapping function (not visible outside):
......
drivers/net/cris/eth_v10.c
View file @ 0242909a
......@@ -32,14 +32,14 @@
#include <linux/skbuff.h>
#include <linux/ethtool.h>
#include <asm/arch/svinto.h>/* DMA and register descriptions */
#include <arch/svinto.h>/* DMA and register descriptions */
#include <asm/io.h> /* CRIS_LED_* I/O functions */
#include <asm/irq.h>
#include <asm/dma.h>
#include <asm/system.h>
#include <asm/ethernet.h>
#include <asm/cache.h>
#include <asm/arch/io_interface_mux.h>
#include <arch/io_interface_mux.h>
//#define ETHDEBUG
#define D(x)
......
drivers/serial/crisv10.c
View file @ 0242909a
......@@ -34,14 +34,14 @@ static char *serial_version = "$Revision: 1.25 $";
#include <asm/system.h>
#include <linux/delay.h>
#include <asm/arch/svinto.h>
#include <arch/svinto.h>
/* non-arch dependent serial structures are in linux/serial.h */
#include <linux/serial.h>
/* while we keep our own stuff (struct e100_serial) in a local .h file */
#include "crisv10.h"
#include <asm/fasttimer.h>
#include <asm/arch/io_interface_mux.h>
#include <arch/io_interface_mux.h>
#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
#ifndef CONFIG_ETRAX_FAST_TIMER
......
drivers/serial/crisv10.h
View file @ 0242909a
......@@ -10,7 +10,7 @@
#include <linux/circ_buf.h>
#include <asm/termios.h>
#include <asm/dma.h>
#include <asm/arch/io_interface_mux.h>
#include <arch/io_interface_mux.h>
/* Software state per channel */
......
include/asm-cris/arch-v32/arbiter.h deleted 100644 → 0
View file @ 0a6d2fac
#ifndef _ASM_CRIS_ARCH_ARBITER_H
#define _ASM_CRIS_ARCH_ARBITER_H
#define EXT_REGION 0
#define INT_REGION 1
typedef void (watch_callback)(void);
enum
{
arbiter_all_dmas = 0x3ff,
arbiter_cpu = 0xc00,
arbiter_all_clients = 0x3fff
};
enum
{
arbiter_all_read = 0x55,
arbiter_all_write = 0xaa,
arbiter_all_accesses = 0xff
};
int crisv32_arbiter_allocate_bandwidth(int client, int region,
unsigned long bandwidth);
int crisv32_arbiter_watch(unsigned long start, unsigned long size,
unsigned long clients, unsigned long accesses,
watch_callback* cb);
int crisv32_arbiter_unwatch(int id);
#endif
include/asm-cris/arch-v32/hwregs/asm/pinmux_defs_asm.h deleted 100644 → 0
View file @ 0a6d2fac
#ifndef __pinmux_defs_asm_h
#define __pinmux_defs_asm_h
/*
* This file is autogenerated from
* file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r
* id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp
* last modfied: Mon Apr 11 16:09:11 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/pinmux_defs_asm.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r
* id: $Id: pinmux_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#ifndef REG_FIELD
#define REG_FIELD( scope, reg, field, value ) \
REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
#define REG_FIELD_X_( value, shift ) ((value) << shift)
#endif
#ifndef REG_STATE
#define REG_STATE( scope, reg, field, symbolic_value ) \
REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
#define REG_STATE_X_( k, shift ) (k << shift)
#endif
#ifndef REG_MASK
#define REG_MASK( scope, reg, field ) \
REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
#endif
#ifndef REG_LSB
#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
#endif
#ifndef REG_BIT
#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
STRIDE_##scope##_##reg )
#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
((inst) + offs + (index) * stride)
#endif
/* Register rw_pa, scope pinmux, type rw */
#define reg_pinmux_rw_pa___pa0___lsb 0
#define reg_pinmux_rw_pa___pa0___width 1
#define reg_pinmux_rw_pa___pa0___bit 0
#define reg_pinmux_rw_pa___pa1___lsb 1
#define reg_pinmux_rw_pa___pa1___width 1
#define reg_pinmux_rw_pa___pa1___bit 1
#define reg_pinmux_rw_pa___pa2___lsb 2
#define reg_pinmux_rw_pa___pa2___width 1
#define reg_pinmux_rw_pa___pa2___bit 2
#define reg_pinmux_rw_pa___pa3___lsb 3
#define reg_pinmux_rw_pa___pa3___width 1
#define reg_pinmux_rw_pa___pa3___bit 3
#define reg_pinmux_rw_pa___pa4___lsb 4
#define reg_pinmux_rw_pa___pa4___width 1
#define reg_pinmux_rw_pa___pa4___bit 4
#define reg_pinmux_rw_pa___pa5___lsb 5
#define reg_pinmux_rw_pa___pa5___width 1
#define reg_pinmux_rw_pa___pa5___bit 5
#define reg_pinmux_rw_pa___pa6___lsb 6
#define reg_pinmux_rw_pa___pa6___width 1
#define reg_pinmux_rw_pa___pa6___bit 6
#define reg_pinmux_rw_pa___pa7___lsb 7
#define reg_pinmux_rw_pa___pa7___width 1
#define reg_pinmux_rw_pa___pa7___bit 7
#define reg_pinmux_rw_pa___csp2_n___lsb 8
#define reg_pinmux_rw_pa___csp2_n___width 1
#define reg_pinmux_rw_pa___csp2_n___bit 8
#define reg_pinmux_rw_pa___csp3_n___lsb 9
#define reg_pinmux_rw_pa___csp3_n___width 1
#define reg_pinmux_rw_pa___csp3_n___bit 9
#define reg_pinmux_rw_pa___csp5_n___lsb 10
#define reg_pinmux_rw_pa___csp5_n___width 1
#define reg_pinmux_rw_pa___csp5_n___bit 10
#define reg_pinmux_rw_pa___csp6_n___lsb 11
#define reg_pinmux_rw_pa___csp6_n___width 1
#define reg_pinmux_rw_pa___csp6_n___bit 11
#define reg_pinmux_rw_pa___hsh4___lsb 12
#define reg_pinmux_rw_pa___hsh4___width 1
#define reg_pinmux_rw_pa___hsh4___bit 12
#define reg_pinmux_rw_pa___hsh5___lsb 13
#define reg_pinmux_rw_pa___hsh5___width 1
#define reg_pinmux_rw_pa___hsh5___bit 13
#define reg_pinmux_rw_pa___hsh6___lsb 14
#define reg_pinmux_rw_pa___hsh6___width 1
#define reg_pinmux_rw_pa___hsh6___bit 14
#define reg_pinmux_rw_pa___hsh7___lsb 15
#define reg_pinmux_rw_pa___hsh7___width 1
#define reg_pinmux_rw_pa___hsh7___bit 15
#define reg_pinmux_rw_pa_offset 0
/* Register rw_hwprot, scope pinmux, type rw */
#define reg_pinmux_rw_hwprot___ser1___lsb 0
#define reg_pinmux_rw_hwprot___ser1___width 1
#define reg_pinmux_rw_hwprot___ser1___bit 0
#define reg_pinmux_rw_hwprot___ser2___lsb 1
#define reg_pinmux_rw_hwprot___ser2___width 1
#define reg_pinmux_rw_hwprot___ser2___bit 1
#define reg_pinmux_rw_hwprot___ser3___lsb 2
#define reg_pinmux_rw_hwprot___ser3___width 1
#define reg_pinmux_rw_hwprot___ser3___bit 2
#define reg_pinmux_rw_hwprot___sser0___lsb 3
#define reg_pinmux_rw_hwprot___sser0___width 1
#define reg_pinmux_rw_hwprot___sser0___bit 3
#define reg_pinmux_rw_hwprot___sser1___lsb 4
#define reg_pinmux_rw_hwprot___sser1___width 1
#define reg_pinmux_rw_hwprot___sser1___bit 4
#define reg_pinmux_rw_hwprot___ata0___lsb 5
#define reg_pinmux_rw_hwprot___ata0___width 1
#define reg_pinmux_rw_hwprot___ata0___bit 5
#define reg_pinmux_rw_hwprot___ata1___lsb 6
#define reg_pinmux_rw_hwprot___ata1___width 1
#define reg_pinmux_rw_hwprot___ata1___bit 6
#define reg_pinmux_rw_hwprot___ata2___lsb 7
#define reg_pinmux_rw_hwprot___ata2___width 1
#define reg_pinmux_rw_hwprot___ata2___bit 7
#define reg_pinmux_rw_hwprot___ata3___lsb 8
#define reg_pinmux_rw_hwprot___ata3___width 1
#define reg_pinmux_rw_hwprot___ata3___bit 8
#define reg_pinmux_rw_hwprot___ata___lsb 9
#define reg_pinmux_rw_hwprot___ata___width 1
#define reg_pinmux_rw_hwprot___ata___bit 9
#define reg_pinmux_rw_hwprot___eth1___lsb 10
#define reg_pinmux_rw_hwprot___eth1___width 1
#define reg_pinmux_rw_hwprot___eth1___bit 10
#define reg_pinmux_rw_hwprot___eth1_mgm___lsb 11
#define reg_pinmux_rw_hwprot___eth1_mgm___width 1
#define reg_pinmux_rw_hwprot___eth1_mgm___bit 11
#define reg_pinmux_rw_hwprot___timer___lsb 12
#define reg_pinmux_rw_hwprot___timer___width 1
#define reg_pinmux_rw_hwprot___timer___bit 12
#define reg_pinmux_rw_hwprot___p21___lsb 13
#define reg_pinmux_rw_hwprot___p21___width 1
#define reg_pinmux_rw_hwprot___p21___bit 13
#define reg_pinmux_rw_hwprot_offset 4
/* Register rw_pb_gio, scope pinmux, type rw */
#define reg_pinmux_rw_pb_gio___pb0___lsb 0
#define reg_pinmux_rw_pb_gio___pb0___width 1
#define reg_pinmux_rw_pb_gio___pb0___bit 0
#define reg_pinmux_rw_pb_gio___pb1___lsb 1
#define reg_pinmux_rw_pb_gio___pb1___width 1
#define reg_pinmux_rw_pb_gio___pb1___bit 1
#define reg_pinmux_rw_pb_gio___pb2___lsb 2
#define reg_pinmux_rw_pb_gio___pb2___width 1
#define reg_pinmux_rw_pb_gio___pb2___bit 2
#define reg_pinmux_rw_pb_gio___pb3___lsb 3
#define reg_pinmux_rw_pb_gio___pb3___width 1
#define reg_pinmux_rw_pb_gio___pb3___bit 3
#define reg_pinmux_rw_pb_gio___pb4___lsb 4
#define reg_pinmux_rw_pb_gio___pb4___width 1
#define reg_pinmux_rw_pb_gio___pb4___bit 4
#define reg_pinmux_rw_pb_gio___pb5___lsb 5
#define reg_pinmux_rw_pb_gio___pb5___width 1
#define reg_pinmux_rw_pb_gio___pb5___bit 5
#define reg_pinmux_rw_pb_gio___pb6___lsb 6
#define reg_pinmux_rw_pb_gio___pb6___width 1
#define reg_pinmux_rw_pb_gio___pb6___bit 6
#define reg_pinmux_rw_pb_gio___pb7___lsb 7
#define reg_pinmux_rw_pb_gio___pb7___width 1
#define reg_pinmux_rw_pb_gio___pb7___bit 7
#define reg_pinmux_rw_pb_gio___pb8___lsb 8
#define reg_pinmux_rw_pb_gio___pb8___width 1
#define reg_pinmux_rw_pb_gio___pb8___bit 8
#define reg_pinmux_rw_pb_gio___pb9___lsb 9
#define reg_pinmux_rw_pb_gio___pb9___width 1
#define reg_pinmux_rw_pb_gio___pb9___bit 9
#define reg_pinmux_rw_pb_gio___pb10___lsb 10
#define reg_pinmux_rw_pb_gio___pb10___width 1
#define reg_pinmux_rw_pb_gio___pb10___bit 10
#define reg_pinmux_rw_pb_gio___pb11___lsb 11
#define reg_pinmux_rw_pb_gio___pb11___width 1
#define reg_pinmux_rw_pb_gio___pb11___bit 11
#define reg_pinmux_rw_pb_gio___pb12___lsb 12
#define reg_pinmux_rw_pb_gio___pb12___width 1
#define reg_pinmux_rw_pb_gio___pb12___bit 12
#define reg_pinmux_rw_pb_gio___pb13___lsb 13
#define reg_pinmux_rw_pb_gio___pb13___width 1
#define reg_pinmux_rw_pb_gio___pb13___bit 13
#define reg_pinmux_rw_pb_gio___pb14___lsb 14
#define reg_pinmux_rw_pb_gio___pb14___width 1
#define reg_pinmux_rw_pb_gio___pb14___bit 14
#define reg_pinmux_rw_pb_gio___pb15___lsb 15
#define reg_pinmux_rw_pb_gio___pb15___width 1
#define reg_pinmux_rw_pb_gio___pb15___bit 15
#define reg_pinmux_rw_pb_gio___pb16___lsb 16
#define reg_pinmux_rw_pb_gio___pb16___width 1
#define reg_pinmux_rw_pb_gio___pb16___bit 16
#define reg_pinmux_rw_pb_gio___pb17___lsb 17
#define reg_pinmux_rw_pb_gio___pb17___width 1
#define reg_pinmux_rw_pb_gio___pb17___bit 17
#define reg_pinmux_rw_pb_gio_offset 8
/* Register rw_pb_iop, scope pinmux, type rw */
#define reg_pinmux_rw_pb_iop___pb0___lsb 0
#define reg_pinmux_rw_pb_iop___pb0___width 1
#define reg_pinmux_rw_pb_iop___pb0___bit 0
#define reg_pinmux_rw_pb_iop___pb1___lsb 1
#define reg_pinmux_rw_pb_iop___pb1___width 1
#define reg_pinmux_rw_pb_iop___pb1___bit 1
#define reg_pinmux_rw_pb_iop___pb2___lsb 2
#define reg_pinmux_rw_pb_iop___pb2___width 1
#define reg_pinmux_rw_pb_iop___pb2___bit 2
#define reg_pinmux_rw_pb_iop___pb3___lsb 3
#define reg_pinmux_rw_pb_iop___pb3___width 1
#define reg_pinmux_rw_pb_iop___pb3___bit 3
#define reg_pinmux_rw_pb_iop___pb4___lsb 4
#define reg_pinmux_rw_pb_iop___pb4___width 1
#define reg_pinmux_rw_pb_iop___pb4___bit 4
#define reg_pinmux_rw_pb_iop___pb5___lsb 5
#define reg_pinmux_rw_pb_iop___pb5___width 1
#define reg_pinmux_rw_pb_iop___pb5___bit 5
#define reg_pinmux_rw_pb_iop___pb6___lsb 6
#define reg_pinmux_rw_pb_iop___pb6___width 1
#define reg_pinmux_rw_pb_iop___pb6___bit 6
#define reg_pinmux_rw_pb_iop___pb7___lsb 7
#define reg_pinmux_rw_pb_iop___pb7___width 1
#define reg_pinmux_rw_pb_iop___pb7___bit 7
#define reg_pinmux_rw_pb_iop___pb8___lsb 8
#define reg_pinmux_rw_pb_iop___pb8___width 1
#define reg_pinmux_rw_pb_iop___pb8___bit 8
#define reg_pinmux_rw_pb_iop___pb9___lsb 9
#define reg_pinmux_rw_pb_iop___pb9___width 1
#define reg_pinmux_rw_pb_iop___pb9___bit 9
#define reg_pinmux_rw_pb_iop___pb10___lsb 10
#define reg_pinmux_rw_pb_iop___pb10___width 1
#define reg_pinmux_rw_pb_iop___pb10___bit 10
#define reg_pinmux_rw_pb_iop___pb11___lsb 11
#define reg_pinmux_rw_pb_iop___pb11___width 1
#define reg_pinmux_rw_pb_iop___pb11___bit 11
#define reg_pinmux_rw_pb_iop___pb12___lsb 12
#define reg_pinmux_rw_pb_iop___pb12___width 1
#define reg_pinmux_rw_pb_iop___pb12___bit 12
#define reg_pinmux_rw_pb_iop___pb13___lsb 13
#define reg_pinmux_rw_pb_iop___pb13___width 1
#define reg_pinmux_rw_pb_iop___pb13___bit 13
#define reg_pinmux_rw_pb_iop___pb14___lsb 14
#define reg_pinmux_rw_pb_iop___pb14___width 1
#define reg_pinmux_rw_pb_iop___pb14___bit 14
#define reg_pinmux_rw_pb_iop___pb15___lsb 15
#define reg_pinmux_rw_pb_iop___pb15___width 1
#define reg_pinmux_rw_pb_iop___pb15___bit 15
#define reg_pinmux_rw_pb_iop___pb16___lsb 16
#define reg_pinmux_rw_pb_iop___pb16___width 1
#define reg_pinmux_rw_pb_iop___pb16___bit 16
#define reg_pinmux_rw_pb_iop___pb17___lsb 17
#define reg_pinmux_rw_pb_iop___pb17___width 1
#define reg_pinmux_rw_pb_iop___pb17___bit 17
#define reg_pinmux_rw_pb_iop_offset 12
/* Register rw_pc_gio, scope pinmux, type rw */
#define reg_pinmux_rw_pc_gio___pc0___lsb 0
#define reg_pinmux_rw_pc_gio___pc0___width 1
#define reg_pinmux_rw_pc_gio___pc0___bit 0
#define reg_pinmux_rw_pc_gio___pc1___lsb 1
#define reg_pinmux_rw_pc_gio___pc1___width 1
#define reg_pinmux_rw_pc_gio___pc1___bit 1
#define reg_pinmux_rw_pc_gio___pc2___lsb 2
#define reg_pinmux_rw_pc_gio___pc2___width 1
#define reg_pinmux_rw_pc_gio___pc2___bit 2
#define reg_pinmux_rw_pc_gio___pc3___lsb 3
#define reg_pinmux_rw_pc_gio___pc3___width 1
#define reg_pinmux_rw_pc_gio___pc3___bit 3
#define reg_pinmux_rw_pc_gio___pc4___lsb 4
#define reg_pinmux_rw_pc_gio___pc4___width 1
#define reg_pinmux_rw_pc_gio___pc4___bit 4
#define reg_pinmux_rw_pc_gio___pc5___lsb 5
#define reg_pinmux_rw_pc_gio___pc5___width 1
#define reg_pinmux_rw_pc_gio___pc5___bit 5
#define reg_pinmux_rw_pc_gio___pc6___lsb 6
#define reg_pinmux_rw_pc_gio___pc6___width 1
#define reg_pinmux_rw_pc_gio___pc6___bit 6
#define reg_pinmux_rw_pc_gio___pc7___lsb 7
#define reg_pinmux_rw_pc_gio___pc7___width 1
#define reg_pinmux_rw_pc_gio___pc7___bit 7
#define reg_pinmux_rw_pc_gio___pc8___lsb 8
#define reg_pinmux_rw_pc_gio___pc8___width 1
#define reg_pinmux_rw_pc_gio___pc8___bit 8
#define reg_pinmux_rw_pc_gio___pc9___lsb 9
#define reg_pinmux_rw_pc_gio___pc9___width 1
#define reg_pinmux_rw_pc_gio___pc9___bit 9
#define reg_pinmux_rw_pc_gio___pc10___lsb 10
#define reg_pinmux_rw_pc_gio___pc10___width 1
#define reg_pinmux_rw_pc_gio___pc10___bit 10
#define reg_pinmux_rw_pc_gio___pc11___lsb 11
#define reg_pinmux_rw_pc_gio___pc11___width 1
#define reg_pinmux_rw_pc_gio___pc11___bit 11
#define reg_pinmux_rw_pc_gio___pc12___lsb 12
#define reg_pinmux_rw_pc_gio___pc12___width 1
#define reg_pinmux_rw_pc_gio___pc12___bit 12
#define reg_pinmux_rw_pc_gio___pc13___lsb 13
#define reg_pinmux_rw_pc_gio___pc13___width 1
#define reg_pinmux_rw_pc_gio___pc13___bit 13
#define reg_pinmux_rw_pc_gio___pc14___lsb 14
#define reg_pinmux_rw_pc_gio___pc14___width 1
#define reg_pinmux_rw_pc_gio___pc14___bit 14
#define reg_pinmux_rw_pc_gio___pc15___lsb 15
#define reg_pinmux_rw_pc_gio___pc15___width 1
#define reg_pinmux_rw_pc_gio___pc15___bit 15
#define reg_pinmux_rw_pc_gio___pc16___lsb 16
#define reg_pinmux_rw_pc_gio___pc16___width 1
#define reg_pinmux_rw_pc_gio___pc16___bit 16
#define reg_pinmux_rw_pc_gio___pc17___lsb 17
#define reg_pinmux_rw_pc_gio___pc17___width 1
#define reg_pinmux_rw_pc_gio___pc17___bit 17
#define reg_pinmux_rw_pc_gio_offset 16
/* Register rw_pc_iop, scope pinmux, type rw */
#define reg_pinmux_rw_pc_iop___pc0___lsb 0
#define reg_pinmux_rw_pc_iop___pc0___width 1
#define reg_pinmux_rw_pc_iop___pc0___bit 0
#define reg_pinmux_rw_pc_iop___pc1___lsb 1
#define reg_pinmux_rw_pc_iop___pc1___width 1
#define reg_pinmux_rw_pc_iop___pc1___bit 1
#define reg_pinmux_rw_pc_iop___pc2___lsb 2
#define reg_pinmux_rw_pc_iop___pc2___width 1
#define reg_pinmux_rw_pc_iop___pc2___bit 2
#define reg_pinmux_rw_pc_iop___pc3___lsb 3
#define reg_pinmux_rw_pc_iop___pc3___width 1
#define reg_pinmux_rw_pc_iop___pc3___bit 3
#define reg_pinmux_rw_pc_iop___pc4___lsb 4
#define reg_pinmux_rw_pc_iop___pc4___width 1
#define reg_pinmux_rw_pc_iop___pc4___bit 4
#define reg_pinmux_rw_pc_iop___pc5___lsb 5
#define reg_pinmux_rw_pc_iop___pc5___width 1
#define reg_pinmux_rw_pc_iop___pc5___bit 5
#define reg_pinmux_rw_pc_iop___pc6___lsb 6
#define reg_pinmux_rw_pc_iop___pc6___width 1
#define reg_pinmux_rw_pc_iop___pc6___bit 6
#define reg_pinmux_rw_pc_iop___pc7___lsb 7
#define reg_pinmux_rw_pc_iop___pc7___width 1
#define reg_pinmux_rw_pc_iop___pc7___bit 7
#define reg_pinmux_rw_pc_iop___pc8___lsb 8
#define reg_pinmux_rw_pc_iop___pc8___width 1
#define reg_pinmux_rw_pc_iop___pc8___bit 8
#define reg_pinmux_rw_pc_iop___pc9___lsb 9
#define reg_pinmux_rw_pc_iop___pc9___width 1
#define reg_pinmux_rw_pc_iop___pc9___bit 9
#define reg_pinmux_rw_pc_iop___pc10___lsb 10
#define reg_pinmux_rw_pc_iop___pc10___width 1
#define reg_pinmux_rw_pc_iop___pc10___bit 10
#define reg_pinmux_rw_pc_iop___pc11___lsb 11
#define reg_pinmux_rw_pc_iop___pc11___width 1
#define reg_pinmux_rw_pc_iop___pc11___bit 11
#define reg_pinmux_rw_pc_iop___pc12___lsb 12
#define reg_pinmux_rw_pc_iop___pc12___width 1
#define reg_pinmux_rw_pc_iop___pc12___bit 12
#define reg_pinmux_rw_pc_iop___pc13___lsb 13
#define reg_pinmux_rw_pc_iop___pc13___width 1
#define reg_pinmux_rw_pc_iop___pc13___bit 13
#define reg_pinmux_rw_pc_iop___pc14___lsb 14
#define reg_pinmux_rw_pc_iop___pc14___width 1
#define reg_pinmux_rw_pc_iop___pc14___bit 14
#define reg_pinmux_rw_pc_iop___pc15___lsb 15
#define reg_pinmux_rw_pc_iop___pc15___width 1
#define reg_pinmux_rw_pc_iop___pc15___bit 15
#define reg_pinmux_rw_pc_iop___pc16___lsb 16
#define reg_pinmux_rw_pc_iop___pc16___width 1
#define reg_pinmux_rw_pc_iop___pc16___bit 16
#define reg_pinmux_rw_pc_iop___pc17___lsb 17
#define reg_pinmux_rw_pc_iop___pc17___width 1
#define reg_pinmux_rw_pc_iop___pc17___bit 17
#define reg_pinmux_rw_pc_iop_offset 20
/* Register rw_pd_gio, scope pinmux, type rw */
#define reg_pinmux_rw_pd_gio___pd0___lsb 0
#define reg_pinmux_rw_pd_gio___pd0___width 1
#define reg_pinmux_rw_pd_gio___pd0___bit 0
#define reg_pinmux_rw_pd_gio___pd1___lsb 1
#define reg_pinmux_rw_pd_gio___pd1___width 1
#define reg_pinmux_rw_pd_gio___pd1___bit 1
#define reg_pinmux_rw_pd_gio___pd2___lsb 2
#define reg_pinmux_rw_pd_gio___pd2___width 1
#define reg_pinmux_rw_pd_gio___pd2___bit 2
#define reg_pinmux_rw_pd_gio___pd3___lsb 3
#define reg_pinmux_rw_pd_gio___pd3___width 1
#define reg_pinmux_rw_pd_gio___pd3___bit 3
#define reg_pinmux_rw_pd_gio___pd4___lsb 4
#define reg_pinmux_rw_pd_gio___pd4___width 1
#define reg_pinmux_rw_pd_gio___pd4___bit 4
#define reg_pinmux_rw_pd_gio___pd5___lsb 5
#define reg_pinmux_rw_pd_gio___pd5___width 1
#define reg_pinmux_rw_pd_gio___pd5___bit 5
#define reg_pinmux_rw_pd_gio___pd6___lsb 6
#define reg_pinmux_rw_pd_gio___pd6___width 1
#define reg_pinmux_rw_pd_gio___pd6___bit 6
#define reg_pinmux_rw_pd_gio___pd7___lsb 7
#define reg_pinmux_rw_pd_gio___pd7___width 1
#define reg_pinmux_rw_pd_gio___pd7___bit 7
#define reg_pinmux_rw_pd_gio___pd8___lsb 8
#define reg_pinmux_rw_pd_gio___pd8___width 1
#define reg_pinmux_rw_pd_gio___pd8___bit 8
#define reg_pinmux_rw_pd_gio___pd9___lsb 9
#define reg_pinmux_rw_pd_gio___pd9___width 1
#define reg_pinmux_rw_pd_gio___pd9___bit 9
#define reg_pinmux_rw_pd_gio___pd10___lsb 10
#define reg_pinmux_rw_pd_gio___pd10___width 1
#define reg_pinmux_rw_pd_gio___pd10___bit 10
#define reg_pinmux_rw_pd_gio___pd11___lsb 11
#define reg_pinmux_rw_pd_gio___pd11___width 1
#define reg_pinmux_rw_pd_gio___pd11___bit 11
#define reg_pinmux_rw_pd_gio___pd12___lsb 12
#define reg_pinmux_rw_pd_gio___pd12___width 1
#define reg_pinmux_rw_pd_gio___pd12___bit 12
#define reg_pinmux_rw_pd_gio___pd13___lsb 13
#define reg_pinmux_rw_pd_gio___pd13___width 1
#define reg_pinmux_rw_pd_gio___pd13___bit 13
#define reg_pinmux_rw_pd_gio___pd14___lsb 14
#define reg_pinmux_rw_pd_gio___pd14___width 1
#define reg_pinmux_rw_pd_gio___pd14___bit 14
#define reg_pinmux_rw_pd_gio___pd15___lsb 15
#define reg_pinmux_rw_pd_gio___pd15___width 1
#define reg_pinmux_rw_pd_gio___pd15___bit 15
#define reg_pinmux_rw_pd_gio___pd16___lsb 16
#define reg_pinmux_rw_pd_gio___pd16___width 1
#define reg_pinmux_rw_pd_gio___pd16___bit 16
#define reg_pinmux_rw_pd_gio___pd17___lsb 17
#define reg_pinmux_rw_pd_gio___pd17___width 1
#define reg_pinmux_rw_pd_gio___pd17___bit 17
#define reg_pinmux_rw_pd_gio_offset 24
/* Register rw_pd_iop, scope pinmux, type rw */
#define reg_pinmux_rw_pd_iop___pd0___lsb 0
#define reg_pinmux_rw_pd_iop___pd0___width 1
#define reg_pinmux_rw_pd_iop___pd0___bit 0
#define reg_pinmux_rw_pd_iop___pd1___lsb 1
#define reg_pinmux_rw_pd_iop___pd1___width 1
#define reg_pinmux_rw_pd_iop___pd1___bit 1
#define reg_pinmux_rw_pd_iop___pd2___lsb 2
#define reg_pinmux_rw_pd_iop___pd2___width 1
#define reg_pinmux_rw_pd_iop___pd2___bit 2
#define reg_pinmux_rw_pd_iop___pd3___lsb 3
#define reg_pinmux_rw_pd_iop___pd3___width 1
#define reg_pinmux_rw_pd_iop___pd3___bit 3
#define reg_pinmux_rw_pd_iop___pd4___lsb 4
#define reg_pinmux_rw_pd_iop___pd4___width 1
#define reg_pinmux_rw_pd_iop___pd4___bit 4
#define reg_pinmux_rw_pd_iop___pd5___lsb 5
#define reg_pinmux_rw_pd_iop___pd5___width 1
#define reg_pinmux_rw_pd_iop___pd5___bit 5
#define reg_pinmux_rw_pd_iop___pd6___lsb 6
#define reg_pinmux_rw_pd_iop___pd6___width 1
#define reg_pinmux_rw_pd_iop___pd6___bit 6
#define reg_pinmux_rw_pd_iop___pd7___lsb 7
#define reg_pinmux_rw_pd_iop___pd7___width 1
#define reg_pinmux_rw_pd_iop___pd7___bit 7
#define reg_pinmux_rw_pd_iop___pd8___lsb 8
#define reg_pinmux_rw_pd_iop___pd8___width 1
#define reg_pinmux_rw_pd_iop___pd8___bit 8
#define reg_pinmux_rw_pd_iop___pd9___lsb 9
#define reg_pinmux_rw_pd_iop___pd9___width 1
#define reg_pinmux_rw_pd_iop___pd9___bit 9
#define reg_pinmux_rw_pd_iop___pd10___lsb 10
#define reg_pinmux_rw_pd_iop___pd10___width 1
#define reg_pinmux_rw_pd_iop___pd10___bit 10
#define reg_pinmux_rw_pd_iop___pd11___lsb 11
#define reg_pinmux_rw_pd_iop___pd11___width 1
#define reg_pinmux_rw_pd_iop___pd11___bit 11
#define reg_pinmux_rw_pd_iop___pd12___lsb 12
#define reg_pinmux_rw_pd_iop___pd12___width 1
#define reg_pinmux_rw_pd_iop___pd12___bit 12
#define reg_pinmux_rw_pd_iop___pd13___lsb 13
#define reg_pinmux_rw_pd_iop___pd13___width 1
#define reg_pinmux_rw_pd_iop___pd13___bit 13
#define reg_pinmux_rw_pd_iop___pd14___lsb 14
#define reg_pinmux_rw_pd_iop___pd14___width 1
#define reg_pinmux_rw_pd_iop___pd14___bit 14
#define reg_pinmux_rw_pd_iop___pd15___lsb 15
#define reg_pinmux_rw_pd_iop___pd15___width 1
#define reg_pinmux_rw_pd_iop___pd15___bit 15
#define reg_pinmux_rw_pd_iop___pd16___lsb 16
#define reg_pinmux_rw_pd_iop___pd16___width 1
#define reg_pinmux_rw_pd_iop___pd16___bit 16
#define reg_pinmux_rw_pd_iop___pd17___lsb 17
#define reg_pinmux_rw_pd_iop___pd17___width 1
#define reg_pinmux_rw_pd_iop___pd17___bit 17
#define reg_pinmux_rw_pd_iop_offset 28
/* Register rw_pe_gio, scope pinmux, type rw */
#define reg_pinmux_rw_pe_gio___pe0___lsb 0
#define reg_pinmux_rw_pe_gio___pe0___width 1
#define reg_pinmux_rw_pe_gio___pe0___bit 0
#define reg_pinmux_rw_pe_gio___pe1___lsb 1
#define reg_pinmux_rw_pe_gio___pe1___width 1
#define reg_pinmux_rw_pe_gio___pe1___bit 1
#define reg_pinmux_rw_pe_gio___pe2___lsb 2
#define reg_pinmux_rw_pe_gio___pe2___width 1
#define reg_pinmux_rw_pe_gio___pe2___bit 2
#define reg_pinmux_rw_pe_gio___pe3___lsb 3
#define reg_pinmux_rw_pe_gio___pe3___width 1
#define reg_pinmux_rw_pe_gio___pe3___bit 3
#define reg_pinmux_rw_pe_gio___pe4___lsb 4
#define reg_pinmux_rw_pe_gio___pe4___width 1
#define reg_pinmux_rw_pe_gio___pe4___bit 4
#define reg_pinmux_rw_pe_gio___pe5___lsb 5
#define reg_pinmux_rw_pe_gio___pe5___width 1
#define reg_pinmux_rw_pe_gio___pe5___bit 5
#define reg_pinmux_rw_pe_gio___pe6___lsb 6
#define reg_pinmux_rw_pe_gio___pe6___width 1
#define reg_pinmux_rw_pe_gio___pe6___bit 6
#define reg_pinmux_rw_pe_gio___pe7___lsb 7
#define reg_pinmux_rw_pe_gio___pe7___width 1
#define reg_pinmux_rw_pe_gio___pe7___bit 7
#define reg_pinmux_rw_pe_gio___pe8___lsb 8
#define reg_pinmux_rw_pe_gio___pe8___width 1
#define reg_pinmux_rw_pe_gio___pe8___bit 8
#define reg_pinmux_rw_pe_gio___pe9___lsb 9
#define reg_pinmux_rw_pe_gio___pe9___width 1
#define reg_pinmux_rw_pe_gio___pe9___bit 9
#define reg_pinmux_rw_pe_gio___pe10___lsb 10
#define reg_pinmux_rw_pe_gio___pe10___width 1
#define reg_pinmux_rw_pe_gio___pe10___bit 10
#define reg_pinmux_rw_pe_gio___pe11___lsb 11
#define reg_pinmux_rw_pe_gio___pe11___width 1
#define reg_pinmux_rw_pe_gio___pe11___bit 11
#define reg_pinmux_rw_pe_gio___pe12___lsb 12
#define reg_pinmux_rw_pe_gio___pe12___width 1
#define reg_pinmux_rw_pe_gio___pe12___bit 12
#define reg_pinmux_rw_pe_gio___pe13___lsb 13
#define reg_pinmux_rw_pe_gio___pe13___width 1
#define reg_pinmux_rw_pe_gio___pe13___bit 13
#define reg_pinmux_rw_pe_gio___pe14___lsb 14
#define reg_pinmux_rw_pe_gio___pe14___width 1
#define reg_pinmux_rw_pe_gio___pe14___bit 14
#define reg_pinmux_rw_pe_gio___pe15___lsb 15
#define reg_pinmux_rw_pe_gio___pe15___width 1
#define reg_pinmux_rw_pe_gio___pe15___bit 15
#define reg_pinmux_rw_pe_gio___pe16___lsb 16
#define reg_pinmux_rw_pe_gio___pe16___width 1
#define reg_pinmux_rw_pe_gio___pe16___bit 16
#define reg_pinmux_rw_pe_gio___pe17___lsb 17
#define reg_pinmux_rw_pe_gio___pe17___width 1
#define reg_pinmux_rw_pe_gio___pe17___bit 17
#define reg_pinmux_rw_pe_gio_offset 32
/* Register rw_pe_iop, scope pinmux, type rw */
#define reg_pinmux_rw_pe_iop___pe0___lsb 0
#define reg_pinmux_rw_pe_iop___pe0___width 1
#define reg_pinmux_rw_pe_iop___pe0___bit 0
#define reg_pinmux_rw_pe_iop___pe1___lsb 1
#define reg_pinmux_rw_pe_iop___pe1___width 1
#define reg_pinmux_rw_pe_iop___pe1___bit 1
#define reg_pinmux_rw_pe_iop___pe2___lsb 2
#define reg_pinmux_rw_pe_iop___pe2___width 1
#define reg_pinmux_rw_pe_iop___pe2___bit 2
#define reg_pinmux_rw_pe_iop___pe3___lsb 3
#define reg_pinmux_rw_pe_iop___pe3___width 1
#define reg_pinmux_rw_pe_iop___pe3___bit 3
#define reg_pinmux_rw_pe_iop___pe4___lsb 4
#define reg_pinmux_rw_pe_iop___pe4___width 1
#define reg_pinmux_rw_pe_iop___pe4___bit 4
#define reg_pinmux_rw_pe_iop___pe5___lsb 5
#define reg_pinmux_rw_pe_iop___pe5___width 1
#define reg_pinmux_rw_pe_iop___pe5___bit 5
#define reg_pinmux_rw_pe_iop___pe6___lsb 6
#define reg_pinmux_rw_pe_iop___pe6___width 1
#define reg_pinmux_rw_pe_iop___pe6___bit 6
#define reg_pinmux_rw_pe_iop___pe7___lsb 7
#define reg_pinmux_rw_pe_iop___pe7___width 1
#define reg_pinmux_rw_pe_iop___pe7___bit 7
#define reg_pinmux_rw_pe_iop___pe8___lsb 8
#define reg_pinmux_rw_pe_iop___pe8___width 1
#define reg_pinmux_rw_pe_iop___pe8___bit 8
#define reg_pinmux_rw_pe_iop___pe9___lsb 9
#define reg_pinmux_rw_pe_iop___pe9___width 1
#define reg_pinmux_rw_pe_iop___pe9___bit 9
#define reg_pinmux_rw_pe_iop___pe10___lsb 10
#define reg_pinmux_rw_pe_iop___pe10___width 1
#define reg_pinmux_rw_pe_iop___pe10___bit 10
#define reg_pinmux_rw_pe_iop___pe11___lsb 11
#define reg_pinmux_rw_pe_iop___pe11___width 1
#define reg_pinmux_rw_pe_iop___pe11___bit 11
#define reg_pinmux_rw_pe_iop___pe12___lsb 12
#define reg_pinmux_rw_pe_iop___pe12___width 1
#define reg_pinmux_rw_pe_iop___pe12___bit 12
#define reg_pinmux_rw_pe_iop___pe13___lsb 13
#define reg_pinmux_rw_pe_iop___pe13___width 1
#define reg_pinmux_rw_pe_iop___pe13___bit 13
#define reg_pinmux_rw_pe_iop___pe14___lsb 14
#define reg_pinmux_rw_pe_iop___pe14___width 1
#define reg_pinmux_rw_pe_iop___pe14___bit 14
#define reg_pinmux_rw_pe_iop___pe15___lsb 15
#define reg_pinmux_rw_pe_iop___pe15___width 1
#define reg_pinmux_rw_pe_iop___pe15___bit 15
#define reg_pinmux_rw_pe_iop___pe16___lsb 16
#define reg_pinmux_rw_pe_iop___pe16___width 1
#define reg_pinmux_rw_pe_iop___pe16___bit 16
#define reg_pinmux_rw_pe_iop___pe17___lsb 17
#define reg_pinmux_rw_pe_iop___pe17___width 1
#define reg_pinmux_rw_pe_iop___pe17___bit 17
#define reg_pinmux_rw_pe_iop_offset 36
/* Register rw_usb_phy, scope pinmux, type rw */
#define reg_pinmux_rw_usb_phy___en_usb0___lsb 0
#define reg_pinmux_rw_usb_phy___en_usb0___width 1
#define reg_pinmux_rw_usb_phy___en_usb0___bit 0
#define reg_pinmux_rw_usb_phy___en_usb1___lsb 1
#define reg_pinmux_rw_usb_phy___en_usb1___width 1
#define reg_pinmux_rw_usb_phy___en_usb1___bit 1
#define reg_pinmux_rw_usb_phy_offset 40
/* Constants */
#define regk_pinmux_no 0x00000000
#define regk_pinmux_rw_hwprot_default 0x00000000
#define regk_pinmux_rw_pa_default 0x00000000
#define regk_pinmux_rw_pb_gio_default 0x00000000
#define regk_pinmux_rw_pb_iop_default 0x00000000
#define regk_pinmux_rw_pc_gio_default 0x00000000
#define regk_pinmux_rw_pc_iop_default 0x00000000
#define regk_pinmux_rw_pd_gio_default 0x00000000
#define regk_pinmux_rw_pd_iop_default 0x00000000
#define regk_pinmux_rw_pe_gio_default 0x00000000
#define regk_pinmux_rw_pe_iop_default 0x00000000
#define regk_pinmux_rw_usb_phy_default 0x00000000
#define regk_pinmux_yes 0x00000001
#endif /* __pinmux_defs_asm_h */
include/asm-cris/arch-v32/hwregs/asm/reg_map_asm.h deleted 100644 → 0
View file @ 0a6d2fac
#ifndef __reg_map_h
#define __reg_map_h
/*
* This file is autogenerated from
* file: ../../mod/fakereg.rmap
* id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp
* last modified: Wed Feb 11 20:53:25 2004
* file: ../../rtl/global.rmap
* id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp
* last modified: Mon Aug 18 17:08:23 2003
* file: ../../mod/modreg.rmap
* id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp
* last modified: Fri Feb 20 16:40:04 2004
*
* by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/reg_map_asm.h -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap
* id: $Id: reg_map_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
#define regi_artpec_mod 0xb7044000
#define regi_ata 0xb0032000
#define regi_ata_mod 0xb7006000
#define regi_barber 0xb701a000
#define regi_bif_core 0xb0014000
#define regi_bif_dma 0xb0016000
#define regi_bif_slave 0xb0018000
#define regi_bif_slave_ext 0xac000000
#define regi_bus_master 0xb703c000
#define regi_config 0xb003c000
#define regi_dma0 0xb0000000
#define regi_dma1 0xb0002000
#define regi_dma2 0xb0004000
#define regi_dma3 0xb0006000
#define regi_dma4 0xb0008000
#define regi_dma5 0xb000a000
#define regi_dma6 0xb000c000
#define regi_dma7 0xb000e000
#define regi_dma8 0xb0010000
#define regi_dma9 0xb0012000
#define regi_eth0 0xb0034000
#define regi_eth1 0xb0036000
#define regi_eth_mod 0xb7004000
#define regi_eth_mod1 0xb701c000
#define regi_eth_strmod 0xb7008000
#define regi_eth_strmod1 0xb7032000
#define regi_ext_dma 0xb703a000
#define regi_ext_mem 0xb7046000
#define regi_gen_io 0xb7016000
#define regi_gio 0xb001a000
#define regi_hook 0xb7000000
#define regi_iop 0xb0020000
#define regi_irq 0xb001c000
#define regi_irq_nmi 0xb701e000
#define regi_marb 0xb003e000
#define regi_marb_bp0 0xb003e240
#define regi_marb_bp1 0xb003e280
#define regi_marb_bp2 0xb003e2c0
#define regi_marb_bp3 0xb003e300
#define regi_nand_mod 0xb7014000
#define regi_p21 0xb002e000
#define regi_p21_mod 0xb7042000
#define regi_pci_mod 0xb7010000
#define regi_pin_test 0xb7018000
#define regi_pinmux 0xb0038000
#define regi_sdram_chk 0xb703e000
#define regi_sdram_mod 0xb7012000
#define regi_ser0 0xb0026000
#define regi_ser1 0xb0028000
#define regi_ser2 0xb002a000
#define regi_ser3 0xb002c000
#define regi_ser_mod0 0xb7020000
#define regi_ser_mod1 0xb7022000
#define regi_ser_mod2 0xb7024000
#define regi_ser_mod3 0xb7026000
#define regi_smif_stat 0xb700e000
#define regi_sser0 0xb0022000
#define regi_sser1 0xb0024000
#define regi_sser_mod0 0xb700a000
#define regi_sser_mod1 0xb700c000
#define regi_strcop 0xb0030000
#define regi_strmux 0xb003a000
#define regi_strmux_tst 0xb7040000
#define regi_tap 0xb7002000
#define regi_timer 0xb001e000
#define regi_timer_mod 0xb7034000
#define regi_trace 0xb0040000
#define regi_usb0 0xb7028000
#define regi_usb1 0xb702a000
#define regi_usb2 0xb702c000
#define regi_usb3 0xb702e000
#define regi_usb_dev 0xb7030000
#define regi_utmi_mod0 0xb7036000
#define regi_utmi_mod1 0xb7038000
#endif /* __reg_map_h */
include/asm-cris/arch-v32/hwregs/gio_defs.h deleted 100644 → 0
View file @ 0a6d2fac
#ifndef __gio_defs_h
#define __gio_defs_h
/*
* This file is autogenerated from
* file: ../../inst/gio/rtl/gio_regs.r
* id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp
* last modfied: Mon Apr 11 16:07:47 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile gio_defs.h ../../inst/gio/rtl/gio_regs.r
* id: $Id: gio_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope gio */
/* Register rw_pa_dout, scope gio, type rw */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_gio_rw_pa_dout;
#define REG_RD_ADDR_gio_rw_pa_dout 0
#define REG_WR_ADDR_gio_rw_pa_dout 0
/* Register r_pa_din, scope gio, type r */
typedef struct {
unsigned int data : 8;
unsigned int dummy1 : 24;
} reg_gio_r_pa_din;
#define REG_RD_ADDR_gio_r_pa_din 4
/* Register rw_pa_oe, scope gio, type rw */
typedef struct {
unsigned int oe : 8;
unsigned int dummy1 : 24;
} reg_gio_rw_pa_oe;
#define REG_RD_ADDR_gio_rw_pa_oe 8
#define REG_WR_ADDR_gio_rw_pa_oe 8
/* Register rw_intr_cfg, scope gio, type rw */
typedef struct {
unsigned int pa0 : 3;
unsigned int pa1 : 3;
unsigned int pa2 : 3;
unsigned int pa3 : 3;
unsigned int pa4 : 3;
unsigned int pa5 : 3;
unsigned int pa6 : 3;
unsigned int pa7 : 3;
unsigned int dummy1 : 8;
} reg_gio_rw_intr_cfg;
#define REG_RD_ADDR_gio_rw_intr_cfg 12
#define REG_WR_ADDR_gio_rw_intr_cfg 12
/* Register rw_intr_mask, scope gio, type rw */
typedef struct {
unsigned int pa0 : 1;
unsigned int pa1 : 1;
unsigned int pa2 : 1;
unsigned int pa3 : 1;
unsigned int pa4 : 1;
unsigned int pa5 : 1;
unsigned int pa6 : 1;
unsigned int pa7 : 1;
unsigned int dummy1 : 24;
} reg_gio_rw_intr_mask;
#define REG_RD_ADDR_gio_rw_intr_mask 16
#define REG_WR_ADDR_gio_rw_intr_mask 16
/* Register rw_ack_intr, scope gio, type rw */
typedef struct {
unsigned int pa0 : 1;
unsigned int pa1 : 1;
unsigned int pa2 : 1;
unsigned int pa3 : 1;
unsigned int pa4 : 1;
unsigned int pa5 : 1;
unsigned int pa6 : 1;
unsigned int pa7 : 1;
unsigned int dummy1 : 24;
} reg_gio_rw_ack_intr;
#define REG_RD_ADDR_gio_rw_ack_intr 20
#define REG_WR_ADDR_gio_rw_ack_intr 20
/* Register r_intr, scope gio, type r */
typedef struct {
unsigned int pa0 : 1;
unsigned int pa1 : 1;
unsigned int pa2 : 1;
unsigned int pa3 : 1;
unsigned int pa4 : 1;
unsigned int pa5 : 1;
unsigned int pa6 : 1;
unsigned int pa7 : 1;
unsigned int dummy1 : 24;
} reg_gio_r_intr;
#define REG_RD_ADDR_gio_r_intr 24
/* Register r_masked_intr, scope gio, type r */
typedef struct {
unsigned int pa0 : 1;
unsigned int pa1 : 1;
unsigned int pa2 : 1;
unsigned int pa3 : 1;
unsigned int pa4 : 1;
unsigned int pa5 : 1;
unsigned int pa6 : 1;
unsigned int pa7 : 1;
unsigned int dummy1 : 24;
} reg_gio_r_masked_intr;
#define REG_RD_ADDR_gio_r_masked_intr 28
/* Register rw_pb_dout, scope gio, type rw */
typedef struct {
unsigned int data : 18;
unsigned int dummy1 : 14;
} reg_gio_rw_pb_dout;
#define REG_RD_ADDR_gio_rw_pb_dout 32
#define REG_WR_ADDR_gio_rw_pb_dout 32
/* Register r_pb_din, scope gio, type r */
typedef struct {
unsigned int data : 18;
unsigned int dummy1 : 14;
} reg_gio_r_pb_din;
#define REG_RD_ADDR_gio_r_pb_din 36
/* Register rw_pb_oe, scope gio, type rw */
typedef struct {
unsigned int oe : 18;
unsigned int dummy1 : 14;
} reg_gio_rw_pb_oe;
#define REG_RD_ADDR_gio_rw_pb_oe 40
#define REG_WR_ADDR_gio_rw_pb_oe 40
/* Register rw_pc_dout, scope gio, type rw */
typedef struct {
unsigned int data : 18;
unsigned int dummy1 : 14;
} reg_gio_rw_pc_dout;
#define REG_RD_ADDR_gio_rw_pc_dout 48
#define REG_WR_ADDR_gio_rw_pc_dout 48
/* Register r_pc_din, scope gio, type r */
typedef struct {
unsigned int data : 18;
unsigned int dummy1 : 14;
} reg_gio_r_pc_din;
#define REG_RD_ADDR_gio_r_pc_din 52
/* Register rw_pc_oe, scope gio, type rw */
typedef struct {
unsigned int oe : 18;
unsigned int dummy1 : 14;
} reg_gio_rw_pc_oe;
#define REG_RD_ADDR_gio_rw_pc_oe 56
#define REG_WR_ADDR_gio_rw_pc_oe 56
/* Register rw_pd_dout, scope gio, type rw */
typedef struct {
unsigned int data : 18;
unsigned int dummy1 : 14;
} reg_gio_rw_pd_dout;
#define REG_RD_ADDR_gio_rw_pd_dout 64
#define REG_WR_ADDR_gio_rw_pd_dout 64
/* Register r_pd_din, scope gio, type r */
typedef struct {
unsigned int data : 18;
unsigned int dummy1 : 14;
} reg_gio_r_pd_din;
#define REG_RD_ADDR_gio_r_pd_din 68
/* Register rw_pd_oe, scope gio, type rw */
typedef struct {
unsigned int oe : 18;
unsigned int dummy1 : 14;
} reg_gio_rw_pd_oe;
#define REG_RD_ADDR_gio_rw_pd_oe 72
#define REG_WR_ADDR_gio_rw_pd_oe 72
/* Register rw_pe_dout, scope gio, type rw */
typedef struct {
unsigned int data : 18;
unsigned int dummy1 : 14;
} reg_gio_rw_pe_dout;
#define REG_RD_ADDR_gio_rw_pe_dout 80
#define REG_WR_ADDR_gio_rw_pe_dout 80
/* Register r_pe_din, scope gio, type r */
typedef struct {
unsigned int data : 18;
unsigned int dummy1 : 14;
} reg_gio_r_pe_din;
#define REG_RD_ADDR_gio_r_pe_din 84
/* Register rw_pe_oe, scope gio, type rw */
typedef struct {
unsigned int oe : 18;
unsigned int dummy1 : 14;
} reg_gio_rw_pe_oe;
#define REG_RD_ADDR_gio_rw_pe_oe 88
#define REG_WR_ADDR_gio_rw_pe_oe 88
/* Constants */
enum {
regk_gio_anyedge = 0x00000007,
regk_gio_hi = 0x00000001,
regk_gio_lo = 0x00000002,
regk_gio_negedge = 0x00000006,
regk_gio_no = 0x00000000,
regk_gio_off = 0x00000000,
regk_gio_posedge = 0x00000005,
regk_gio_rw_intr_cfg_default = 0x00000000,
regk_gio_rw_intr_mask_default = 0x00000000,
regk_gio_rw_pa_oe_default = 0x00000000,
regk_gio_rw_pb_oe_default = 0x00000000,
regk_gio_rw_pc_oe_default = 0x00000000,
regk_gio_rw_pd_oe_default = 0x00000000,
regk_gio_rw_pe_oe_default = 0x00000000,
regk_gio_set = 0x00000003,
regk_gio_yes = 0x00000001
};
#endif /* __gio_defs_h */
include/asm-cris/arch-v32/hwregs/intr_vect.h deleted 100644 → 0
View file @ 0a6d2fac
/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
from ../../inst/intr_vect/rtl/guinness/ivmask.config.r
version . */
#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
#define MEMARB_INTR_VECT 0x31
#define GEN_IO_INTR_VECT 0x32
#define IOP0_INTR_VECT 0x33
#define IOP1_INTR_VECT 0x34
#define IOP2_INTR_VECT 0x35
#define IOP3_INTR_VECT 0x36
#define DMA0_INTR_VECT 0x37
#define DMA1_INTR_VECT 0x38
#define DMA2_INTR_VECT 0x39
#define DMA3_INTR_VECT 0x3a
#define DMA4_INTR_VECT 0x3b
#define DMA5_INTR_VECT 0x3c
#define DMA6_INTR_VECT 0x3d
#define DMA7_INTR_VECT 0x3e
#define DMA8_INTR_VECT 0x3f
#define DMA9_INTR_VECT 0x40
#define ATA_INTR_VECT 0x41
#define SSER0_INTR_VECT 0x42
#define SSER1_INTR_VECT 0x43
#define SER0_INTR_VECT 0x44
#define SER1_INTR_VECT 0x45
#define SER2_INTR_VECT 0x46
#define SER3_INTR_VECT 0x47
#define P21_INTR_VECT 0x48
#define ETH0_INTR_VECT 0x49
#define ETH1_INTR_VECT 0x4a
#define TIMER_INTR_VECT 0x4b
#define BIF_ARB_INTR_VECT 0x4c
#define BIF_DMA_INTR_VECT 0x4d
#define EXT_INTR_VECT 0x4e
#define IPI_INTR_VECT 0x4f
#endif
include/asm-cris/arch-v32/hwregs/pinmux_defs.h deleted 100644 → 0
View file @ 0a6d2fac
#ifndef __pinmux_defs_h
#define __pinmux_defs_h
/*
* This file is autogenerated from
* file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r
* id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp
* last modfied: Mon Apr 11 16:09:11 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile pinmux_defs.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r
* id: $Id: pinmux_defs.h,v 1.3 2005/04/24 18:30:58 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope pinmux */
/* Register rw_pa, scope pinmux, type rw */
typedef struct {
unsigned int pa0 : 1;
unsigned int pa1 : 1;
unsigned int pa2 : 1;
unsigned int pa3 : 1;
unsigned int pa4 : 1;
unsigned int pa5 : 1;
unsigned int pa6 : 1;
unsigned int pa7 : 1;
unsigned int csp2_n : 1;
unsigned int csp3_n : 1;
unsigned int csp5_n : 1;
unsigned int csp6_n : 1;
unsigned int hsh4 : 1;
unsigned int hsh5 : 1;
unsigned int hsh6 : 1;
unsigned int hsh7 : 1;
unsigned int dummy1 : 16;
} reg_pinmux_rw_pa;
#define REG_RD_ADDR_pinmux_rw_pa 0
#define REG_WR_ADDR_pinmux_rw_pa 0
/* Register rw_hwprot, scope pinmux, type rw */
typedef struct {
unsigned int ser1 : 1;
unsigned int ser2 : 1;
unsigned int ser3 : 1;
unsigned int sser0 : 1;
unsigned int sser1 : 1;
unsigned int ata0 : 1;
unsigned int ata1 : 1;
unsigned int ata2 : 1;
unsigned int ata3 : 1;
unsigned int ata : 1;
unsigned int eth1 : 1;
unsigned int eth1_mgm : 1;
unsigned int timer : 1;
unsigned int p21 : 1;
unsigned int dummy1 : 18;
} reg_pinmux_rw_hwprot;
#define REG_RD_ADDR_pinmux_rw_hwprot 4
#define REG_WR_ADDR_pinmux_rw_hwprot 4
/* Register rw_pb_gio, scope pinmux, type rw */
typedef struct {
unsigned int pb0 : 1;
unsigned int pb1 : 1;
unsigned int pb2 : 1;
unsigned int pb3 : 1;
unsigned int pb4 : 1;
unsigned int pb5 : 1;
unsigned int pb6 : 1;
unsigned int pb7 : 1;
unsigned int pb8 : 1;
unsigned int pb9 : 1;
unsigned int pb10 : 1;
unsigned int pb11 : 1;
unsigned int pb12 : 1;
unsigned int pb13 : 1;
unsigned int pb14 : 1;
unsigned int pb15 : 1;
unsigned int pb16 : 1;
unsigned int pb17 : 1;
unsigned int dummy1 : 14;
} reg_pinmux_rw_pb_gio;
#define REG_RD_ADDR_pinmux_rw_pb_gio 8
#define REG_WR_ADDR_pinmux_rw_pb_gio 8
/* Register rw_pb_iop, scope pinmux, type rw */
typedef struct {
unsigned int pb0 : 1;
unsigned int pb1 : 1;
unsigned int pb2 : 1;
unsigned int pb3 : 1;
unsigned int pb4 : 1;
unsigned int pb5 : 1;
unsigned int pb6 : 1;
unsigned int pb7 : 1;
unsigned int pb8 : 1;
unsigned int pb9 : 1;
unsigned int pb10 : 1;
unsigned int pb11 : 1;
unsigned int pb12 : 1;
unsigned int pb13 : 1;
unsigned int pb14 : 1;
unsigned int pb15 : 1;
unsigned int pb16 : 1;
unsigned int pb17 : 1;
unsigned int dummy1 : 14;
} reg_pinmux_rw_pb_iop;
#define REG_RD_ADDR_pinmux_rw_pb_iop 12
#define REG_WR_ADDR_pinmux_rw_pb_iop 12
/* Register rw_pc_gio, scope pinmux, type rw */
typedef struct {
unsigned int pc0 : 1;
unsigned int pc1 : 1;
unsigned int pc2 : 1;
unsigned int pc3 : 1;
unsigned int pc4 : 1;
unsigned int pc5 : 1;
unsigned int pc6 : 1;
unsigned int pc7 : 1;
unsigned int pc8 : 1;
unsigned int pc9 : 1;
unsigned int pc10 : 1;
unsigned int pc11 : 1;
unsigned int pc12 : 1;
unsigned int pc13 : 1;
unsigned int pc14 : 1;
unsigned int pc15 : 1;
unsigned int pc16 : 1;
unsigned int pc17 : 1;
unsigned int dummy1 : 14;
} reg_pinmux_rw_pc_gio;
#define REG_RD_ADDR_pinmux_rw_pc_gio 16
#define REG_WR_ADDR_pinmux_rw_pc_gio 16
/* Register rw_pc_iop, scope pinmux, type rw */
typedef struct {
unsigned int pc0 : 1;
unsigned int pc1 : 1;
unsigned int pc2 : 1;
unsigned int pc3 : 1;
unsigned int pc4 : 1;
unsigned int pc5 : 1;
unsigned int pc6 : 1;
unsigned int pc7 : 1;
unsigned int pc8 : 1;
unsigned int pc9 : 1;
unsigned int pc10 : 1;
unsigned int pc11 : 1;
unsigned int pc12 : 1;
unsigned int pc13 : 1;
unsigned int pc14 : 1;
unsigned int pc15 : 1;
unsigned int pc16 : 1;
unsigned int pc17 : 1;
unsigned int dummy1 : 14;
} reg_pinmux_rw_pc_iop;
#define REG_RD_ADDR_pinmux_rw_pc_iop 20
#define REG_WR_ADDR_pinmux_rw_pc_iop 20
/* Register rw_pd_gio, scope pinmux, type rw */
typedef struct {
unsigned int pd0 : 1;
unsigned int pd1 : 1;
unsigned int pd2 : 1;
unsigned int pd3 : 1;
unsigned int pd4 : 1;
unsigned int pd5 : 1;
unsigned int pd6 : 1;
unsigned int pd7 : 1;
unsigned int pd8 : 1;
unsigned int pd9 : 1;
unsigned int pd10 : 1;
unsigned int pd11 : 1;
unsigned int pd12 : 1;
unsigned int pd13 : 1;
unsigned int pd14 : 1;
unsigned int pd15 : 1;
unsigned int pd16 : 1;
unsigned int pd17 : 1;
unsigned int dummy1 : 14;
} reg_pinmux_rw_pd_gio;
#define REG_RD_ADDR_pinmux_rw_pd_gio 24
#define REG_WR_ADDR_pinmux_rw_pd_gio 24
/* Register rw_pd_iop, scope pinmux, type rw */
typedef struct {
unsigned int pd0 : 1;
unsigned int pd1 : 1;
unsigned int pd2 : 1;
unsigned int pd3 : 1;
unsigned int pd4 : 1;
unsigned int pd5 : 1;
unsigned int pd6 : 1;
unsigned int pd7 : 1;
unsigned int pd8 : 1;
unsigned int pd9 : 1;
unsigned int pd10 : 1;
unsigned int pd11 : 1;
unsigned int pd12 : 1;
unsigned int pd13 : 1;
unsigned int pd14 : 1;
unsigned int pd15 : 1;
unsigned int pd16 : 1;
unsigned int pd17 : 1;
unsigned int dummy1 : 14;
} reg_pinmux_rw_pd_iop;
#define REG_RD_ADDR_pinmux_rw_pd_iop 28
#define REG_WR_ADDR_pinmux_rw_pd_iop 28
/* Register rw_pe_gio, scope pinmux, type rw */
typedef struct {
unsigned int pe0 : 1;
unsigned int pe1 : 1;
unsigned int pe2 : 1;
unsigned int pe3 : 1;
unsigned int pe4 : 1;
unsigned int pe5 : 1;
unsigned int pe6 : 1;
unsigned int pe7 : 1;
unsigned int pe8 : 1;
unsigned int pe9 : 1;
unsigned int pe10 : 1;
unsigned int pe11 : 1;
unsigned int pe12 : 1;
unsigned int pe13 : 1;
unsigned int pe14 : 1;
unsigned int pe15 : 1;
unsigned int pe16 : 1;
unsigned int pe17 : 1;
unsigned int dummy1 : 14;
} reg_pinmux_rw_pe_gio;
#define REG_RD_ADDR_pinmux_rw_pe_gio 32
#define REG_WR_ADDR_pinmux_rw_pe_gio 32
/* Register rw_pe_iop, scope pinmux, type rw */
typedef struct {
unsigned int pe0 : 1;
unsigned int pe1 : 1;
unsigned int pe2 : 1;
unsigned int pe3 : 1;
unsigned int pe4 : 1;
unsigned int pe5 : 1;
unsigned int pe6 : 1;
unsigned int pe7 : 1;
unsigned int pe8 : 1;
unsigned int pe9 : 1;
unsigned int pe10 : 1;
unsigned int pe11 : 1;
unsigned int pe12 : 1;
unsigned int pe13 : 1;
unsigned int pe14 : 1;
unsigned int pe15 : 1;
unsigned int pe16 : 1;
unsigned int pe17 : 1;
unsigned int dummy1 : 14;
} reg_pinmux_rw_pe_iop;
#define REG_RD_ADDR_pinmux_rw_pe_iop 36
#define REG_WR_ADDR_pinmux_rw_pe_iop 36
/* Register rw_usb_phy, scope pinmux, type rw */
typedef struct {
unsigned int en_usb0 : 1;
unsigned int en_usb1 : 1;
unsigned int dummy1 : 30;
} reg_pinmux_rw_usb_phy;
#define REG_RD_ADDR_pinmux_rw_usb_phy 40
#define REG_WR_ADDR_pinmux_rw_usb_phy 40
/* Constants */
enum {
regk_pinmux_no = 0x00000000,
regk_pinmux_rw_hwprot_default = 0x00000000,
regk_pinmux_rw_pa_default = 0x00000000,
regk_pinmux_rw_pb_gio_default = 0x00000000,
regk_pinmux_rw_pb_iop_default = 0x00000000,
regk_pinmux_rw_pc_gio_default = 0x00000000,
regk_pinmux_rw_pc_iop_default = 0x00000000,
regk_pinmux_rw_pd_gio_default = 0x00000000,
regk_pinmux_rw_pd_iop_default = 0x00000000,
regk_pinmux_rw_pe_gio_default = 0x00000000,
regk_pinmux_rw_pe_iop_default = 0x00000000,
regk_pinmux_rw_usb_phy_default = 0x00000000,
regk_pinmux_yes = 0x00000001
};
#endif /* __pinmux_defs_h */
include/asm-cris/arch-v32/hwregs/strmux_defs.h deleted 100644 → 0
View file @ 0a6d2fac
#ifndef __strmux_defs_h
#define __strmux_defs_h
/*
* This file is autogenerated from
* file: ../../inst/strmux/rtl/guinness/strmux_regs.r
* id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp
* last modfied: Mon Apr 11 16:09:43 2005
*
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile strmux_defs.h ../../inst/strmux/rtl/guinness/strmux_regs.r
* id: $Id: strmux_defs.h,v 1.5 2005/04/24 18:30:58 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
*/
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
REG_READ( reg_##scope##_##reg, \
(inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
REG_WRITE( reg_##scope##_##reg, \
(inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif
#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg, (val) )
#endif
#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif
#ifndef reg_page_size
#define reg_page_size 8192
#endif
#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif
#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
( (inst) + REG_RD_ADDR_##scope##_##reg + \
(index) * STRIDE_##scope##_##reg )
#endif
/* C-code for register scope strmux */
/* Register rw_cfg, scope strmux, type rw */
typedef struct {
unsigned int dma0 : 3;
unsigned int dma1 : 3;
unsigned int dma2 : 3;
unsigned int dma3 : 3;
unsigned int dma4 : 3;
unsigned int dma5 : 3;
unsigned int dma6 : 3;
unsigned int dma7 : 3;
unsigned int dma8 : 3;
unsigned int dma9 : 3;
unsigned int dummy1 : 2;
} reg_strmux_rw_cfg;
#define REG_RD_ADDR_strmux_rw_cfg 0
#define REG_WR_ADDR_strmux_rw_cfg 0
/* Constants */
enum {
regk_strmux_ata = 0x00000003,
regk_strmux_eth0 = 0x00000001,
regk_strmux_eth1 = 0x00000004,
regk_strmux_ext0 = 0x00000001,
regk_strmux_ext1 = 0x00000001,
regk_strmux_ext2 = 0x00000001,
regk_strmux_ext3 = 0x00000001,
regk_strmux_iop0 = 0x00000002,
regk_strmux_iop1 = 0x00000001,
regk_strmux_off = 0x00000000,
regk_strmux_p21 = 0x00000004,
regk_strmux_rw_cfg_default = 0x00000000,
regk_strmux_ser0 = 0x00000002,
regk_strmux_ser1 = 0x00000002,
regk_strmux_ser2 = 0x00000004,
regk_strmux_ser3 = 0x00000003,
regk_strmux_sser0 = 0x00000003,
regk_strmux_sser1 = 0x00000003,
regk_strmux_strcop = 0x00000002
};
#endif /* __strmux_defs_h */
include/asm-cris/arch-v32/pinmux.h deleted 100644 → 0
View file @ 0a6d2fac
#ifndef _ASM_CRIS_ARCH_PINMUX_H
#define _ASM_CRIS_ARCH_PINMUX_H
#define PORT_B 0
#define PORT_C 1
#define PORT_D 2
#define PORT_E 3
enum pin_mode
{
pinmux_none = 0,
pinmux_fixed,
pinmux_gpio,
pinmux_iop
};
enum fixed_function
{
pinmux_ser1,
pinmux_ser2,
pinmux_ser3,
pinmux_sser0,
pinmux_sser1,
pinmux_ata0,
pinmux_ata1,
pinmux_ata2,
pinmux_ata3,
pinmux_ata,
pinmux_eth1,
pinmux_timer
};
int crisv32_pinmux_init(void);
int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode);
int crisv32_pinmux_alloc_fixed(enum fixed_function function);
int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin);
int crisv32_pinmux_dealloc_fixed(enum fixed_function function);
void crisv32_pinmux_dump(void);
#endif
include/asm-cris/spinlock.h deleted 100644 → 0
View file @ 0a6d2fac
#include <asm/arch/spinlock.h>
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