Commit 038b0f53 authored by Markos Chandras's avatar Markos Chandras Committed by Ralf Baechle

MIPS: CM: The CMGCRBase register is 64-bit on 64 bit kernels.

The CMGCRBase register (CP0, 15, 3) register is 64-bit on MIPS64
so we change its type to unsigned long.
Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10644/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent c0b584a2
...@@ -20,7 +20,7 @@ int mips_cm_is64; ...@@ -20,7 +20,7 @@ int mips_cm_is64;
phys_addr_t __mips_cm_phys_base(void) phys_addr_t __mips_cm_phys_base(void)
{ {
u32 config3 = read_c0_config3(); u32 config3 = read_c0_config3();
u32 cmgcr; unsigned long cmgcr;
/* Check the CMGCRBase register is implemented */ /* Check the CMGCRBase register is implemented */
if (!(config3 & MIPS_CONF3_CMGCR)) if (!(config3 & MIPS_CONF3_CMGCR))
......
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