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Commit 041b893b authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Stephen Boyd
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clk: qcom: gcc-sc7180: use parent_hws where possible 

Switch to using parent_hws instead of parent_data when parents are
defined in this driver and so accessible using clk_hw.
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-20-dmitry.baryshkov@linaro.orgSigned-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 634e438f
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Showing with 82 additions and 82 deletions
drivers/clk/qcom/gcc-sc7180.c
View file @ 041b893b
...@@ -65,8 +65,8 @@ static struct clk_alpha_pll_postdiv gpll0_out_even = { ...@@ -65,8 +65,8 @@ static struct clk_alpha_pll_postdiv gpll0_out_even = {
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gpll0_out_even", .name = "gpll0_out_even",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gpll0.clkr.hw, &gpll0.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops, .ops = &clk_alpha_pll_postdiv_fabia_ops,
...@@ -78,8 +78,8 @@ static struct clk_fixed_factor gcc_pll0_main_div_cdiv = { ...@@ -78,8 +78,8 @@ static struct clk_fixed_factor gcc_pll0_main_div_cdiv = {
.div = 2, .div = 2,
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_pll0_main_div_cdiv", .name = "gcc_pll0_main_div_cdiv",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gpll0.clkr.hw, &gpll0.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.ops = &clk_fixed_factor_ops, .ops = &clk_fixed_factor_ops,
...@@ -848,8 +848,8 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { ...@@ -848,8 +848,8 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_phy_axi_clk", .name = "gcc_aggre_ufs_phy_axi_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, &gcc_ufs_phy_axi_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -866,8 +866,8 @@ static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { ...@@ -866,8 +866,8 @@ static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_aggre_usb3_prim_axi_clk", .name = "gcc_aggre_usb3_prim_axi_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb30_prim_master_clk_src.clkr.hw, &gcc_usb30_prim_master_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -968,8 +968,8 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { ...@@ -968,8 +968,8 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_prim_axi_clk", .name = "gcc_cfg_noc_usb3_prim_axi_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb30_prim_master_clk_src.clkr.hw, &gcc_usb30_prim_master_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -987,8 +987,8 @@ static struct clk_branch gcc_cpuss_ahb_clk = { ...@@ -987,8 +987,8 @@ static struct clk_branch gcc_cpuss_ahb_clk = {
.enable_mask = BIT(21), .enable_mask = BIT(21),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_ahb_clk", .name = "gcc_cpuss_ahb_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_cpuss_ahb_clk_src.clkr.hw, &gcc_cpuss_ahb_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
...@@ -1030,8 +1030,8 @@ static struct clk_branch gcc_disp_gpll0_clk_src = { ...@@ -1030,8 +1030,8 @@ static struct clk_branch gcc_disp_gpll0_clk_src = {
.enable_mask = BIT(18), .enable_mask = BIT(18),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_disp_gpll0_clk_src", .name = "gcc_disp_gpll0_clk_src",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gpll0.clkr.hw, &gpll0.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.ops = &clk_branch2_aon_ops, .ops = &clk_branch2_aon_ops,
...@@ -1046,8 +1046,8 @@ static struct clk_branch gcc_disp_gpll0_div_clk_src = { ...@@ -1046,8 +1046,8 @@ static struct clk_branch gcc_disp_gpll0_div_clk_src = {
.enable_mask = BIT(19), .enable_mask = BIT(19),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_disp_gpll0_div_clk_src", .name = "gcc_disp_gpll0_div_clk_src",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_pll0_main_div_cdiv.hw, &gcc_pll0_main_div_cdiv.hw,
}, },
.num_parents = 1, .num_parents = 1,
.ops = &clk_branch2_ops, .ops = &clk_branch2_ops,
...@@ -1091,8 +1091,8 @@ static struct clk_branch gcc_gp1_clk = { ...@@ -1091,8 +1091,8 @@ static struct clk_branch gcc_gp1_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk", .name = "gcc_gp1_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_gp1_clk_src.clkr.hw, &gcc_gp1_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1109,8 +1109,8 @@ static struct clk_branch gcc_gp2_clk = { ...@@ -1109,8 +1109,8 @@ static struct clk_branch gcc_gp2_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk", .name = "gcc_gp2_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_gp2_clk_src.clkr.hw, &gcc_gp2_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1127,8 +1127,8 @@ static struct clk_branch gcc_gp3_clk = { ...@@ -1127,8 +1127,8 @@ static struct clk_branch gcc_gp3_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk", .name = "gcc_gp3_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_gp3_clk_src.clkr.hw, &gcc_gp3_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1144,8 +1144,8 @@ static struct clk_branch gcc_gpu_gpll0_clk_src = { ...@@ -1144,8 +1144,8 @@ static struct clk_branch gcc_gpu_gpll0_clk_src = {
.enable_mask = BIT(15), .enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_clk_src", .name = "gcc_gpu_gpll0_clk_src",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gpll0.clkr.hw, &gpll0.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.ops = &clk_branch2_ops, .ops = &clk_branch2_ops,
...@@ -1160,8 +1160,8 @@ static struct clk_branch gcc_gpu_gpll0_div_clk_src = { ...@@ -1160,8 +1160,8 @@ static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
.enable_mask = BIT(16), .enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_div_clk_src", .name = "gcc_gpu_gpll0_div_clk_src",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_pll0_main_div_cdiv.hw, &gcc_pll0_main_div_cdiv.hw,
}, },
.num_parents = 1, .num_parents = 1,
.ops = &clk_branch2_ops, .ops = &clk_branch2_ops,
...@@ -1284,8 +1284,8 @@ static struct clk_branch gcc_npu_gpll0_clk_src = { ...@@ -1284,8 +1284,8 @@ static struct clk_branch gcc_npu_gpll0_clk_src = {
.enable_mask = BIT(25), .enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_npu_gpll0_clk_src", .name = "gcc_npu_gpll0_clk_src",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gpll0.clkr.hw, &gpll0.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.ops = &clk_branch2_ops, .ops = &clk_branch2_ops,
...@@ -1300,8 +1300,8 @@ static struct clk_branch gcc_npu_gpll0_div_clk_src = { ...@@ -1300,8 +1300,8 @@ static struct clk_branch gcc_npu_gpll0_div_clk_src = {
.enable_mask = BIT(26), .enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_npu_gpll0_div_clk_src", .name = "gcc_npu_gpll0_div_clk_src",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_pll0_main_div_cdiv.hw, &gcc_pll0_main_div_cdiv.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1318,8 +1318,8 @@ static struct clk_branch gcc_pdm2_clk = { ...@@ -1318,8 +1318,8 @@ static struct clk_branch gcc_pdm2_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk", .name = "gcc_pdm2_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_pdm2_clk_src.clkr.hw, &gcc_pdm2_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1394,8 +1394,8 @@ static struct clk_branch gcc_qspi_core_clk = { ...@@ -1394,8 +1394,8 @@ static struct clk_branch gcc_qspi_core_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qspi_core_clk", .name = "gcc_qspi_core_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qspi_core_clk_src.clkr.hw, &gcc_qspi_core_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1438,8 +1438,8 @@ static struct clk_branch gcc_qupv3_wrap0_s0_clk = { ...@@ -1438,8 +1438,8 @@ static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
.enable_mask = BIT(10), .enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s0_clk", .name = "gcc_qupv3_wrap0_s0_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1456,8 +1456,8 @@ static struct clk_branch gcc_qupv3_wrap0_s1_clk = { ...@@ -1456,8 +1456,8 @@ static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
.enable_mask = BIT(11), .enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s1_clk", .name = "gcc_qupv3_wrap0_s1_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1474,8 +1474,8 @@ static struct clk_branch gcc_qupv3_wrap0_s2_clk = { ...@@ -1474,8 +1474,8 @@ static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
.enable_mask = BIT(12), .enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s2_clk", .name = "gcc_qupv3_wrap0_s2_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1492,8 +1492,8 @@ static struct clk_branch gcc_qupv3_wrap0_s3_clk = { ...@@ -1492,8 +1492,8 @@ static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
.enable_mask = BIT(13), .enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s3_clk", .name = "gcc_qupv3_wrap0_s3_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1510,8 +1510,8 @@ static struct clk_branch gcc_qupv3_wrap0_s4_clk = { ...@@ -1510,8 +1510,8 @@ static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
.enable_mask = BIT(14), .enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s4_clk", .name = "gcc_qupv3_wrap0_s4_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1528,8 +1528,8 @@ static struct clk_branch gcc_qupv3_wrap0_s5_clk = { ...@@ -1528,8 +1528,8 @@ static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
.enable_mask = BIT(15), .enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s5_clk", .name = "gcc_qupv3_wrap0_s5_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1572,8 +1572,8 @@ static struct clk_branch gcc_qupv3_wrap1_s0_clk = { ...@@ -1572,8 +1572,8 @@ static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
.enable_mask = BIT(22), .enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s0_clk", .name = "gcc_qupv3_wrap1_s0_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1590,8 +1590,8 @@ static struct clk_branch gcc_qupv3_wrap1_s1_clk = { ...@@ -1590,8 +1590,8 @@ static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
.enable_mask = BIT(23), .enable_mask = BIT(23),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s1_clk", .name = "gcc_qupv3_wrap1_s1_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1608,8 +1608,8 @@ static struct clk_branch gcc_qupv3_wrap1_s2_clk = { ...@@ -1608,8 +1608,8 @@ static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
.enable_mask = BIT(24), .enable_mask = BIT(24),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s2_clk", .name = "gcc_qupv3_wrap1_s2_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1626,8 +1626,8 @@ static struct clk_branch gcc_qupv3_wrap1_s3_clk = { ...@@ -1626,8 +1626,8 @@ static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
.enable_mask = BIT(25), .enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s3_clk", .name = "gcc_qupv3_wrap1_s3_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1644,8 +1644,8 @@ static struct clk_branch gcc_qupv3_wrap1_s4_clk = { ...@@ -1644,8 +1644,8 @@ static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
.enable_mask = BIT(26), .enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s4_clk", .name = "gcc_qupv3_wrap1_s4_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1662,8 +1662,8 @@ static struct clk_branch gcc_qupv3_wrap1_s5_clk = { ...@@ -1662,8 +1662,8 @@ static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
.enable_mask = BIT(27), .enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s5_clk", .name = "gcc_qupv3_wrap1_s5_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1749,8 +1749,8 @@ static struct clk_branch gcc_sdcc1_apps_clk = { ...@@ -1749,8 +1749,8 @@ static struct clk_branch gcc_sdcc1_apps_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk", .name = "gcc_sdcc1_apps_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_sdcc1_apps_clk_src.clkr.hw, &gcc_sdcc1_apps_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1767,8 +1767,8 @@ static struct clk_branch gcc_sdcc1_ice_core_clk = { ...@@ -1767,8 +1767,8 @@ static struct clk_branch gcc_sdcc1_ice_core_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk", .name = "gcc_sdcc1_ice_core_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_sdcc1_ice_core_clk_src.clkr.hw, &gcc_sdcc1_ice_core_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1798,8 +1798,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = { ...@@ -1798,8 +1798,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk", .name = "gcc_sdcc2_apps_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_sdcc2_apps_clk_src.clkr.hw, &gcc_sdcc2_apps_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1817,8 +1817,8 @@ static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { ...@@ -1817,8 +1817,8 @@ static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_cpuss_ahb_clk", .name = "gcc_sys_noc_cpuss_ahb_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_cpuss_ahb_clk_src.clkr.hw, &gcc_cpuss_ahb_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
...@@ -1865,8 +1865,8 @@ static struct clk_branch gcc_ufs_phy_axi_clk = { ...@@ -1865,8 +1865,8 @@ static struct clk_branch gcc_ufs_phy_axi_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk", .name = "gcc_ufs_phy_axi_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, &gcc_ufs_phy_axi_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1885,8 +1885,8 @@ static struct clk_branch gcc_ufs_phy_ice_core_clk = { ...@@ -1885,8 +1885,8 @@ static struct clk_branch gcc_ufs_phy_ice_core_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk", .name = "gcc_ufs_phy_ice_core_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw, &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1905,8 +1905,8 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk = { ...@@ -1905,8 +1905,8 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk", .name = "gcc_ufs_phy_phy_aux_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1951,8 +1951,8 @@ static struct clk_branch gcc_ufs_phy_unipro_core_clk = { ...@@ -1951,8 +1951,8 @@ static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk", .name = "gcc_ufs_phy_unipro_core_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1969,8 +1969,8 @@ static struct clk_branch gcc_usb30_prim_master_clk = { ...@@ -1969,8 +1969,8 @@ static struct clk_branch gcc_usb30_prim_master_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk", .name = "gcc_usb30_prim_master_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb30_prim_master_clk_src.clkr.hw, &gcc_usb30_prim_master_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2032,8 +2032,8 @@ static struct clk_branch gcc_usb3_prim_phy_aux_clk = { ...@@ -2032,8 +2032,8 @@ static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk", .name = "gcc_usb3_prim_phy_aux_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2050,8 +2050,8 @@ static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { ...@@ -2050,8 +2050,8 @@ static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_com_aux_clk", .name = "gcc_usb3_prim_phy_com_aux_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2108,8 +2108,8 @@ static struct clk_branch gcc_video_gpll0_div_clk_src = { ...@@ -2108,8 +2108,8 @@ static struct clk_branch gcc_video_gpll0_div_clk_src = {
.enable_mask = BIT(20), .enable_mask = BIT(20),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_video_gpll0_div_clk_src", .name = "gcc_video_gpll0_div_clk_src",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_pll0_main_div_cdiv.hw, &gcc_pll0_main_div_cdiv.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
......
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