Commit 04abc0a3 authored by Avinash Patil's avatar Avinash Patil Committed by John W. Linville

mwifiex: change default tx/rx win_size for BA setup

This patch fixes an issue where RX throughput values observed
were substantially lower than TX counterparts for PCIe8897 STA.
PCIe8897 supports larger rx_win_size. After changing these values
we see big improvement for TX and RX throughput values.

Different tx_win_size and rx_win_size are used for AP mode.

All BA setup related initialization has been moved to separate
function.
Signed-off-by: default avatarAvinash Patil <patila@marvell.com>
Signed-off-by: default avatarSagar Bijwe <bsagar@marvell.com>
Signed-off-by: default avatarYogesh Ashok Powar <yogeshp@marvell.com>
Signed-off-by: default avatarBing Zhao <bzhao@marvell.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 9a574cd6
...@@ -679,3 +679,25 @@ void mwifiex_del_tx_ba_stream_tbl_by_ra(struct mwifiex_private *priv, u8 *ra) ...@@ -679,3 +679,25 @@ void mwifiex_del_tx_ba_stream_tbl_by_ra(struct mwifiex_private *priv, u8 *ra)
return; return;
} }
/* This function initializes the BlockACK setup information for given
* mwifiex_private structure.
*/
void mwifiex_set_ba_params(struct mwifiex_private *priv)
{
priv->add_ba_param.timeout = MWIFIEX_DEFAULT_BLOCK_ACK_TIMEOUT;
if (GET_BSS_ROLE(priv) == MWIFIEX_BSS_ROLE_UAP) {
priv->add_ba_param.tx_win_size =
MWIFIEX_UAP_AMPDU_DEF_TXWINSIZE;
priv->add_ba_param.rx_win_size =
MWIFIEX_UAP_AMPDU_DEF_RXWINSIZE;
} else {
priv->add_ba_param.tx_win_size =
MWIFIEX_STA_AMPDU_DEF_TXWINSIZE;
priv->add_ba_param.rx_win_size =
MWIFIEX_STA_AMPDU_DEF_RXWINSIZE;
}
return;
}
...@@ -41,8 +41,11 @@ ...@@ -41,8 +41,11 @@
#define MWIFIEX_MAX_TX_BASTREAM_SUPPORTED 2 #define MWIFIEX_MAX_TX_BASTREAM_SUPPORTED 2
#define MWIFIEX_MAX_RX_BASTREAM_SUPPORTED 16 #define MWIFIEX_MAX_RX_BASTREAM_SUPPORTED 16
#define MWIFIEX_AMPDU_DEF_TXWINSIZE 32 #define MWIFIEX_STA_AMPDU_DEF_TXWINSIZE 16
#define MWIFIEX_AMPDU_DEF_RXWINSIZE 16 #define MWIFIEX_STA_AMPDU_DEF_RXWINSIZE 32
#define MWIFIEX_UAP_AMPDU_DEF_TXWINSIZE 32
#define MWIFIEX_UAP_AMPDU_DEF_RXWINSIZE 16
#define MWIFIEX_DEFAULT_BLOCK_ACK_TIMEOUT 0xffff #define MWIFIEX_DEFAULT_BLOCK_ACK_TIMEOUT 0xffff
#define MWIFIEX_RATE_BITMAP_MCS0 32 #define MWIFIEX_RATE_BITMAP_MCS0 32
......
...@@ -924,6 +924,7 @@ void ...@@ -924,6 +924,7 @@ void
mwifiex_set_wmm_params(struct mwifiex_private *priv, mwifiex_set_wmm_params(struct mwifiex_private *priv,
struct mwifiex_uap_bss_param *bss_cfg, struct mwifiex_uap_bss_param *bss_cfg,
struct cfg80211_ap_settings *params); struct cfg80211_ap_settings *params);
void mwifiex_set_ba_params(struct mwifiex_private *priv);
/* /*
* This function checks if the queuing is RA based or not. * This function checks if the queuing is RA based or not.
......
...@@ -436,10 +436,7 @@ mwifiex_wmm_init(struct mwifiex_adapter *adapter) ...@@ -436,10 +436,7 @@ mwifiex_wmm_init(struct mwifiex_adapter *adapter)
= priv->aggr_prio_tbl[7].ampdu_user = priv->aggr_prio_tbl[7].ampdu_user
= BA_STREAM_NOT_ALLOWED; = BA_STREAM_NOT_ALLOWED;
priv->add_ba_param.timeout = MWIFIEX_DEFAULT_BLOCK_ACK_TIMEOUT; mwifiex_set_ba_params(priv);
priv->add_ba_param.tx_win_size = MWIFIEX_AMPDU_DEF_TXWINSIZE;
priv->add_ba_param.rx_win_size = MWIFIEX_AMPDU_DEF_RXWINSIZE;
mwifiex_reset_11n_rx_seq_num(priv); mwifiex_reset_11n_rx_seq_num(priv);
atomic_set(&priv->wmm.tx_pkts_queued, 0); atomic_set(&priv->wmm.tx_pkts_queued, 0);
......
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