Commit 04e4783f authored by Christoph Hellwig's avatar Christoph Hellwig Committed by Thomas Bogendoerfer

MIPS/malta: simplify plat_setup_iocoherency

Given that plat_mem_setup runs before earlyparams are handled and malta
selects CONFIG_DMA_MAYBE_COHERENT, coherentio can only be set to
IO_COHERENCE_DEFAULT at this point.  So remove the checking for other
options and merge plat_enable_iocoherency into plat_setup_iocoherency
to simplify the code a bit.
Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 7c86ff99
...@@ -90,16 +90,15 @@ static void __init fd_activate(void) ...@@ -90,16 +90,15 @@ static void __init fd_activate(void)
} }
#endif #endif
static int __init plat_enable_iocoherency(void) static void __init plat_setup_iocoherency(void)
{ {
int supported = 0;
u32 cfg; u32 cfg;
if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) { if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
pr_info("Enabled Bonito CPU coherency\n"); pr_info("Enabled Bonito CPU coherency\n");
supported = 1; hw_coherentio = 1;
} }
if (strstr(fw_getcmdline(), "iobcuncached")) { if (strstr(fw_getcmdline(), "iobcuncached")) {
BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
...@@ -118,29 +117,16 @@ static int __init plat_enable_iocoherency(void) ...@@ -118,29 +117,16 @@ static int __init plat_enable_iocoherency(void)
/* Nothing special needs to be done to enable coherency */ /* Nothing special needs to be done to enable coherency */
pr_info("CMP IOCU detected\n"); pr_info("CMP IOCU detected\n");
cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0)); cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0));
if (!(cfg & ROCIT_CONFIG_GEN0_PCI_IOCU)) { if (cfg & ROCIT_CONFIG_GEN0_PCI_IOCU)
hw_coherentio = 1;
else
pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n"); pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");
return 0;
}
supported = 1;
} }
hw_coherentio = supported;
return supported;
}
static void __init plat_setup_iocoherency(void) if (hw_coherentio)
{ pr_info("Hardware DMA cache coherency enabled\n");
if (plat_enable_iocoherency()) { else
if (coherentio == IO_COHERENCE_DISABLED) pr_info("Software DMA cache coherency enabled\n");
pr_info("Hardware DMA cache coherency disabled\n");
else
pr_info("Hardware DMA cache coherency enabled\n");
} else {
if (coherentio == IO_COHERENCE_ENABLED)
pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
else
pr_info("Software DMA cache coherency enabled\n");
}
} }
static void __init pci_clock_check(void) static void __init pci_clock_check(void)
......
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