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Commit 05fccb0e authored by Ingo Molnar's avatar Ingo Molnar
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x86: code cleanups in arch/x86/kernel/pci-gart_64.c 

code cleanups:

                                       errors   lines of code   errors/KLOC
 arch/x86/kernel/pci-gart_64.c            183             748         244.6
 arch/x86/kernel/pci-gart_64.c              0             790             0
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent e8d591dc
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Showing with 276 additions and 232 deletions
arch/x86/kernel/pci-gart_64.c
View file @ 05fccb0e
/* /*
* Dynamic DMA mapping support for AMD Hammer. * Dynamic DMA mapping support for AMD Hammer.
* *
* Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI. * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI.
* This allows to use PCI devices that only support 32bit addresses on systems * This allows to use PCI devices that only support 32bit addresses on systems
* with more than 4GB. * with more than 4GB.
* *
* See Documentation/DMA-mapping.txt for the interface specification. * See Documentation/DMA-mapping.txt for the interface specification.
* *
* Copyright 2002 Andi Kleen, SuSE Labs. * Copyright 2002 Andi Kleen, SuSE Labs.
* Subject to the GNU General Public License v2 only. * Subject to the GNU General Public License v2 only.
*/ */
...@@ -37,23 +37,26 @@ ...@@ -37,23 +37,26 @@
#include <asm/k8.h> #include <asm/k8.h>
static unsigned long iommu_bus_base; /* GART remapping area (physical) */ static unsigned long iommu_bus_base; /* GART remapping area (physical) */
static unsigned long iommu_size; /* size of remapping area bytes */ static unsigned long iommu_size; /* size of remapping area bytes */
static unsigned long iommu_pages; /* .. and in pages */ static unsigned long iommu_pages; /* .. and in pages */
static u32 *iommu_gatt_base; /* Remapping table */ static u32 *iommu_gatt_base; /* Remapping table */
/* If this is disabled the IOMMU will use an optimized flushing strategy /*
of only flushing when an mapping is reused. With it true the GART is flushed * If this is disabled the IOMMU will use an optimized flushing strategy
for every mapping. Problem is that doing the lazy flush seems to trigger * of only flushing when an mapping is reused. With it true the GART is
bugs with some popular PCI cards, in particular 3ware (but has been also * flushed for every mapping. Problem is that doing the lazy flush seems
also seen with Qlogic at least). */ * to trigger bugs with some popular PCI cards, in particular 3ware (but
* has been also also seen with Qlogic at least).
*/
int iommu_fullflush = 1; int iommu_fullflush = 1;
/* Allocation bitmap for the remapping area */ /* Allocation bitmap for the remapping area: */
static DEFINE_SPINLOCK(iommu_bitmap_lock); static DEFINE_SPINLOCK(iommu_bitmap_lock);
static unsigned long *iommu_gart_bitmap; /* guarded by iommu_bitmap_lock */ /* Guarded by iommu_bitmap_lock: */
static unsigned long *iommu_gart_bitmap;
static u32 gart_unmapped_entry; static u32 gart_unmapped_entry;
#define GPTE_VALID 1 #define GPTE_VALID 1
#define GPTE_COHERENT 2 #define GPTE_COHERENT 2
...@@ -61,10 +64,10 @@ static u32 gart_unmapped_entry; ...@@ -61,10 +64,10 @@ static u32 gart_unmapped_entry;
(((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT) (((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT)
#define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28)) #define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28))
#define to_pages(addr,size) \ #define to_pages(addr, size) \
(round_up(((addr) & ~PAGE_MASK) + (size), PAGE_SIZE) >> PAGE_SHIFT) (round_up(((addr) & ~PAGE_MASK) + (size), PAGE_SIZE) >> PAGE_SHIFT)
#define EMERGENCY_PAGES 32 /* = 128KB */ #define EMERGENCY_PAGES 32 /* = 128KB */
#ifdef CONFIG_AGP #ifdef CONFIG_AGP
#define AGPEXTERN extern #define AGPEXTERN extern
...@@ -77,130 +80,152 @@ AGPEXTERN int agp_memory_reserved; ...@@ -77,130 +80,152 @@ AGPEXTERN int agp_memory_reserved;
AGPEXTERN __u32 *agp_gatt_table; AGPEXTERN __u32 *agp_gatt_table;
static unsigned long next_bit; /* protected by iommu_bitmap_lock */ static unsigned long next_bit; /* protected by iommu_bitmap_lock */
static int need_flush; /* global flush state. set for each gart wrap */ static int need_flush; /* global flush state. set for each gart wrap */
static unsigned long alloc_iommu(int size) static unsigned long alloc_iommu(int size)
{ {
unsigned long offset, flags; unsigned long offset, flags;
spin_lock_irqsave(&iommu_bitmap_lock, flags); spin_lock_irqsave(&iommu_bitmap_lock, flags);
offset = find_next_zero_string(iommu_gart_bitmap,next_bit,iommu_pages,size); offset = find_next_zero_string(iommu_gart_bitmap, next_bit,
iommu_pages, size);
if (offset == -1) { if (offset == -1) {
need_flush = 1; need_flush = 1;
offset = find_next_zero_string(iommu_gart_bitmap,0,iommu_pages,size); offset = find_next_zero_string(iommu_gart_bitmap, 0,
iommu_pages, size);
} }
if (offset != -1) { if (offset != -1) {
set_bit_string(iommu_gart_bitmap, offset, size); set_bit_string(iommu_gart_bitmap, offset, size);
next_bit = offset+size; next_bit = offset+size;
if (next_bit >= iommu_pages) { if (next_bit >= iommu_pages) {
next_bit = 0; next_bit = 0;
need_flush = 1; need_flush = 1;
} }
} }
if (iommu_fullflush) if (iommu_fullflush)
need_flush = 1; need_flush = 1;
spin_unlock_irqrestore(&iommu_bitmap_lock, flags); spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
return offset; return offset;
} }
static void free_iommu(unsigned long offset, int size) static void free_iommu(unsigned long offset, int size)
{ {
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&iommu_bitmap_lock, flags); spin_lock_irqsave(&iommu_bitmap_lock, flags);
__clear_bit_string(iommu_gart_bitmap, offset, size); __clear_bit_string(iommu_gart_bitmap, offset, size);
spin_unlock_irqrestore(&iommu_bitmap_lock, flags); spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
} }
/* /*
* Use global flush state to avoid races with multiple flushers. * Use global flush state to avoid races with multiple flushers.
*/ */
static void flush_gart(void) static void flush_gart(void)
{ {
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&iommu_bitmap_lock, flags); spin_lock_irqsave(&iommu_bitmap_lock, flags);
if (need_flush) { if (need_flush) {
k8_flush_garts(); k8_flush_garts();
need_flush = 0; need_flush = 0;
} }
spin_unlock_irqrestore(&iommu_bitmap_lock, flags); spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
} }
#ifdef CONFIG_IOMMU_LEAK #ifdef CONFIG_IOMMU_LEAK
#define SET_LEAK(x) if (iommu_leak_tab) \ #define SET_LEAK(x) \
iommu_leak_tab[x] = __builtin_return_address(0); do { \
#define CLEAR_LEAK(x) if (iommu_leak_tab) \ if (iommu_leak_tab) \
iommu_leak_tab[x] = NULL; iommu_leak_tab[x] = __builtin_return_address(0);\
} while (0)
#define CLEAR_LEAK(x) \
do { \
if (iommu_leak_tab) \
iommu_leak_tab[x] = NULL; \
} while (0)
/* Debugging aid for drivers that don't free their IOMMU tables */ /* Debugging aid for drivers that don't free their IOMMU tables */
static void **iommu_leak_tab; static void **iommu_leak_tab;
static int leak_trace; static int leak_trace;
static int iommu_leak_pages = 20; static int iommu_leak_pages = 20;
static void dump_leak(void) static void dump_leak(void)
{ {
int i; int i;
static int dump; static int dump;
if (dump || !iommu_leak_tab) return;
if (dump || !iommu_leak_tab)
return;
dump = 1; dump = 1;
show_stack(NULL,NULL); show_stack(NULL, NULL);
/* Very crude. dump some from the end of the table too */
printk("Dumping %d pages from end of IOMMU:\n", iommu_leak_pages); /* Very crude. dump some from the end of the table too */
for (i = 0; i < iommu_leak_pages; i+=2) { printk(KERN_DEBUG "Dumping %d pages from end of IOMMU:\n",
printk("%lu: ", iommu_pages-i); iommu_leak_pages);
for (i = 0; i < iommu_leak_pages; i += 2) {
printk(KERN_DEBUG "%lu: ", iommu_pages-i);
printk_address((unsigned long) iommu_leak_tab[iommu_pages-i]); printk_address((unsigned long) iommu_leak_tab[iommu_pages-i]);
printk("%c", (i+1)%2 == 0 ? '\n' : ' '); printk(KERN_CONT "%c", (i+1)%2 == 0 ? '\n' : ' ');
} }
printk("\n"); printk(KERN_DEBUG "\n");
} }
#else #else
#define SET_LEAK(x) # define SET_LEAK(x)
#define CLEAR_LEAK(x) # define CLEAR_LEAK(x)
#endif #endif
static void iommu_full(struct device *dev, size_t size, int dir) static void iommu_full(struct device *dev, size_t size, int dir)
{ {
/* /*
* Ran out of IOMMU space for this operation. This is very bad. * Ran out of IOMMU space for this operation. This is very bad.
* Unfortunately the drivers cannot handle this operation properly. * Unfortunately the drivers cannot handle this operation properly.
* Return some non mapped prereserved space in the aperture and * Return some non mapped prereserved space in the aperture and
* let the Northbridge deal with it. This will result in garbage * let the Northbridge deal with it. This will result in garbage
* in the IO operation. When the size exceeds the prereserved space * in the IO operation. When the size exceeds the prereserved space
* memory corruption will occur or random memory will be DMAed * memory corruption will occur or random memory will be DMAed
* out. Hopefully no network devices use single mappings that big. * out. Hopefully no network devices use single mappings that big.
*/ */
printk(KERN_ERR printk(KERN_ERR
"PCI-DMA: Out of IOMMU space for %lu bytes at device %s\n", "PCI-DMA: Out of IOMMU space for %lu bytes at device %s\n",
size, dev->bus_id); size, dev->bus_id);
if (size > PAGE_SIZE*EMERGENCY_PAGES) { if (size > PAGE_SIZE*EMERGENCY_PAGES) {
if (dir == PCI_DMA_FROMDEVICE || dir == PCI_DMA_BIDIRECTIONAL) if (dir == PCI_DMA_FROMDEVICE || dir == PCI_DMA_BIDIRECTIONAL)
panic("PCI-DMA: Memory would be corrupted\n"); panic("PCI-DMA: Memory would be corrupted\n");
if (dir == PCI_DMA_TODEVICE || dir == PCI_DMA_BIDIRECTIONAL) if (dir == PCI_DMA_TODEVICE || dir == PCI_DMA_BIDIRECTIONAL)
panic(KERN_ERR "PCI-DMA: Random memory would be DMAed\n"); panic(KERN_ERR
} "PCI-DMA: Random memory would be DMAed\n");
}
#ifdef CONFIG_IOMMU_LEAK #ifdef CONFIG_IOMMU_LEAK
dump_leak(); dump_leak();
#endif #endif
} }
static inline int need_iommu(struct device *dev, unsigned long addr, size_t size) static inline int
{ need_iommu(struct device *dev, unsigned long addr, size_t size)
{
u64 mask = *dev->dma_mask; u64 mask = *dev->dma_mask;
int high = addr + size > mask; int high = addr + size > mask;
int mmu = high; int mmu = high;
if (force_iommu)
mmu = 1; if (force_iommu)
return mmu; mmu = 1;
return mmu;
} }
static inline int nonforced_iommu(struct device *dev, unsigned long addr, size_t size) static inline int
{ nonforced_iommu(struct device *dev, unsigned long addr, size_t size)
{
u64 mask = *dev->dma_mask; u64 mask = *dev->dma_mask;
int high = addr + size > mask; int high = addr + size > mask;
int mmu = high; int mmu = high;
return mmu;
return mmu;
} }
/* Map a single continuous physical area into the IOMMU. /* Map a single continuous physical area into the IOMMU.
...@@ -208,13 +233,14 @@ static inline int nonforced_iommu(struct device *dev, unsigned long addr, size_t ...@@ -208,13 +233,14 @@ static inline int nonforced_iommu(struct device *dev, unsigned long addr, size_t
*/ */
static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem, static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem,
size_t size, int dir) size_t size, int dir)
{ {
unsigned long npages = to_pages(phys_mem, size); unsigned long npages = to_pages(phys_mem, size);
unsigned long iommu_page = alloc_iommu(npages); unsigned long iommu_page = alloc_iommu(npages);
int i; int i;
if (iommu_page == -1) { if (iommu_page == -1) {
if (!nonforced_iommu(dev, phys_mem, size)) if (!nonforced_iommu(dev, phys_mem, size))
return phys_mem; return phys_mem;
if (panic_on_overflow) if (panic_on_overflow)
panic("dma_map_area overflow %lu bytes\n", size); panic("dma_map_area overflow %lu bytes\n", size);
iommu_full(dev, size, dir); iommu_full(dev, size, dir);
...@@ -229,35 +255,39 @@ static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem, ...@@ -229,35 +255,39 @@ static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem,
return iommu_bus_base + iommu_page*PAGE_SIZE + (phys_mem & ~PAGE_MASK); return iommu_bus_base + iommu_page*PAGE_SIZE + (phys_mem & ~PAGE_MASK);
} }
static dma_addr_t gart_map_simple(struct device *dev, char *buf, static dma_addr_t
size_t size, int dir) gart_map_simple(struct device *dev, char *buf, size_t size, int dir)
{ {
dma_addr_t map = dma_map_area(dev, virt_to_bus(buf), size, dir); dma_addr_t map = dma_map_area(dev, virt_to_bus(buf), size, dir);
flush_gart(); flush_gart();
return map; return map;
} }
/* Map a single area into the IOMMU */ /* Map a single area into the IOMMU */
static dma_addr_t gart_map_single(struct device *dev, void *addr, size_t size, int dir) static dma_addr_t
gart_map_single(struct device *dev, void *addr, size_t size, int dir)
{ {
unsigned long phys_mem, bus; unsigned long phys_mem, bus;
if (!dev) if (!dev)
dev = &fallback_dev; dev = &fallback_dev;
phys_mem = virt_to_phys(addr); phys_mem = virt_to_phys(addr);
if (!need_iommu(dev, phys_mem, size)) if (!need_iommu(dev, phys_mem, size))
return phys_mem; return phys_mem;
bus = gart_map_simple(dev, addr, size, dir); bus = gart_map_simple(dev, addr, size, dir);
return bus;
return bus;
} }
/* /*
* Free a DMA mapping. * Free a DMA mapping.
*/ */
static void gart_unmap_single(struct device *dev, dma_addr_t dma_addr, static void gart_unmap_single(struct device *dev, dma_addr_t dma_addr,
size_t size, int direction) size_t size, int direction)
{ {
unsigned long iommu_page; unsigned long iommu_page;
int npages; int npages;
...@@ -266,6 +296,7 @@ static void gart_unmap_single(struct device *dev, dma_addr_t dma_addr, ...@@ -266,6 +296,7 @@ static void gart_unmap_single(struct device *dev, dma_addr_t dma_addr,
if (dma_addr < iommu_bus_base + EMERGENCY_PAGES*PAGE_SIZE || if (dma_addr < iommu_bus_base + EMERGENCY_PAGES*PAGE_SIZE ||
dma_addr >= iommu_bus_base + iommu_size) dma_addr >= iommu_bus_base + iommu_size)
return; return;
iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT; iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT;
npages = to_pages(dma_addr, size); npages = to_pages(dma_addr, size);
for (i = 0; i < npages; i++) { for (i = 0; i < npages; i++) {
...@@ -278,7 +309,8 @@ static void gart_unmap_single(struct device *dev, dma_addr_t dma_addr, ...@@ -278,7 +309,8 @@ static void gart_unmap_single(struct device *dev, dma_addr_t dma_addr,
/* /*
* Wrapper for pci_unmap_single working with scatterlists. * Wrapper for pci_unmap_single working with scatterlists.
*/ */
static void gart_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, int dir) static void
gart_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, int dir)
{ {
struct scatterlist *s; struct scatterlist *s;
int i; int i;
...@@ -303,12 +335,13 @@ static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg, ...@@ -303,12 +335,13 @@ static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg,
for_each_sg(sg, s, nents, i) { for_each_sg(sg, s, nents, i) {
unsigned long addr = sg_phys(s); unsigned long addr = sg_phys(s);
if (nonforced_iommu(dev, addr, s->length)) {
if (nonforced_iommu(dev, addr, s->length)) {
addr = dma_map_area(dev, addr, s->length, dir); addr = dma_map_area(dev, addr, s->length, dir);
if (addr == bad_dma_address) { if (addr == bad_dma_address) {
if (i > 0) if (i > 0)
gart_unmap_sg(dev, sg, i, dir); gart_unmap_sg(dev, sg, i, dir);
nents = 0; nents = 0;
sg[0].dma_length = 0; sg[0].dma_length = 0;
break; break;
} }
...@@ -317,15 +350,16 @@ static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg, ...@@ -317,15 +350,16 @@ static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg,
s->dma_length = s->length; s->dma_length = s->length;
} }
flush_gart(); flush_gart();
return nents; return nents;
} }
/* Map multiple scatterlist entries continuous into the first. */ /* Map multiple scatterlist entries continuous into the first. */
static int __dma_map_cont(struct scatterlist *start, int nelems, static int __dma_map_cont(struct scatterlist *start, int nelems,
struct scatterlist *sout, unsigned long pages) struct scatterlist *sout, unsigned long pages)
{ {
unsigned long iommu_start = alloc_iommu(pages); unsigned long iommu_start = alloc_iommu(pages);
unsigned long iommu_page = iommu_start; unsigned long iommu_page = iommu_start;
struct scatterlist *s; struct scatterlist *s;
int i; int i;
...@@ -335,32 +369,33 @@ static int __dma_map_cont(struct scatterlist *start, int nelems, ...@@ -335,32 +369,33 @@ static int __dma_map_cont(struct scatterlist *start, int nelems,
for_each_sg(start, s, nelems, i) { for_each_sg(start, s, nelems, i) {
unsigned long pages, addr; unsigned long pages, addr;
unsigned long phys_addr = s->dma_address; unsigned long phys_addr = s->dma_address;
BUG_ON(s != start && s->offset); BUG_ON(s != start && s->offset);
if (s == start) { if (s == start) {
sout->dma_address = iommu_bus_base; sout->dma_address = iommu_bus_base;
sout->dma_address += iommu_page*PAGE_SIZE + s->offset; sout->dma_address += iommu_page*PAGE_SIZE + s->offset;
sout->dma_length = s->length; sout->dma_length = s->length;
} else { } else {
sout->dma_length += s->length; sout->dma_length += s->length;
} }
addr = phys_addr; addr = phys_addr;
pages = to_pages(s->offset, s->length); pages = to_pages(s->offset, s->length);
while (pages--) { while (pages--) {
iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr); iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr);
SET_LEAK(iommu_page); SET_LEAK(iommu_page);
addr += PAGE_SIZE; addr += PAGE_SIZE;
iommu_page++; iommu_page++;
} }
} }
BUG_ON(iommu_page - iommu_start != pages); BUG_ON(iommu_page - iommu_start != pages);
return 0; return 0;
} }
static inline int dma_map_cont(struct scatterlist *start, int nelems, static inline int
struct scatterlist *sout, dma_map_cont(struct scatterlist *start, int nelems, struct scatterlist *sout,
unsigned long pages, int need) unsigned long pages, int need)
{ {
if (!need) { if (!need) {
BUG_ON(nelems != 1); BUG_ON(nelems != 1);
...@@ -370,22 +405,19 @@ static inline int dma_map_cont(struct scatterlist *start, int nelems, ...@@ -370,22 +405,19 @@ static inline int dma_map_cont(struct scatterlist *start, int nelems,
} }
return __dma_map_cont(start, nelems, sout, pages); return __dma_map_cont(start, nelems, sout, pages);
} }
/* /*
* DMA map all entries in a scatterlist. * DMA map all entries in a scatterlist.
* Merge chunks that have page aligned sizes into a continuous mapping. * Merge chunks that have page aligned sizes into a continuous mapping.
*/ */
static int gart_map_sg(struct device *dev, struct scatterlist *sg, int nents, static int
int dir) gart_map_sg(struct device *dev, struct scatterlist *sg, int nents, int dir)
{ {
int i;
int out;
int start;
unsigned long pages = 0;
int need = 0, nextneed;
struct scatterlist *s, *ps, *start_sg, *sgmap; struct scatterlist *s, *ps, *start_sg, *sgmap;
int need = 0, nextneed, i, out, start;
unsigned long pages = 0;
if (nents == 0) if (nents == 0)
return 0; return 0;
if (!dev) if (!dev)
...@@ -397,15 +429,19 @@ static int gart_map_sg(struct device *dev, struct scatterlist *sg, int nents, ...@@ -397,15 +429,19 @@ static int gart_map_sg(struct device *dev, struct scatterlist *sg, int nents,
ps = NULL; /* shut up gcc */ ps = NULL; /* shut up gcc */
for_each_sg(sg, s, nents, i) { for_each_sg(sg, s, nents, i) {
dma_addr_t addr = sg_phys(s); dma_addr_t addr = sg_phys(s);
s->dma_address = addr; s->dma_address = addr;
BUG_ON(s->length == 0); BUG_ON(s->length == 0);
nextneed = need_iommu(dev, addr, s->length); nextneed = need_iommu(dev, addr, s->length);
/* Handle the previous not yet processed entries */ /* Handle the previous not yet processed entries */
if (i > start) { if (i > start) {
/* Can only merge when the last chunk ends on a page /*
boundary and the new one doesn't have an offset. */ * Can only merge when the last chunk ends on a
* page boundary and the new one doesn't have an
* offset.
*/
if (!iommu_merge || !nextneed || !need || s->offset || if (!iommu_merge || !nextneed || !need || s->offset ||
(ps->offset + ps->length) % PAGE_SIZE) { (ps->offset + ps->length) % PAGE_SIZE) {
if (dma_map_cont(start_sg, i - start, sgmap, if (dma_map_cont(start_sg, i - start, sgmap,
...@@ -436,6 +472,7 @@ static int gart_map_sg(struct device *dev, struct scatterlist *sg, int nents, ...@@ -436,6 +472,7 @@ static int gart_map_sg(struct device *dev, struct scatterlist *sg, int nents,
error: error:
flush_gart(); flush_gart();
gart_unmap_sg(dev, sg, out, dir); gart_unmap_sg(dev, sg, out, dir);
/* When it was forced or merged try again in a dumb way */ /* When it was forced or merged try again in a dumb way */
if (force_iommu || iommu_merge) { if (force_iommu || iommu_merge) {
out = dma_map_sg_nonforce(dev, sg, nents, dir); out = dma_map_sg_nonforce(dev, sg, nents, dir);
...@@ -444,64 +481,68 @@ static int gart_map_sg(struct device *dev, struct scatterlist *sg, int nents, ...@@ -444,64 +481,68 @@ static int gart_map_sg(struct device *dev, struct scatterlist *sg, int nents,
} }
if (panic_on_overflow) if (panic_on_overflow)
panic("dma_map_sg: overflow on %lu pages\n", pages); panic("dma_map_sg: overflow on %lu pages\n", pages);
iommu_full(dev, pages << PAGE_SHIFT, dir); iommu_full(dev, pages << PAGE_SHIFT, dir);
for_each_sg(sg, s, nents, i) for_each_sg(sg, s, nents, i)
s->dma_address = bad_dma_address; s->dma_address = bad_dma_address;
return 0; return 0;
} }
static int no_agp; static int no_agp;
static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size) static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size)
{ {
unsigned long a; unsigned long a;
if (!iommu_size) {
iommu_size = aper_size; if (!iommu_size) {
if (!no_agp) iommu_size = aper_size;
iommu_size /= 2; if (!no_agp)
} iommu_size /= 2;
}
a = aper + iommu_size;
a = aper + iommu_size;
iommu_size -= round_up(a, LARGE_PAGE_SIZE) - a; iommu_size -= round_up(a, LARGE_PAGE_SIZE) - a;
if (iommu_size < 64*1024*1024) if (iommu_size < 64*1024*1024) {
printk(KERN_WARNING printk(KERN_WARNING
"PCI-DMA: Warning: Small IOMMU %luMB. Consider increasing the AGP aperture in BIOS\n",iommu_size>>20); "PCI-DMA: Warning: Small IOMMU %luMB."
" Consider increasing the AGP aperture in BIOS\n",
iommu_size >> 20);
}
return iommu_size; return iommu_size;
} }
static __init unsigned read_aperture(struct pci_dev *dev, u32 *size) static __init unsigned read_aperture(struct pci_dev *dev, u32 *size)
{ {
unsigned aper_size = 0, aper_base_32; unsigned aper_size = 0, aper_base_32, aper_order;
u64 aper_base; u64 aper_base;
unsigned aper_order;
pci_read_config_dword(dev, 0x94, &aper_base_32); pci_read_config_dword(dev, 0x94, &aper_base_32);
pci_read_config_dword(dev, 0x90, &aper_order); pci_read_config_dword(dev, 0x90, &aper_order);
aper_order = (aper_order >> 1) & 7; aper_order = (aper_order >> 1) & 7;
aper_base = aper_base_32 & 0x7fff; aper_base = aper_base_32 & 0x7fff;
aper_base <<= 25; aper_base <<= 25;
aper_size = (32 * 1024 * 1024) << aper_order; aper_size = (32 * 1024 * 1024) << aper_order;
if (aper_base + aper_size > 0x100000000UL || !aper_size) if (aper_base + aper_size > 0x100000000UL || !aper_size)
aper_base = 0; aper_base = 0;
*size = aper_size; *size = aper_size;
return aper_base; return aper_base;
} }
/* /*
* Private Northbridge GATT initialization in case we cannot use the * Private Northbridge GATT initialization in case we cannot use the
* AGP driver for some reason. * AGP driver for some reason.
*/ */
static __init int init_k8_gatt(struct agp_kern_info *info) static __init int init_k8_gatt(struct agp_kern_info *info)
{ {
unsigned aper_size, gatt_size, new_aper_size;
unsigned aper_base, new_aper_base;
struct pci_dev *dev; struct pci_dev *dev;
void *gatt; void *gatt;
unsigned aper_base, new_aper_base;
unsigned aper_size, gatt_size, new_aper_size;
int i; int i;
printk(KERN_INFO "PCI-DMA: Disabling AGP.\n"); printk(KERN_INFO "PCI-DMA: Disabling AGP.\n");
...@@ -509,75 +550,77 @@ static __init int init_k8_gatt(struct agp_kern_info *info) ...@@ -509,75 +550,77 @@ static __init int init_k8_gatt(struct agp_kern_info *info)
dev = NULL; dev = NULL;
for (i = 0; i < num_k8_northbridges; i++) { for (i = 0; i < num_k8_northbridges; i++) {
dev = k8_northbridges[i]; dev = k8_northbridges[i];
new_aper_base = read_aperture(dev, &new_aper_size); new_aper_base = read_aperture(dev, &new_aper_size);
if (!new_aper_base) if (!new_aper_base)
goto nommu; goto nommu;
if (!aper_base) { if (!aper_base) {
aper_size = new_aper_size; aper_size = new_aper_size;
aper_base = new_aper_base; aper_base = new_aper_base;
} }
if (aper_size != new_aper_size || aper_base != new_aper_base) if (aper_size != new_aper_size || aper_base != new_aper_base)
goto nommu; goto nommu;
} }
if (!aper_base) if (!aper_base)
goto nommu; goto nommu;
info->aper_base = aper_base; info->aper_base = aper_base;
info->aper_size = aper_size>>20; info->aper_size = aper_size >> 20;
gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32); gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32);
gatt = (void *)__get_free_pages(GFP_KERNEL, get_order(gatt_size)); gatt = (void *)__get_free_pages(GFP_KERNEL, get_order(gatt_size));
if (!gatt) if (!gatt)
panic("Cannot allocate GATT table"); panic("Cannot allocate GATT table");
if (change_page_attr_addr((unsigned long)gatt, gatt_size >> PAGE_SHIFT, PAGE_KERNEL_NOCACHE)) if (change_page_attr_addr((unsigned long)gatt, gatt_size >> PAGE_SHIFT,
PAGE_KERNEL_NOCACHE))
panic("Could not set GART PTEs to uncacheable pages"); panic("Could not set GART PTEs to uncacheable pages");
global_flush_tlb(); global_flush_tlb();
memset(gatt, 0, gatt_size); memset(gatt, 0, gatt_size);
agp_gatt_table = gatt; agp_gatt_table = gatt;
for (i = 0; i < num_k8_northbridges; i++) { for (i = 0; i < num_k8_northbridges; i++) {
u32 ctl; u32 gatt_reg;
u32 gatt_reg; u32 ctl;
dev = k8_northbridges[i]; dev = k8_northbridges[i];
gatt_reg = __pa(gatt) >> 12; gatt_reg = __pa(gatt) >> 12;
gatt_reg <<= 4; gatt_reg <<= 4;
pci_write_config_dword(dev, 0x98, gatt_reg); pci_write_config_dword(dev, 0x98, gatt_reg);
pci_read_config_dword(dev, 0x90, &ctl); pci_read_config_dword(dev, 0x90, &ctl);
ctl |= 1; ctl |= 1;
ctl &= ~((1<<4) | (1<<5)); ctl &= ~((1<<4) | (1<<5));
pci_write_config_dword(dev, 0x90, ctl); pci_write_config_dword(dev, 0x90, ctl);
} }
flush_gart(); flush_gart();
printk("PCI-DMA: aperture base @ %x size %u KB\n",aper_base, aper_size>>10); printk(KERN_INFO "PCI-DMA: aperture base @ %x size %u KB\n",
aper_base, aper_size>>10);
return 0; return 0;
nommu: nommu:
/* Should not happen anymore */ /* Should not happen anymore */
printk(KERN_ERR "PCI-DMA: More than 4GB of RAM and no IOMMU\n" printk(KERN_ERR "PCI-DMA: More than 4GB of RAM and no IOMMU\n"
KERN_ERR "PCI-DMA: 32bit PCI IO may malfunction.\n"); KERN_ERR "PCI-DMA: 32bit PCI IO may malfunction.\n");
return -1; return -1;
} }
extern int agp_amd64_init(void); extern int agp_amd64_init(void);
static const struct dma_mapping_ops gart_dma_ops = { static const struct dma_mapping_ops gart_dma_ops = {
.mapping_error = NULL, .mapping_error = NULL,
.map_single = gart_map_single, .map_single = gart_map_single,
.map_simple = gart_map_simple, .map_simple = gart_map_simple,
.unmap_single = gart_unmap_single, .unmap_single = gart_unmap_single,
.sync_single_for_cpu = NULL, .sync_single_for_cpu = NULL,
.sync_single_for_device = NULL, .sync_single_for_device = NULL,
.sync_single_range_for_cpu = NULL, .sync_single_range_for_cpu = NULL,
.sync_single_range_for_device = NULL, .sync_single_range_for_device = NULL,
.sync_sg_for_cpu = NULL, .sync_sg_for_cpu = NULL,
.sync_sg_for_device = NULL, .sync_sg_for_device = NULL,
.map_sg = gart_map_sg, .map_sg = gart_map_sg,
.unmap_sg = gart_unmap_sg, .unmap_sg = gart_unmap_sg,
}; };
void gart_iommu_shutdown(void) void gart_iommu_shutdown(void)
...@@ -588,23 +631,23 @@ void gart_iommu_shutdown(void) ...@@ -588,23 +631,23 @@ void gart_iommu_shutdown(void)
if (no_agp && (dma_ops != &gart_dma_ops)) if (no_agp && (dma_ops != &gart_dma_ops))
return; return;
for (i = 0; i < num_k8_northbridges; i++) { for (i = 0; i < num_k8_northbridges; i++) {
u32 ctl; u32 ctl;
dev = k8_northbridges[i]; dev = k8_northbridges[i];
pci_read_config_dword(dev, 0x90, &ctl); pci_read_config_dword(dev, 0x90, &ctl);
ctl &= ~1; ctl &= ~1;
pci_write_config_dword(dev, 0x90, ctl); pci_write_config_dword(dev, 0x90, ctl);
} }
} }
void __init gart_iommu_init(void) void __init gart_iommu_init(void)
{ {
struct agp_kern_info info; struct agp_kern_info info;
unsigned long aper_size;
unsigned long iommu_start; unsigned long iommu_start;
unsigned long aper_size;
unsigned long scratch; unsigned long scratch;
long i; long i;
...@@ -614,14 +657,14 @@ void __init gart_iommu_init(void) ...@@ -614,14 +657,14 @@ void __init gart_iommu_init(void)
} }
#ifndef CONFIG_AGP_AMD64 #ifndef CONFIG_AGP_AMD64
no_agp = 1; no_agp = 1;
#else #else
/* Makefile puts PCI initialization via subsys_initcall first. */ /* Makefile puts PCI initialization via subsys_initcall first. */
/* Add other K8 AGP bridge drivers here */ /* Add other K8 AGP bridge drivers here */
no_agp = no_agp || no_agp = no_agp ||
(agp_amd64_init() < 0) || (agp_amd64_init() < 0) ||
(agp_copy_info(agp_bridge, &info) < 0); (agp_copy_info(agp_bridge, &info) < 0);
#endif #endif
if (swiotlb) if (swiotlb)
return; return;
...@@ -643,77 +686,78 @@ void __init gart_iommu_init(void) ...@@ -643,77 +686,78 @@ void __init gart_iommu_init(void)
} }
printk(KERN_INFO "PCI-DMA: using GART IOMMU.\n"); printk(KERN_INFO "PCI-DMA: using GART IOMMU.\n");
aper_size = info.aper_size * 1024 * 1024; aper_size = info.aper_size * 1024 * 1024;
iommu_size = check_iommu_size(info.aper_base, aper_size); iommu_size = check_iommu_size(info.aper_base, aper_size);
iommu_pages = iommu_size >> PAGE_SHIFT; iommu_pages = iommu_size >> PAGE_SHIFT;
iommu_gart_bitmap = (void*)__get_free_pages(GFP_KERNEL, iommu_gart_bitmap = (void *) __get_free_pages(GFP_KERNEL,
get_order(iommu_pages/8)); get_order(iommu_pages/8));
if (!iommu_gart_bitmap) if (!iommu_gart_bitmap)
panic("Cannot allocate iommu bitmap\n"); panic("Cannot allocate iommu bitmap\n");
memset(iommu_gart_bitmap, 0, iommu_pages/8); memset(iommu_gart_bitmap, 0, iommu_pages/8);
#ifdef CONFIG_IOMMU_LEAK #ifdef CONFIG_IOMMU_LEAK
if (leak_trace) { if (leak_trace) {
iommu_leak_tab = (void *)__get_free_pages(GFP_KERNEL, iommu_leak_tab = (void *)__get_free_pages(GFP_KERNEL,
get_order(iommu_pages*sizeof(void *))); get_order(iommu_pages*sizeof(void *)));
if (iommu_leak_tab) if (iommu_leak_tab)
memset(iommu_leak_tab, 0, iommu_pages * 8); memset(iommu_leak_tab, 0, iommu_pages * 8);
else else
printk("PCI-DMA: Cannot allocate leak trace area\n"); printk(KERN_DEBUG
} "PCI-DMA: Cannot allocate leak trace area\n");
}
#endif #endif
/* /*
* Out of IOMMU space handling. * Out of IOMMU space handling.
* Reserve some invalid pages at the beginning of the GART. * Reserve some invalid pages at the beginning of the GART.
*/ */
set_bit_string(iommu_gart_bitmap, 0, EMERGENCY_PAGES); set_bit_string(iommu_gart_bitmap, 0, EMERGENCY_PAGES);
agp_memory_reserved = iommu_size; agp_memory_reserved = iommu_size;
printk(KERN_INFO printk(KERN_INFO
"PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n", "PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n",
iommu_size>>20); iommu_size >> 20);
iommu_start = aper_size - iommu_size; iommu_start = aper_size - iommu_size;
iommu_bus_base = info.aper_base + iommu_start; iommu_bus_base = info.aper_base + iommu_start;
bad_dma_address = iommu_bus_base; bad_dma_address = iommu_bus_base;
iommu_gatt_base = agp_gatt_table + (iommu_start>>PAGE_SHIFT); iommu_gatt_base = agp_gatt_table + (iommu_start>>PAGE_SHIFT);
/* /*
* Unmap the IOMMU part of the GART. The alias of the page is * Unmap the IOMMU part of the GART. The alias of the page is
* always mapped with cache enabled and there is no full cache * always mapped with cache enabled and there is no full cache
* coherency across the GART remapping. The unmapping avoids * coherency across the GART remapping. The unmapping avoids
* automatic prefetches from the CPU allocating cache lines in * automatic prefetches from the CPU allocating cache lines in
* there. All CPU accesses are done via the direct mapping to * there. All CPU accesses are done via the direct mapping to
* the backing memory. The GART address is only used by PCI * the backing memory. The GART address is only used by PCI
* devices. * devices.
*/ */
clear_kernel_mapping((unsigned long)__va(iommu_bus_base), iommu_size); clear_kernel_mapping((unsigned long)__va(iommu_bus_base), iommu_size);
/* /*
* Try to workaround a bug (thanks to BenH) * Try to workaround a bug (thanks to BenH)
* Set unmapped entries to a scratch page instead of 0. * Set unmapped entries to a scratch page instead of 0.
* Any prefetches that hit unmapped entries won't get an bus abort * Any prefetches that hit unmapped entries won't get an bus abort
* then. * then.
*/ */
scratch = get_zeroed_page(GFP_KERNEL); scratch = get_zeroed_page(GFP_KERNEL);
if (!scratch) if (!scratch)
panic("Cannot allocate iommu scratch page"); panic("Cannot allocate iommu scratch page");
gart_unmapped_entry = GPTE_ENCODE(__pa(scratch)); gart_unmapped_entry = GPTE_ENCODE(__pa(scratch));
for (i = EMERGENCY_PAGES; i < iommu_pages; i++) for (i = EMERGENCY_PAGES; i < iommu_pages; i++)
iommu_gatt_base[i] = gart_unmapped_entry; iommu_gatt_base[i] = gart_unmapped_entry;
flush_gart(); flush_gart();
dma_ops = &gart_dma_ops; dma_ops = &gart_dma_ops;
} }
void __init gart_parse_options(char *p) void __init gart_parse_options(char *p)
{ {
int arg; int arg;
#ifdef CONFIG_IOMMU_LEAK #ifdef CONFIG_IOMMU_LEAK
if (!strncmp(p,"leak",4)) { if (!strncmp(p, "leak", 4)) {
leak_trace = 1; leak_trace = 1;
p += 4; p += 4;
if (*p == '=') ++p; if (*p == '=') ++p;
...@@ -723,18 +767,18 @@ void __init gart_parse_options(char *p) ...@@ -723,18 +767,18 @@ void __init gart_parse_options(char *p)
#endif #endif
if (isdigit(*p) && get_option(&p, &arg)) if (isdigit(*p) && get_option(&p, &arg))
iommu_size = arg; iommu_size = arg;
if (!strncmp(p, "fullflush",8)) if (!strncmp(p, "fullflush", 8))
iommu_fullflush = 1; iommu_fullflush = 1;
if (!strncmp(p, "nofullflush",11)) if (!strncmp(p, "nofullflush", 11))
iommu_fullflush = 0; iommu_fullflush = 0;
if (!strncmp(p,"noagp",5)) if (!strncmp(p, "noagp", 5))
no_agp = 1; no_agp = 1;
if (!strncmp(p, "noaperture",10)) if (!strncmp(p, "noaperture", 10))
fix_aperture = 0; fix_aperture = 0;
/* duplicated from pci-dma.c */ /* duplicated from pci-dma.c */
if (!strncmp(p,"force",5)) if (!strncmp(p, "force", 5))
gart_iommu_aperture_allowed = 1; gart_iommu_aperture_allowed = 1;
if (!strncmp(p,"allowed",7)) if (!strncmp(p, "allowed", 7))
gart_iommu_aperture_allowed = 1; gart_iommu_aperture_allowed = 1;
if (!strncmp(p, "memaper", 7)) { if (!strncmp(p, "memaper", 7)) {
fallback_aper_force = 1; fallback_aper_force = 1;
......
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