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Commit 05ffdd7b authored by Jay Cliburn's avatar Jay Cliburn Committed by Jeff Garzik
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atl1: reorder atl1_main functions 

Reorder functions in atl1_main into more logical groupings to make the
code easier to follow. This patch is large, but it's harmless; it neither
adds nor removes any functionality whatsoever.
Signed-off-by: default avatarJay Cliburn <jacliburn@bellsouth.net>
Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
parent 2ca13da7
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Showing with 1248 additions and 1248 deletions
drivers/net/atl1/atl1_main.c
View file @ 05ffdd7b
...@@ -168,6 +168,64 @@ static int __devinit atl1_sw_init(struct atl1_adapter *adapter) ...@@ -168,6 +168,64 @@ static int __devinit atl1_sw_init(struct atl1_adapter *adapter)
return 0; return 0;
} }
static int mdio_read(struct net_device *netdev, int phy_id, int reg_num)
{
struct atl1_adapter *adapter = netdev_priv(netdev);
u16 result;
atl1_read_phy_reg(&adapter->hw, reg_num & 0x1f, &result);
return result;
}
static void mdio_write(struct net_device *netdev, int phy_id, int reg_num,
int val)
{
struct atl1_adapter *adapter = netdev_priv(netdev);
atl1_write_phy_reg(&adapter->hw, reg_num, val);
}
/*
* atl1_mii_ioctl -
* @netdev:
* @ifreq:
* @cmd:
*/
static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
{
struct atl1_adapter *adapter = netdev_priv(netdev);
unsigned long flags;
int retval;
if (!netif_running(netdev))
return -EINVAL;
spin_lock_irqsave(&adapter->lock, flags);
retval = generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
spin_unlock_irqrestore(&adapter->lock, flags);
return retval;
}
/*
* atl1_ioctl -
* @netdev:
* @ifreq:
* @cmd:
*/
static int atl1_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
{
switch (cmd) {
case SIOCGMIIPHY:
case SIOCGMIIREG:
case SIOCSMIIREG:
return atl1_mii_ioctl(netdev, ifr, cmd);
default:
return -EOPNOTSUPP;
}
}
/* /*
* atl1_setup_mem_resources - allocate Tx / RX descriptor resources * atl1_setup_mem_resources - allocate Tx / RX descriptor resources
* @adapter: board private structure * @adapter: board private structure
...@@ -276,972 +334,1095 @@ void atl1_init_ring_ptrs(struct atl1_adapter *adapter) ...@@ -276,972 +334,1095 @@ void atl1_init_ring_ptrs(struct atl1_adapter *adapter)
} }
/* /*
* atl1_irq_enable - Enable default interrupt generation settings * atl1_clean_rx_ring - Free RFD Buffers
* @adapter: board private structure * @adapter: board private structure
*/ */
static void atl1_irq_enable(struct atl1_adapter *adapter) static void atl1_clean_rx_ring(struct atl1_adapter *adapter)
{
iowrite32(IMR_NORMAL_MASK, adapter->hw.hw_addr + REG_IMR);
ioread32(adapter->hw.hw_addr + REG_IMR);
}
static void atl1_clear_phy_int(struct atl1_adapter *adapter)
{
u16 phy_data;
unsigned long flags;
spin_lock_irqsave(&adapter->lock, flags);
atl1_read_phy_reg(&adapter->hw, 19, &phy_data);
spin_unlock_irqrestore(&adapter->lock, flags);
}
static void atl1_inc_smb(struct atl1_adapter *adapter)
{ {
struct stats_msg_block *smb = adapter->smb.smb; struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
/* Fill out the OS statistics structure */ struct atl1_buffer *buffer_info;
adapter->soft_stats.rx_packets += smb->rx_ok; struct pci_dev *pdev = adapter->pdev;
adapter->soft_stats.tx_packets += smb->tx_ok; unsigned long size;
adapter->soft_stats.rx_bytes += smb->rx_byte_cnt; unsigned int i;
adapter->soft_stats.tx_bytes += smb->tx_byte_cnt;
adapter->soft_stats.multicast += smb->rx_mcast;
adapter->soft_stats.collisions += (smb->tx_1_col + smb->tx_2_col * 2 +
smb->tx_late_col + smb->tx_abort_col * adapter->hw.max_retry);
/* Rx Errors */ /* Free all the Rx ring sk_buffs */
adapter->soft_stats.rx_errors += (smb->rx_frag + smb->rx_fcs_err + for (i = 0; i < rfd_ring->count; i++) {
smb->rx_len_err + smb->rx_sz_ov + smb->rx_rxf_ov + buffer_info = &rfd_ring->buffer_info[i];
smb->rx_rrd_ov + smb->rx_align_err); if (buffer_info->dma) {
adapter->soft_stats.rx_fifo_errors += smb->rx_rxf_ov; pci_unmap_page(pdev, buffer_info->dma,
adapter->soft_stats.rx_length_errors += smb->rx_len_err; buffer_info->length, PCI_DMA_FROMDEVICE);
adapter->soft_stats.rx_crc_errors += smb->rx_fcs_err; buffer_info->dma = 0;
adapter->soft_stats.rx_frame_errors += smb->rx_align_err; }
adapter->soft_stats.rx_missed_errors += (smb->rx_rrd_ov + if (buffer_info->skb) {
smb->rx_rxf_ov); dev_kfree_skb(buffer_info->skb);
buffer_info->skb = NULL;
}
}
adapter->soft_stats.rx_pause += smb->rx_pause; size = sizeof(struct atl1_buffer) * rfd_ring->count;
adapter->soft_stats.rx_rrd_ov += smb->rx_rrd_ov; memset(rfd_ring->buffer_info, 0, size);
adapter->soft_stats.rx_trunc += smb->rx_sz_ov;
/* Tx Errors */ /* Zero out the descriptor ring */
adapter->soft_stats.tx_errors += (smb->tx_late_col + memset(rfd_ring->desc, 0, rfd_ring->size);
smb->tx_abort_col + smb->tx_underrun + smb->tx_trunc);
adapter->soft_stats.tx_fifo_errors += smb->tx_underrun;
adapter->soft_stats.tx_aborted_errors += smb->tx_abort_col;
adapter->soft_stats.tx_window_errors += smb->tx_late_col;
adapter->soft_stats.excecol += smb->tx_abort_col; rfd_ring->next_to_clean = 0;
adapter->soft_stats.deffer += smb->tx_defer; atomic_set(&rfd_ring->next_to_use, 0);
adapter->soft_stats.scc += smb->tx_1_col;
adapter->soft_stats.mcc += smb->tx_2_col;
adapter->soft_stats.latecol += smb->tx_late_col;
adapter->soft_stats.tx_underun += smb->tx_underrun;
adapter->soft_stats.tx_trunc += smb->tx_trunc;
adapter->soft_stats.tx_pause += smb->tx_pause;
adapter->net_stats.rx_packets = adapter->soft_stats.rx_packets; rrd_ring->next_to_use = 0;
adapter->net_stats.tx_packets = adapter->soft_stats.tx_packets; atomic_set(&rrd_ring->next_to_clean, 0);
adapter->net_stats.rx_bytes = adapter->soft_stats.rx_bytes;
adapter->net_stats.tx_bytes = adapter->soft_stats.tx_bytes;
adapter->net_stats.multicast = adapter->soft_stats.multicast;
adapter->net_stats.collisions = adapter->soft_stats.collisions;
adapter->net_stats.rx_errors = adapter->soft_stats.rx_errors;
adapter->net_stats.rx_over_errors =
adapter->soft_stats.rx_missed_errors;
adapter->net_stats.rx_length_errors =
adapter->soft_stats.rx_length_errors;
adapter->net_stats.rx_crc_errors = adapter->soft_stats.rx_crc_errors;
adapter->net_stats.rx_frame_errors =
adapter->soft_stats.rx_frame_errors;
adapter->net_stats.rx_fifo_errors = adapter->soft_stats.rx_fifo_errors;
adapter->net_stats.rx_missed_errors =
adapter->soft_stats.rx_missed_errors;
adapter->net_stats.tx_errors = adapter->soft_stats.tx_errors;
adapter->net_stats.tx_fifo_errors = adapter->soft_stats.tx_fifo_errors;
adapter->net_stats.tx_aborted_errors =
adapter->soft_stats.tx_aborted_errors;
adapter->net_stats.tx_window_errors =
adapter->soft_stats.tx_window_errors;
adapter->net_stats.tx_carrier_errors =
adapter->soft_stats.tx_carrier_errors;
} }
static void atl1_rx_checksum(struct atl1_adapter *adapter, /*
struct rx_return_desc *rrd, struct sk_buff *skb) * atl1_clean_tx_ring - Free Tx Buffers
* @adapter: board private structure
*/
static void atl1_clean_tx_ring(struct atl1_adapter *adapter)
{ {
struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
struct atl1_buffer *buffer_info;
struct pci_dev *pdev = adapter->pdev; struct pci_dev *pdev = adapter->pdev;
unsigned long size;
unsigned int i;
skb->ip_summed = CHECKSUM_NONE; /* Free all the Tx ring sk_buffs */
for (i = 0; i < tpd_ring->count; i++) {
buffer_info = &tpd_ring->buffer_info[i];
if (buffer_info->dma) {
pci_unmap_page(pdev, buffer_info->dma,
buffer_info->length, PCI_DMA_TODEVICE);
buffer_info->dma = 0;
}
}
if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) { for (i = 0; i < tpd_ring->count; i++) {
if (rrd->err_flg & (ERR_FLAG_CRC | ERR_FLAG_TRUNC | buffer_info = &tpd_ring->buffer_info[i];
ERR_FLAG_CODE | ERR_FLAG_OV)) { if (buffer_info->skb) {
adapter->hw_csum_err++; dev_kfree_skb_any(buffer_info->skb);
dev_printk(KERN_DEBUG, &pdev->dev, buffer_info->skb = NULL;
"rx checksum error\n");
return;
} }
} }
/* not IPv4 */ size = sizeof(struct atl1_buffer) * tpd_ring->count;
if (!(rrd->pkt_flg & PACKET_FLAG_IPV4)) memset(tpd_ring->buffer_info, 0, size);
/* checksum is invalid, but it's not an IPv4 pkt, so ok */
return;
/* IPv4 packet */ /* Zero out the descriptor ring */
if (likely(!(rrd->err_flg & memset(tpd_ring->desc, 0, tpd_ring->size);
(ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM)))) {
skb->ip_summed = CHECKSUM_UNNECESSARY;
adapter->hw_csum_good++;
return;
}
/* IPv4, but hardware thinks its checksum is wrong */ atomic_set(&tpd_ring->next_to_use, 0);
dev_printk(KERN_DEBUG, &pdev->dev, atomic_set(&tpd_ring->next_to_clean, 0);
"hw csum wrong, pkt_flag:%x, err_flag:%x\n",
rrd->pkt_flg, rrd->err_flg);
skb->ip_summed = CHECKSUM_COMPLETE;
skb->csum = htons(rrd->xsz.xsum_sz.rx_chksum);
adapter->hw_csum_err++;
return;
} }
/* /*
* atl1_alloc_rx_buffers - Replace used receive buffers * atl1_free_ring_resources - Free Tx / RX descriptor Resources
* @adapter: address of board private structure * @adapter: board private structure
*
* Free all transmit software resources
*/ */
static u16 atl1_alloc_rx_buffers(struct atl1_adapter *adapter) void atl1_free_ring_resources(struct atl1_adapter *adapter)
{ {
struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
struct pci_dev *pdev = adapter->pdev; struct pci_dev *pdev = adapter->pdev;
struct page *page; struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
unsigned long offset; struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
struct atl1_buffer *buffer_info, *next_info; struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
struct sk_buff *skb; struct atl1_ring_header *ring_header = &adapter->ring_header;
u16 num_alloc = 0;
u16 rfd_next_to_use, next_next;
struct rx_free_desc *rfd_desc;
next_next = rfd_next_to_use = atomic_read(&rfd_ring->next_to_use); atl1_clean_tx_ring(adapter);
if (++next_next == rfd_ring->count) atl1_clean_rx_ring(adapter);
next_next = 0;
buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
next_info = &rfd_ring->buffer_info[next_next];
while (!buffer_info->alloced && !next_info->alloced) { kfree(tpd_ring->buffer_info);
if (buffer_info->skb) { pci_free_consistent(pdev, ring_header->size, ring_header->desc,
buffer_info->alloced = 1; ring_header->dma);
goto next;
}
rfd_desc = ATL1_RFD_DESC(rfd_ring, rfd_next_to_use); tpd_ring->buffer_info = NULL;
tpd_ring->desc = NULL;
tpd_ring->dma = 0;
skb = dev_alloc_skb(adapter->rx_buffer_len + NET_IP_ALIGN); rfd_ring->buffer_info = NULL;
if (unlikely(!skb)) { /* Better luck next round */ rfd_ring->desc = NULL;
adapter->net_stats.rx_dropped++; rfd_ring->dma = 0;
break;
rrd_ring->desc = NULL;
rrd_ring->dma = 0;
}
static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter)
{
u32 value;
struct atl1_hw *hw = &adapter->hw;
struct net_device *netdev = adapter->netdev;
/* Config MAC CTRL Register */
value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN;
/* duplex */
if (FULL_DUPLEX == adapter->link_duplex)
value |= MAC_CTRL_DUPLX;
/* speed */
value |= ((u32) ((SPEED_1000 == adapter->link_speed) ?
MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) <<
MAC_CTRL_SPEED_SHIFT);
/* flow control */
value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
/* PAD & CRC */
value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
/* preamble length */
value |= (((u32) adapter->hw.preamble_len
& MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
/* vlan */
if (adapter->vlgrp)
value |= MAC_CTRL_RMV_VLAN;
/* rx checksum
if (adapter->rx_csum)
value |= MAC_CTRL_RX_CHKSUM_EN;
*/
/* filter mode */
value |= MAC_CTRL_BC_EN;
if (netdev->flags & IFF_PROMISC)
value |= MAC_CTRL_PROMIS_EN;
else if (netdev->flags & IFF_ALLMULTI)
value |= MAC_CTRL_MC_ALL_EN;
/* value |= MAC_CTRL_LOOPBACK; */
iowrite32(value, hw->hw_addr + REG_MAC_CTRL);
}
/*
* atl1_set_mac - Change the Ethernet Address of the NIC
* @netdev: network interface device structure
* @p: pointer to an address structure
*
* Returns 0 on success, negative on failure
*/
static int atl1_set_mac(struct net_device *netdev, void *p)
{
struct atl1_adapter *adapter = netdev_priv(netdev);
struct sockaddr *addr = p;
if (netif_running(netdev))
return -EBUSY;
if (!is_valid_ether_addr(addr->sa_data))
return -EADDRNOTAVAIL;
memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
atl1_set_mac_addr(&adapter->hw);
return 0;
}
static u32 atl1_check_link(struct atl1_adapter *adapter)
{
struct atl1_hw *hw = &adapter->hw;
struct net_device *netdev = adapter->netdev;
u32 ret_val;
u16 speed, duplex, phy_data;
int reconfig = 0;
/* MII_BMSR must read twice */
atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
if (!(phy_data & BMSR_LSTATUS)) { /* link down */
if (netif_carrier_ok(netdev)) { /* old link state: Up */
dev_info(&adapter->pdev->dev, "link is down\n");
adapter->link_speed = SPEED_0;
netif_carrier_off(netdev);
netif_stop_queue(netdev);
} }
return ATL1_SUCCESS;
}
/* /* Link Up */
* Make buffer alignment 2 beyond a 16 byte boundary ret_val = atl1_get_speed_and_duplex(hw, &speed, &duplex);
* this will result in a 16 byte aligned IP header after if (ret_val)
* the 14 byte MAC header is removed return ret_val;
*/
skb_reserve(skb, NET_IP_ALIGN);
buffer_info->alloced = 1; switch (hw->media_type) {
buffer_info->skb = skb; case MEDIA_TYPE_1000M_FULL:
buffer_info->length = (u16) adapter->rx_buffer_len; if (speed != SPEED_1000 || duplex != FULL_DUPLEX)
page = virt_to_page(skb->data); reconfig = 1;
offset = (unsigned long)skb->data & ~PAGE_MASK; break;
buffer_info->dma = pci_map_page(pdev, page, offset, case MEDIA_TYPE_100M_FULL:
adapter->rx_buffer_len, if (speed != SPEED_100 || duplex != FULL_DUPLEX)
PCI_DMA_FROMDEVICE); reconfig = 1;
rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma); break;
rfd_desc->buf_len = cpu_to_le16(adapter->rx_buffer_len); case MEDIA_TYPE_100M_HALF:
rfd_desc->coalese = 0; if (speed != SPEED_100 || duplex != HALF_DUPLEX)
reconfig = 1;
break;
case MEDIA_TYPE_10M_FULL:
if (speed != SPEED_10 || duplex != FULL_DUPLEX)
reconfig = 1;
break;
case MEDIA_TYPE_10M_HALF:
if (speed != SPEED_10 || duplex != HALF_DUPLEX)
reconfig = 1;
break;
}
next: /* link result is our setting */
rfd_next_to_use = next_next; if (!reconfig) {
if (unlikely(++next_next == rfd_ring->count)) if (adapter->link_speed != speed
next_next = 0; || adapter->link_duplex != duplex) {
adapter->link_speed = speed;
adapter->link_duplex = duplex;
atl1_setup_mac_ctrl(adapter);
dev_info(&adapter->pdev->dev,
"%s link is up %d Mbps %s\n",
netdev->name, adapter->link_speed,
adapter->link_duplex == FULL_DUPLEX ?
"full duplex" : "half duplex");
}
if (!netif_carrier_ok(netdev)) { /* Link down -> Up */
netif_carrier_on(netdev);
netif_wake_queue(netdev);
}
return ATL1_SUCCESS;
}
buffer_info = &rfd_ring->buffer_info[rfd_next_to_use]; /* change orignal link status */
next_info = &rfd_ring->buffer_info[next_next]; if (netif_carrier_ok(netdev)) {
num_alloc++; adapter->link_speed = SPEED_0;
netif_carrier_off(netdev);
netif_stop_queue(netdev);
} }
if (num_alloc) { if (hw->media_type != MEDIA_TYPE_AUTO_SENSOR &&
/* hw->media_type != MEDIA_TYPE_1000M_FULL) {
* Force memory writes to complete before letting h/w switch (hw->media_type) {
* know there are new descriptors to fetch. (Only case MEDIA_TYPE_100M_FULL:
* applicable for weak-ordered memory model archs, phy_data = MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
* such as IA-64). MII_CR_RESET;
*/ break;
wmb(); case MEDIA_TYPE_100M_HALF:
atomic_set(&rfd_ring->next_to_use, (int)rfd_next_to_use); phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
break;
case MEDIA_TYPE_10M_FULL:
phy_data =
MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
break;
default: /* MEDIA_TYPE_10M_HALF: */
phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
break;
}
atl1_write_phy_reg(hw, MII_BMCR, phy_data);
return ATL1_SUCCESS;
} }
return num_alloc;
/* auto-neg, insert timer to re-config phy */
if (!adapter->phy_timer_pending) {
adapter->phy_timer_pending = true;
mod_timer(&adapter->phy_config_timer, jiffies + 3 * HZ);
}
return ATL1_SUCCESS;
} }
static void atl1_clean_alloc_flag(struct atl1_adapter *adapter, static void atl1_check_for_link(struct atl1_adapter *adapter)
struct rx_return_desc *rrd, u16 offset)
{ {
struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; struct net_device *netdev = adapter->netdev;
u16 phy_data = 0;
while (rfd_ring->next_to_clean != (rrd->buf_indx + offset)) { spin_lock(&adapter->lock);
rfd_ring->buffer_info[rfd_ring->next_to_clean].alloced = 0; adapter->phy_timer_pending = false;
if (++rfd_ring->next_to_clean == rfd_ring->count) { atl1_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
rfd_ring->next_to_clean = 0; atl1_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
spin_unlock(&adapter->lock);
/* notify upper layer link down ASAP */
if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */
if (netif_carrier_ok(netdev)) { /* old link state: Up */
dev_info(&adapter->pdev->dev, "%s link is down\n",
netdev->name);
adapter->link_speed = SPEED_0;
netif_carrier_off(netdev);
netif_stop_queue(netdev);
} }
} }
schedule_work(&adapter->link_chg_task);
} }
static void atl1_update_rfd_index(struct atl1_adapter *adapter, /*
struct rx_return_desc *rrd) * atl1_set_multi - Multicast and Promiscuous mode set
* @netdev: network interface device structure
*
* The set_multi entry point is called whenever the multicast address
* list or the network interface flags are updated. This routine is
* responsible for configuring the hardware for proper multicast,
* promiscuous mode, and all-multi behavior.
*/
static void atl1_set_multi(struct net_device *netdev)
{ {
u16 num_buf; struct atl1_adapter *adapter = netdev_priv(netdev);
struct atl1_hw *hw = &adapter->hw;
struct dev_mc_list *mc_ptr;
u32 rctl;
u32 hash_value;
num_buf = (rrd->xsz.xsum_sz.pkt_size + adapter->rx_buffer_len - 1) / /* Check for Promiscuous and All Multicast modes */
adapter->rx_buffer_len; rctl = ioread32(hw->hw_addr + REG_MAC_CTRL);
if (rrd->num_buf == num_buf) if (netdev->flags & IFF_PROMISC)
/* clean alloc flag for bad rrd */ rctl |= MAC_CTRL_PROMIS_EN;
atl1_clean_alloc_flag(adapter, rrd, num_buf); else if (netdev->flags & IFF_ALLMULTI) {
rctl |= MAC_CTRL_MC_ALL_EN;
rctl &= ~MAC_CTRL_PROMIS_EN;
} else
rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
iowrite32(rctl, hw->hw_addr + REG_MAC_CTRL);
/* clear the old settings from the multicast hash table */
iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
/* compute mc addresses' hash value ,and put it into hash table */
for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
hash_value = atl1_hash_mc_addr(hw, mc_ptr->dmi_addr);
atl1_hash_set(hw, hash_value);
}
} }
static void atl1_intr_rx(struct atl1_adapter *adapter) /*
* atl1_change_mtu - Change the Maximum Transfer Unit
* @netdev: network interface device structure
* @new_mtu: new value for maximum frame size
*
* Returns 0 on success, negative on failure
*/
static int atl1_change_mtu(struct net_device *netdev, int new_mtu)
{ {
int i, count; struct atl1_adapter *adapter = netdev_priv(netdev);
u16 length; int old_mtu = netdev->mtu;
u16 rrd_next_to_clean; int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
u32 value;
struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
struct atl1_buffer *buffer_info;
struct rx_return_desc *rrd;
struct sk_buff *skb;
count = 0; if ((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
(max_frame > MAX_JUMBO_FRAME_SIZE)) {
dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
return -EINVAL;
}
rrd_next_to_clean = atomic_read(&rrd_ring->next_to_clean); adapter->hw.max_frame_size = max_frame;
adapter->hw.tx_jumbo_task_th = (max_frame + 7) >> 3;
adapter->rx_buffer_len = (max_frame + 7) & ~7;
adapter->hw.rx_jumbo_th = adapter->rx_buffer_len / 8;
while (1) { netdev->mtu = new_mtu;
rrd = ATL1_RRD_DESC(rrd_ring, rrd_next_to_clean); if ((old_mtu != new_mtu) && netif_running(netdev)) {
i = 1; atl1_down(adapter);
if (likely(rrd->xsz.valid)) { /* packet valid */ atl1_up(adapter);
chk_rrd: }
/* check rrd status */
if (likely(rrd->num_buf == 1))
goto rrd_ok;
/* rrd seems to be bad */ return 0;
if (unlikely(i-- > 0)) { }
/* rrd may not be DMAed completely */
dev_printk(KERN_DEBUG, &adapter->pdev->dev,
"incomplete RRD DMA transfer\n");
udelay(1);
goto chk_rrd;
}
/* bad rrd */
dev_printk(KERN_DEBUG, &adapter->pdev->dev,
"bad RRD\n");
/* see if update RFD index */
if (rrd->num_buf > 1)
atl1_update_rfd_index(adapter, rrd);
/* update rrd */ static void set_flow_ctrl_old(struct atl1_adapter *adapter)
rrd->xsz.valid = 0; {
if (++rrd_next_to_clean == rrd_ring->count) u32 hi, lo, value;
rrd_next_to_clean = 0;
count++;
continue;
} else { /* current rrd still not be updated */
break; /* RFD Flow Control */
} value = adapter->rfd_ring.count;
rrd_ok: hi = value / 16;
/* clean alloc flag for bad rrd */ if (hi < 2)
atl1_clean_alloc_flag(adapter, rrd, 0); hi = 2;
lo = value * 7 / 8;
buffer_info = &rfd_ring->buffer_info[rrd->buf_indx]; value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
if (++rfd_ring->next_to_clean == rfd_ring->count) ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
rfd_ring->next_to_clean = 0; iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
/* update rrd next to clean */ /* RRD Flow Control */
if (++rrd_next_to_clean == rrd_ring->count) value = adapter->rrd_ring.count;
rrd_next_to_clean = 0; lo = value / 16;
count++; hi = value * 7 / 8;
if (lo < 2)
lo = 2;
value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
}
if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) { static void set_flow_ctrl_new(struct atl1_hw *hw)
if (!(rrd->err_flg & {
(ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM u32 hi, lo, value;
| ERR_FLAG_LEN))) {
/* packet error, don't need upstream */ /* RXF Flow Control */
buffer_info->alloced = 0; value = ioread32(hw->hw_addr + REG_SRAM_RXF_LEN);
rrd->xsz.valid = 0; lo = value / 16;
continue; if (lo < 192)
} lo = 192;
} hi = value * 7 / 8;
if (hi < lo)
hi = lo + 16;
value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
iowrite32(value, hw->hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
/* RRD Flow Control */
value = ioread32(hw->hw_addr + REG_SRAM_RRD_LEN);
lo = value / 8;
hi = value * 7 / 8;
if (lo < 2)
lo = 2;
if (hi < lo)
hi = lo + 3;
value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
iowrite32(value, hw->hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
}
/*
* atl1_configure - Configure Transmit&Receive Unit after Reset
* @adapter: board private structure
*
* Configure the Tx /Rx unit of the MAC after a reset.
*/
static u32 atl1_configure(struct atl1_adapter *adapter)
{
struct atl1_hw *hw = &adapter->hw;
u32 value;
/* clear interrupt status */
iowrite32(0xffffffff, adapter->hw.hw_addr + REG_ISR);
/* set MAC Address */
value = (((u32) hw->mac_addr[2]) << 24) |
(((u32) hw->mac_addr[3]) << 16) |
(((u32) hw->mac_addr[4]) << 8) |
(((u32) hw->mac_addr[5]));
iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
iowrite32(value, hw->hw_addr + (REG_MAC_STA_ADDR + 4));
/* tx / rx ring */
/* Good Receive */ /* HI base address */
pci_unmap_page(adapter->pdev, buffer_info->dma, iowrite32((u32) ((adapter->tpd_ring.dma & 0xffffffff00000000ULL) >> 32),
buffer_info->length, PCI_DMA_FROMDEVICE); hw->hw_addr + REG_DESC_BASE_ADDR_HI);
skb = buffer_info->skb; /* LO base address */
length = le16_to_cpu(rrd->xsz.xsum_sz.pkt_size); iowrite32((u32) (adapter->rfd_ring.dma & 0x00000000ffffffffULL),
hw->hw_addr + REG_DESC_RFD_ADDR_LO);
iowrite32((u32) (adapter->rrd_ring.dma & 0x00000000ffffffffULL),
hw->hw_addr + REG_DESC_RRD_ADDR_LO);
iowrite32((u32) (adapter->tpd_ring.dma & 0x00000000ffffffffULL),
hw->hw_addr + REG_DESC_TPD_ADDR_LO);
iowrite32((u32) (adapter->cmb.dma & 0x00000000ffffffffULL),
hw->hw_addr + REG_DESC_CMB_ADDR_LO);
iowrite32((u32) (adapter->smb.dma & 0x00000000ffffffffULL),
hw->hw_addr + REG_DESC_SMB_ADDR_LO);
skb_put(skb, length - ETHERNET_FCS_SIZE); /* element count */
value = adapter->rrd_ring.count;
value <<= 16;
value += adapter->rfd_ring.count;
iowrite32(value, hw->hw_addr + REG_DESC_RFD_RRD_RING_SIZE);
iowrite32(adapter->tpd_ring.count, hw->hw_addr +
REG_DESC_TPD_RING_SIZE);
/* Receive Checksum Offload */ /* Load Ptr */
atl1_rx_checksum(adapter, rrd, skb); iowrite32(1, hw->hw_addr + REG_LOAD_PTR);
skb->protocol = eth_type_trans(skb, adapter->netdev);
if (adapter->vlgrp && (rrd->pkt_flg & PACKET_FLAG_VLAN_INS)) { /* config Mailbox */
u16 vlan_tag = (rrd->vlan_tag >> 4) | value = ((atomic_read(&adapter->tpd_ring.next_to_use)
((rrd->vlan_tag & 7) << 13) | & MB_TPD_PROD_INDX_MASK) << MB_TPD_PROD_INDX_SHIFT) |
((rrd->vlan_tag & 8) << 9); ((atomic_read(&adapter->rrd_ring.next_to_clean)
vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag); & MB_RRD_CONS_INDX_MASK) << MB_RRD_CONS_INDX_SHIFT) |
} else ((atomic_read(&adapter->rfd_ring.next_to_use)
netif_rx(skb); & MB_RFD_PROD_INDX_MASK) << MB_RFD_PROD_INDX_SHIFT);
iowrite32(value, hw->hw_addr + REG_MAILBOX);
/* let protocol layer free skb */ /* config IPG/IFG */
buffer_info->skb = NULL; value = (((u32) hw->ipgt & MAC_IPG_IFG_IPGT_MASK)
buffer_info->alloced = 0; << MAC_IPG_IFG_IPGT_SHIFT) |
rrd->xsz.valid = 0; (((u32) hw->min_ifg & MAC_IPG_IFG_MIFG_MASK)
<< MAC_IPG_IFG_MIFG_SHIFT) |
(((u32) hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK)
<< MAC_IPG_IFG_IPGR1_SHIFT) |
(((u32) hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK)
<< MAC_IPG_IFG_IPGR2_SHIFT);
iowrite32(value, hw->hw_addr + REG_MAC_IPG_IFG);
adapter->netdev->last_rx = jiffies; /* config Half-Duplex Control */
} value = ((u32) hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
(((u32) hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK)
<< MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
(0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
(((u32) hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK)
<< MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
iowrite32(value, hw->hw_addr + REG_MAC_HALF_DUPLX_CTRL);
atomic_set(&rrd_ring->next_to_clean, rrd_next_to_clean); /* set Interrupt Moderator Timer */
iowrite16(adapter->imt, hw->hw_addr + REG_IRQ_MODU_TIMER_INIT);
iowrite32(MASTER_CTRL_ITIMER_EN, hw->hw_addr + REG_MASTER_CTRL);
atl1_alloc_rx_buffers(adapter); /* set Interrupt Clear Timer */
iowrite16(adapter->ict, hw->hw_addr + REG_CMBDISDMA_TIMER);
/* update mailbox ? */ /* set MTU, 4 : VLAN */
if (count) { iowrite32(hw->max_frame_size + 4, hw->hw_addr + REG_MTU);
u32 tpd_next_to_use;
u32 rfd_next_to_use;
u32 rrd_next_to_clean;
spin_lock(&adapter->mb_lock); /* jumbo size & rrd retirement timer */
value = (((u32) hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK)
<< RXQ_JMBOSZ_TH_SHIFT) |
(((u32) hw->rx_jumbo_lkah & RXQ_JMBO_LKAH_MASK)
<< RXQ_JMBO_LKAH_SHIFT) |
(((u32) hw->rrd_ret_timer & RXQ_RRD_TIMER_MASK)
<< RXQ_RRD_TIMER_SHIFT);
iowrite32(value, hw->hw_addr + REG_RXQ_JMBOSZ_RRDTIM);
tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use); /* Flow Control */
rfd_next_to_use = switch (hw->dev_rev) {
atomic_read(&adapter->rfd_ring.next_to_use); case 0x8001:
rrd_next_to_clean = case 0x9001:
atomic_read(&adapter->rrd_ring.next_to_clean); case 0x9002:
value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) << case 0x9003:
MB_RFD_PROD_INDX_SHIFT) | set_flow_ctrl_old(adapter);
((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) << break;
MB_RRD_CONS_INDX_SHIFT) | default:
((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) << set_flow_ctrl_new(hw);
MB_TPD_PROD_INDX_SHIFT); break;
iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
spin_unlock(&adapter->mb_lock);
} }
}
static void atl1_intr_tx(struct atl1_adapter *adapter) /* config TXQ */
{ value = (((u32) hw->tpd_burst & TXQ_CTRL_TPD_BURST_NUM_MASK)
struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; << TXQ_CTRL_TPD_BURST_NUM_SHIFT) |
struct atl1_buffer *buffer_info; (((u32) hw->txf_burst & TXQ_CTRL_TXF_BURST_NUM_MASK)
u16 sw_tpd_next_to_clean; << TXQ_CTRL_TXF_BURST_NUM_SHIFT) |
u16 cmb_tpd_next_to_clean; (((u32) hw->tpd_fetch_th & TXQ_CTRL_TPD_FETCH_TH_MASK)
<< TXQ_CTRL_TPD_FETCH_TH_SHIFT) | TXQ_CTRL_ENH_MODE |
TXQ_CTRL_EN;
iowrite32(value, hw->hw_addr + REG_TXQ_CTRL);
sw_tpd_next_to_clean = atomic_read(&tpd_ring->next_to_clean); /* min tpd fetch gap & tx jumbo packet size threshold for taskoffload */
cmb_tpd_next_to_clean = le16_to_cpu(adapter->cmb.cmb->tpd_cons_idx); value = (((u32) hw->tx_jumbo_task_th & TX_JUMBO_TASK_TH_MASK)
<< TX_JUMBO_TASK_TH_SHIFT) |
(((u32) hw->tpd_fetch_gap & TX_TPD_MIN_IPG_MASK)
<< TX_TPD_MIN_IPG_SHIFT);
iowrite32(value, hw->hw_addr + REG_TX_JUMBO_TASK_TH_TPD_IPG);
while (cmb_tpd_next_to_clean != sw_tpd_next_to_clean) { /* config RXQ */
struct tx_packet_desc *tpd; value = (((u32) hw->rfd_burst & RXQ_CTRL_RFD_BURST_NUM_MASK)
<< RXQ_CTRL_RFD_BURST_NUM_SHIFT) |
(((u32) hw->rrd_burst & RXQ_CTRL_RRD_BURST_THRESH_MASK)
<< RXQ_CTRL_RRD_BURST_THRESH_SHIFT) |
(((u32) hw->rfd_fetch_gap & RXQ_CTRL_RFD_PREF_MIN_IPG_MASK)
<< RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT) | RXQ_CTRL_CUT_THRU_EN |
RXQ_CTRL_EN;
iowrite32(value, hw->hw_addr + REG_RXQ_CTRL);
tpd = ATL1_TPD_DESC(tpd_ring, sw_tpd_next_to_clean); /* config DMA Engine */
buffer_info = &tpd_ring->buffer_info[sw_tpd_next_to_clean]; value = ((((u32) hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
if (buffer_info->dma) { << DMA_CTRL_DMAR_BURST_LEN_SHIFT) |
pci_unmap_page(adapter->pdev, buffer_info->dma, ((((u32) hw->dmaw_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
buffer_info->length, PCI_DMA_TODEVICE); << DMA_CTRL_DMAR_BURST_LEN_SHIFT) | DMA_CTRL_DMAR_EN |
buffer_info->dma = 0; DMA_CTRL_DMAW_EN;
} value |= (u32) hw->dma_ord;
if (atl1_rcb_128 == hw->rcb_value)
value |= DMA_CTRL_RCB_VALUE;
iowrite32(value, hw->hw_addr + REG_DMA_CTRL);
if (buffer_info->skb) { /* config CMB / SMB */
dev_kfree_skb_irq(buffer_info->skb); value = hw->cmb_rrd | ((u32) hw->cmb_tpd << 16);
buffer_info->skb = NULL; iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TH);
} value = hw->cmb_rx_timer | ((u32) hw->cmb_tx_timer << 16);
tpd->buffer_addr = 0; iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TIMER);
tpd->desc.data = 0; iowrite32(hw->smb_timer, hw->hw_addr + REG_SMB_TIMER);
if (++sw_tpd_next_to_clean == tpd_ring->count) /* --- enable CMB / SMB */
sw_tpd_next_to_clean = 0; value = CSMB_CTRL_CMB_EN | CSMB_CTRL_SMB_EN;
} iowrite32(value, hw->hw_addr + REG_CSMB_CTRL);
atomic_set(&tpd_ring->next_to_clean, sw_tpd_next_to_clean);
if (netif_queue_stopped(adapter->netdev) value = ioread32(adapter->hw.hw_addr + REG_ISR);
&& netif_carrier_ok(adapter->netdev)) if (unlikely((value & ISR_PHY_LINKDOWN) != 0))
netif_wake_queue(adapter->netdev); value = 1; /* config failed */
else
value = 0;
/* clear all interrupt status */
iowrite32(0x3fffffff, adapter->hw.hw_addr + REG_ISR);
iowrite32(0, adapter->hw.hw_addr + REG_ISR);
return value;
} }
static void atl1_check_for_link(struct atl1_adapter *adapter) /*
* atl1_pcie_patch - Patch for PCIE module
*/
static void atl1_pcie_patch(struct atl1_adapter *adapter)
{ {
struct net_device *netdev = adapter->netdev; u32 value;
u16 phy_data = 0;
spin_lock(&adapter->lock);
adapter->phy_timer_pending = false;
atl1_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
atl1_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
spin_unlock(&adapter->lock);
/* notify upper layer link down ASAP */ /* much vendor magic here */
if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */ value = 0x6500;
if (netif_carrier_ok(netdev)) { /* old link state: Up */ iowrite32(value, adapter->hw.hw_addr + 0x12FC);
dev_info(&adapter->pdev->dev, "%s link is down\n", /* pcie flow control mode change */
netdev->name); value = ioread32(adapter->hw.hw_addr + 0x1008);
adapter->link_speed = SPEED_0; value |= 0x8000;
netif_carrier_off(netdev); iowrite32(value, adapter->hw.hw_addr + 0x1008);
netif_stop_queue(netdev);
}
}
schedule_work(&adapter->link_chg_task);
} }
/* /*
* atl1_intr - Interrupt Handler * When ACPI resume on some VIA MotherBoard, the Interrupt Disable bit/0x400
* @irq: interrupt number * on PCI Command register is disable.
* @data: pointer to a network interface device structure * The function enable this bit.
* @pt_regs: CPU registers structure * Brackett, 2006/03/15
*/ */
static irqreturn_t atl1_intr(int irq, void *data) static void atl1_via_workaround(struct atl1_adapter *adapter)
{ {
struct atl1_adapter *adapter = netdev_priv(data); unsigned long value;
u32 status;
u8 update_rx;
int max_ints = 10;
status = adapter->cmb.cmb->int_stats;
if (!status)
return IRQ_NONE;
update_rx = 0;
do { value = ioread16(adapter->hw.hw_addr + PCI_COMMAND);
/* clear CMB interrupt status at once */ if (value & PCI_COMMAND_INTX_DISABLE)
adapter->cmb.cmb->int_stats = 0; value &= ~PCI_COMMAND_INTX_DISABLE;
iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND);
}
if (status & ISR_GPHY) /* clear phy status */ /*
atl1_clear_phy_int(adapter); * atl1_irq_enable - Enable default interrupt generation settings
* @adapter: board private structure
*/
static void atl1_irq_enable(struct atl1_adapter *adapter)
{
iowrite32(IMR_NORMAL_MASK, adapter->hw.hw_addr + REG_IMR);
ioread32(adapter->hw.hw_addr + REG_IMR);
}
/* clear ISR status, and Enable CMB DMA/Disable Interrupt */ /*
iowrite32(status | ISR_DIS_INT, adapter->hw.hw_addr + REG_ISR); * atl1_irq_disable - Mask off interrupt generation on the NIC
* @adapter: board private structure
*/
static void atl1_irq_disable(struct atl1_adapter *adapter)
{
iowrite32(0, adapter->hw.hw_addr + REG_IMR);
ioread32(adapter->hw.hw_addr + REG_IMR);
synchronize_irq(adapter->pdev->irq);
}
/* check if SMB intr */ static void atl1_clear_phy_int(struct atl1_adapter *adapter)
if (status & ISR_SMB) {
atl1_inc_smb(adapter); u16 phy_data;
unsigned long flags;
/* check if PCIE PHY Link down */ spin_lock_irqsave(&adapter->lock, flags);
if (status & ISR_PHY_LINKDOWN) { atl1_read_phy_reg(&adapter->hw, 19, &phy_data);
dev_printk(KERN_DEBUG, &adapter->pdev->dev, spin_unlock_irqrestore(&adapter->lock, flags);
"pcie phy link down %x\n", status); }
if (netif_running(adapter->netdev)) { /* reset MAC */
iowrite32(0, adapter->hw.hw_addr + REG_IMR);
schedule_work(&adapter->pcie_dma_to_rst_task);
return IRQ_HANDLED;
}
}
/* check if DMA read/write error ? */ static void atl1_inc_smb(struct atl1_adapter *adapter)
if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) { {
dev_printk(KERN_DEBUG, &adapter->pdev->dev, struct stats_msg_block *smb = adapter->smb.smb;
"pcie DMA r/w error (status = 0x%x)\n",
status);
iowrite32(0, adapter->hw.hw_addr + REG_IMR);
schedule_work(&adapter->pcie_dma_to_rst_task);
return IRQ_HANDLED;
}
/* link event */ /* Fill out the OS statistics structure */
if (status & ISR_GPHY) { adapter->soft_stats.rx_packets += smb->rx_ok;
adapter->soft_stats.tx_carrier_errors++; adapter->soft_stats.tx_packets += smb->tx_ok;
atl1_check_for_link(adapter); adapter->soft_stats.rx_bytes += smb->rx_byte_cnt;
} adapter->soft_stats.tx_bytes += smb->tx_byte_cnt;
adapter->soft_stats.multicast += smb->rx_mcast;
adapter->soft_stats.collisions += (smb->tx_1_col + smb->tx_2_col * 2 +
smb->tx_late_col + smb->tx_abort_col * adapter->hw.max_retry);
/* transmit event */ /* Rx Errors */
if (status & ISR_CMB_TX) adapter->soft_stats.rx_errors += (smb->rx_frag + smb->rx_fcs_err +
atl1_intr_tx(adapter); smb->rx_len_err + smb->rx_sz_ov + smb->rx_rxf_ov +
smb->rx_rrd_ov + smb->rx_align_err);
adapter->soft_stats.rx_fifo_errors += smb->rx_rxf_ov;
adapter->soft_stats.rx_length_errors += smb->rx_len_err;
adapter->soft_stats.rx_crc_errors += smb->rx_fcs_err;
adapter->soft_stats.rx_frame_errors += smb->rx_align_err;
adapter->soft_stats.rx_missed_errors += (smb->rx_rrd_ov +
smb->rx_rxf_ov);
/* rx exception */ adapter->soft_stats.rx_pause += smb->rx_pause;
if (unlikely(status & (ISR_RXF_OV | ISR_RFD_UNRUN | adapter->soft_stats.rx_rrd_ov += smb->rx_rrd_ov;
ISR_RRD_OV | ISR_HOST_RFD_UNRUN | adapter->soft_stats.rx_trunc += smb->rx_sz_ov;
ISR_HOST_RRD_OV | ISR_CMB_RX))) {
if (status & (ISR_RXF_OV | ISR_RFD_UNRUN |
ISR_RRD_OV | ISR_HOST_RFD_UNRUN |
ISR_HOST_RRD_OV))
dev_printk(KERN_DEBUG, &adapter->pdev->dev,
"rx exception, ISR = 0x%x\n", status);
atl1_intr_rx(adapter);
}
if (--max_ints < 0) /* Tx Errors */
break; adapter->soft_stats.tx_errors += (smb->tx_late_col +
smb->tx_abort_col + smb->tx_underrun + smb->tx_trunc);
adapter->soft_stats.tx_fifo_errors += smb->tx_underrun;
adapter->soft_stats.tx_aborted_errors += smb->tx_abort_col;
adapter->soft_stats.tx_window_errors += smb->tx_late_col;
} while ((status = adapter->cmb.cmb->int_stats)); adapter->soft_stats.excecol += smb->tx_abort_col;
adapter->soft_stats.deffer += smb->tx_defer;
adapter->soft_stats.scc += smb->tx_1_col;
adapter->soft_stats.mcc += smb->tx_2_col;
adapter->soft_stats.latecol += smb->tx_late_col;
adapter->soft_stats.tx_underun += smb->tx_underrun;
adapter->soft_stats.tx_trunc += smb->tx_trunc;
adapter->soft_stats.tx_pause += smb->tx_pause;
/* re-enable Interrupt */ adapter->net_stats.rx_packets = adapter->soft_stats.rx_packets;
iowrite32(ISR_DIS_SMB | ISR_DIS_DMA, adapter->hw.hw_addr + REG_ISR); adapter->net_stats.tx_packets = adapter->soft_stats.tx_packets;
return IRQ_HANDLED; adapter->net_stats.rx_bytes = adapter->soft_stats.rx_bytes;
adapter->net_stats.tx_bytes = adapter->soft_stats.tx_bytes;
adapter->net_stats.multicast = adapter->soft_stats.multicast;
adapter->net_stats.collisions = adapter->soft_stats.collisions;
adapter->net_stats.rx_errors = adapter->soft_stats.rx_errors;
adapter->net_stats.rx_over_errors =
adapter->soft_stats.rx_missed_errors;
adapter->net_stats.rx_length_errors =
adapter->soft_stats.rx_length_errors;
adapter->net_stats.rx_crc_errors = adapter->soft_stats.rx_crc_errors;
adapter->net_stats.rx_frame_errors =
adapter->soft_stats.rx_frame_errors;
adapter->net_stats.rx_fifo_errors = adapter->soft_stats.rx_fifo_errors;
adapter->net_stats.rx_missed_errors =
adapter->soft_stats.rx_missed_errors;
adapter->net_stats.tx_errors = adapter->soft_stats.tx_errors;
adapter->net_stats.tx_fifo_errors = adapter->soft_stats.tx_fifo_errors;
adapter->net_stats.tx_aborted_errors =
adapter->soft_stats.tx_aborted_errors;
adapter->net_stats.tx_window_errors =
adapter->soft_stats.tx_window_errors;
adapter->net_stats.tx_carrier_errors =
adapter->soft_stats.tx_carrier_errors;
} }
/* /*
* atl1_set_multi - Multicast and Promiscuous mode set * atl1_get_stats - Get System Network Statistics
* @netdev: network interface device structure * @netdev: network interface device structure
* *
* The set_multi entry point is called whenever the multicast address * Returns the address of the device statistics structure.
* list or the network interface flags are updated. This routine is * The statistics are actually updated from the timer callback.
* responsible for configuring the hardware for proper multicast,
* promiscuous mode, and all-multi behavior.
*/ */
static void atl1_set_multi(struct net_device *netdev) static struct net_device_stats *atl1_get_stats(struct net_device *netdev)
{ {
struct atl1_adapter *adapter = netdev_priv(netdev); struct atl1_adapter *adapter = netdev_priv(netdev);
struct atl1_hw *hw = &adapter->hw; return &adapter->net_stats;
struct dev_mc_list *mc_ptr; }
u32 rctl;
u32 hash_value;
/* Check for Promiscuous and All Multicast modes */ static void atl1_update_mailbox(struct atl1_adapter *adapter)
rctl = ioread32(hw->hw_addr + REG_MAC_CTRL); {
if (netdev->flags & IFF_PROMISC) unsigned long flags;
rctl |= MAC_CTRL_PROMIS_EN; u32 tpd_next_to_use;
else if (netdev->flags & IFF_ALLMULTI) { u32 rfd_next_to_use;
rctl |= MAC_CTRL_MC_ALL_EN; u32 rrd_next_to_clean;
rctl &= ~MAC_CTRL_PROMIS_EN; u32 value;
} else
rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
iowrite32(rctl, hw->hw_addr + REG_MAC_CTRL); spin_lock_irqsave(&adapter->mb_lock, flags);
/* clear the old settings from the multicast hash table */ tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE); rfd_next_to_use = atomic_read(&adapter->rfd_ring.next_to_use);
iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2)); rrd_next_to_clean = atomic_read(&adapter->rrd_ring.next_to_clean);
/* compute mc addresses' hash value ,and put it into hash table */ value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) { MB_RFD_PROD_INDX_SHIFT) |
hash_value = atl1_hash_mc_addr(hw, mc_ptr->dmi_addr); ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
atl1_hash_set(hw, hash_value); MB_RRD_CONS_INDX_SHIFT) |
} ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
} MB_TPD_PROD_INDX_SHIFT);
iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter) spin_unlock_irqrestore(&adapter->mb_lock, flags);
{
u32 value;
struct atl1_hw *hw = &adapter->hw;
struct net_device *netdev = adapter->netdev;
/* Config MAC CTRL Register */
value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN;
/* duplex */
if (FULL_DUPLEX == adapter->link_duplex)
value |= MAC_CTRL_DUPLX;
/* speed */
value |= ((u32) ((SPEED_1000 == adapter->link_speed) ?
MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) <<
MAC_CTRL_SPEED_SHIFT);
/* flow control */
value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
/* PAD & CRC */
value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
/* preamble length */
value |= (((u32) adapter->hw.preamble_len
& MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
/* vlan */
if (adapter->vlgrp)
value |= MAC_CTRL_RMV_VLAN;
/* rx checksum
if (adapter->rx_csum)
value |= MAC_CTRL_RX_CHKSUM_EN;
*/
/* filter mode */
value |= MAC_CTRL_BC_EN;
if (netdev->flags & IFF_PROMISC)
value |= MAC_CTRL_PROMIS_EN;
else if (netdev->flags & IFF_ALLMULTI)
value |= MAC_CTRL_MC_ALL_EN;
/* value |= MAC_CTRL_LOOPBACK; */
iowrite32(value, hw->hw_addr + REG_MAC_CTRL);
} }
static u32 atl1_check_link(struct atl1_adapter *adapter) static void atl1_clean_alloc_flag(struct atl1_adapter *adapter,
{ struct rx_return_desc *rrd, u16 offset)
struct atl1_hw *hw = &adapter->hw; {
struct net_device *netdev = adapter->netdev; struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
u32 ret_val;
u16 speed, duplex, phy_data; while (rfd_ring->next_to_clean != (rrd->buf_indx + offset)) {
int reconfig = 0; rfd_ring->buffer_info[rfd_ring->next_to_clean].alloced = 0;
if (++rfd_ring->next_to_clean == rfd_ring->count) {
/* MII_BMSR must read twice */ rfd_ring->next_to_clean = 0;
atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
if (!(phy_data & BMSR_LSTATUS)) { /* link down */
if (netif_carrier_ok(netdev)) { /* old link state: Up */
dev_info(&adapter->pdev->dev, "link is down\n");
adapter->link_speed = SPEED_0;
netif_carrier_off(netdev);
netif_stop_queue(netdev);
} }
return ATL1_SUCCESS;
} }
}
/* Link Up */ static void atl1_update_rfd_index(struct atl1_adapter *adapter,
ret_val = atl1_get_speed_and_duplex(hw, &speed, &duplex); struct rx_return_desc *rrd)
if (ret_val) {
return ret_val; u16 num_buf;
switch (hw->media_type) { num_buf = (rrd->xsz.xsum_sz.pkt_size + adapter->rx_buffer_len - 1) /
case MEDIA_TYPE_1000M_FULL: adapter->rx_buffer_len;
if (speed != SPEED_1000 || duplex != FULL_DUPLEX) if (rrd->num_buf == num_buf)
reconfig = 1; /* clean alloc flag for bad rrd */
break; atl1_clean_alloc_flag(adapter, rrd, num_buf);
case MEDIA_TYPE_100M_FULL: }
if (speed != SPEED_100 || duplex != FULL_DUPLEX)
reconfig = 1;
break;
case MEDIA_TYPE_100M_HALF:
if (speed != SPEED_100 || duplex != HALF_DUPLEX)
reconfig = 1;
break;
case MEDIA_TYPE_10M_FULL:
if (speed != SPEED_10 || duplex != FULL_DUPLEX)
reconfig = 1;
break;
case MEDIA_TYPE_10M_HALF:
if (speed != SPEED_10 || duplex != HALF_DUPLEX)
reconfig = 1;
break;
}
/* link result is our setting */ static void atl1_rx_checksum(struct atl1_adapter *adapter,
if (!reconfig) { struct rx_return_desc *rrd, struct sk_buff *skb)
if (adapter->link_speed != speed {
|| adapter->link_duplex != duplex) { struct pci_dev *pdev = adapter->pdev;
adapter->link_speed = speed;
adapter->link_duplex = duplex;
atl1_setup_mac_ctrl(adapter);
dev_info(&adapter->pdev->dev,
"%s link is up %d Mbps %s\n",
netdev->name, adapter->link_speed,
adapter->link_duplex == FULL_DUPLEX ?
"full duplex" : "half duplex");
}
if (!netif_carrier_ok(netdev)) { /* Link down -> Up */
netif_carrier_on(netdev);
netif_wake_queue(netdev);
}
return ATL1_SUCCESS;
}
/* change orignal link status */ skb->ip_summed = CHECKSUM_NONE;
if (netif_carrier_ok(netdev)) {
adapter->link_speed = SPEED_0;
netif_carrier_off(netdev);
netif_stop_queue(netdev);
}
if (hw->media_type != MEDIA_TYPE_AUTO_SENSOR && if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
hw->media_type != MEDIA_TYPE_1000M_FULL) { if (rrd->err_flg & (ERR_FLAG_CRC | ERR_FLAG_TRUNC |
switch (hw->media_type) { ERR_FLAG_CODE | ERR_FLAG_OV)) {
case MEDIA_TYPE_100M_FULL: adapter->hw_csum_err++;
phy_data = MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 | dev_printk(KERN_DEBUG, &pdev->dev,
MII_CR_RESET; "rx checksum error\n");
break; return;
case MEDIA_TYPE_100M_HALF:
phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
break;
case MEDIA_TYPE_10M_FULL:
phy_data =
MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
break;
default: /* MEDIA_TYPE_10M_HALF: */
phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
break;
} }
atl1_write_phy_reg(hw, MII_BMCR, phy_data);
return ATL1_SUCCESS;
} }
/* auto-neg, insert timer to re-config phy */ /* not IPv4 */
if (!adapter->phy_timer_pending) { if (!(rrd->pkt_flg & PACKET_FLAG_IPV4))
adapter->phy_timer_pending = true; /* checksum is invalid, but it's not an IPv4 pkt, so ok */
mod_timer(&adapter->phy_config_timer, jiffies + 3 * HZ); return;
/* IPv4 packet */
if (likely(!(rrd->err_flg &
(ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM)))) {
skb->ip_summed = CHECKSUM_UNNECESSARY;
adapter->hw_csum_good++;
return;
} }
return ATL1_SUCCESS; /* IPv4, but hardware thinks its checksum is wrong */
dev_printk(KERN_DEBUG, &pdev->dev,
"hw csum wrong, pkt_flag:%x, err_flag:%x\n",
rrd->pkt_flg, rrd->err_flg);
skb->ip_summed = CHECKSUM_COMPLETE;
skb->csum = htons(rrd->xsz.xsum_sz.rx_chksum);
adapter->hw_csum_err++;
return;
} }
static void set_flow_ctrl_old(struct atl1_adapter *adapter) /*
* atl1_alloc_rx_buffers - Replace used receive buffers
* @adapter: address of board private structure
*/
static u16 atl1_alloc_rx_buffers(struct atl1_adapter *adapter)
{ {
u32 hi, lo, value; struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
struct pci_dev *pdev = adapter->pdev;
struct page *page;
unsigned long offset;
struct atl1_buffer *buffer_info, *next_info;
struct sk_buff *skb;
u16 num_alloc = 0;
u16 rfd_next_to_use, next_next;
struct rx_free_desc *rfd_desc;
/* RFD Flow Control */ next_next = rfd_next_to_use = atomic_read(&rfd_ring->next_to_use);
value = adapter->rfd_ring.count; if (++next_next == rfd_ring->count)
hi = value / 16; next_next = 0;
if (hi < 2) buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
hi = 2; next_info = &rfd_ring->buffer_info[next_next];
lo = value * 7 / 8;
value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) | while (!buffer_info->alloced && !next_info->alloced) {
((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT); if (buffer_info->skb) {
iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RXF_PAUSE_THRESH); buffer_info->alloced = 1;
goto next;
}
/* RRD Flow Control */ rfd_desc = ATL1_RFD_DESC(rfd_ring, rfd_next_to_use);
value = adapter->rrd_ring.count;
lo = value / 16;
hi = value * 7 / 8;
if (lo < 2)
lo = 2;
value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
}
static void set_flow_ctrl_new(struct atl1_hw *hw) skb = dev_alloc_skb(adapter->rx_buffer_len + NET_IP_ALIGN);
{ if (unlikely(!skb)) { /* Better luck next round */
u32 hi, lo, value; adapter->net_stats.rx_dropped++;
break;
}
/* RXF Flow Control */ /*
value = ioread32(hw->hw_addr + REG_SRAM_RXF_LEN); * Make buffer alignment 2 beyond a 16 byte boundary
lo = value / 16; * this will result in a 16 byte aligned IP header after
if (lo < 192) * the 14 byte MAC header is removed
lo = 192; */
hi = value * 7 / 8; skb_reserve(skb, NET_IP_ALIGN);
if (hi < lo)
hi = lo + 16;
value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
iowrite32(value, hw->hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
/* RRD Flow Control */ buffer_info->alloced = 1;
value = ioread32(hw->hw_addr + REG_SRAM_RRD_LEN); buffer_info->skb = skb;
lo = value / 8; buffer_info->length = (u16) adapter->rx_buffer_len;
hi = value * 7 / 8; page = virt_to_page(skb->data);
if (lo < 2) offset = (unsigned long)skb->data & ~PAGE_MASK;
lo = 2; buffer_info->dma = pci_map_page(pdev, page, offset,
if (hi < lo) adapter->rx_buffer_len,
hi = lo + 3; PCI_DMA_FROMDEVICE);
value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) | rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT); rfd_desc->buf_len = cpu_to_le16(adapter->rx_buffer_len);
iowrite32(value, hw->hw_addr + REG_RXQ_RRD_PAUSE_THRESH); rfd_desc->coalese = 0;
}
/* next:
* atl1_configure - Configure Transmit&Receive Unit after Reset rfd_next_to_use = next_next;
* @adapter: board private structure if (unlikely(++next_next == rfd_ring->count))
* next_next = 0;
* Configure the Tx /Rx unit of the MAC after a reset.
*/
static u32 atl1_configure(struct atl1_adapter *adapter)
{
struct atl1_hw *hw = &adapter->hw;
u32 value;
/* clear interrupt status */ buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
iowrite32(0xffffffff, adapter->hw.hw_addr + REG_ISR); next_info = &rfd_ring->buffer_info[next_next];
num_alloc++;
}
/* set MAC Address */ if (num_alloc) {
value = (((u32) hw->mac_addr[2]) << 24) | /*
(((u32) hw->mac_addr[3]) << 16) | * Force memory writes to complete before letting h/w
(((u32) hw->mac_addr[4]) << 8) | * know there are new descriptors to fetch. (Only
(((u32) hw->mac_addr[5])); * applicable for weak-ordered memory model archs,
iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR); * such as IA-64).
value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1])); */
iowrite32(value, hw->hw_addr + (REG_MAC_STA_ADDR + 4)); wmb();
atomic_set(&rfd_ring->next_to_use, (int)rfd_next_to_use);
}
return num_alloc;
}
/* tx / rx ring */ static void atl1_intr_rx(struct atl1_adapter *adapter)
{
int i, count;
u16 length;
u16 rrd_next_to_clean;
u32 value;
struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
struct atl1_buffer *buffer_info;
struct rx_return_desc *rrd;
struct sk_buff *skb;
/* HI base address */ count = 0;
iowrite32((u32) ((adapter->tpd_ring.dma & 0xffffffff00000000ULL) >> 32),
hw->hw_addr + REG_DESC_BASE_ADDR_HI);
/* LO base address */
iowrite32((u32) (adapter->rfd_ring.dma & 0x00000000ffffffffULL),
hw->hw_addr + REG_DESC_RFD_ADDR_LO);
iowrite32((u32) (adapter->rrd_ring.dma & 0x00000000ffffffffULL),
hw->hw_addr + REG_DESC_RRD_ADDR_LO);
iowrite32((u32) (adapter->tpd_ring.dma & 0x00000000ffffffffULL),
hw->hw_addr + REG_DESC_TPD_ADDR_LO);
iowrite32((u32) (adapter->cmb.dma & 0x00000000ffffffffULL),
hw->hw_addr + REG_DESC_CMB_ADDR_LO);
iowrite32((u32) (adapter->smb.dma & 0x00000000ffffffffULL),
hw->hw_addr + REG_DESC_SMB_ADDR_LO);
/* element count */ rrd_next_to_clean = atomic_read(&rrd_ring->next_to_clean);
value = adapter->rrd_ring.count;
value <<= 16;
value += adapter->rfd_ring.count;
iowrite32(value, hw->hw_addr + REG_DESC_RFD_RRD_RING_SIZE);
iowrite32(adapter->tpd_ring.count, hw->hw_addr +
REG_DESC_TPD_RING_SIZE);
/* Load Ptr */ while (1) {
iowrite32(1, hw->hw_addr + REG_LOAD_PTR); rrd = ATL1_RRD_DESC(rrd_ring, rrd_next_to_clean);
i = 1;
if (likely(rrd->xsz.valid)) { /* packet valid */
chk_rrd:
/* check rrd status */
if (likely(rrd->num_buf == 1))
goto rrd_ok;
/* config Mailbox */ /* rrd seems to be bad */
value = ((atomic_read(&adapter->tpd_ring.next_to_use) if (unlikely(i-- > 0)) {
& MB_TPD_PROD_INDX_MASK) << MB_TPD_PROD_INDX_SHIFT) | /* rrd may not be DMAed completely */
((atomic_read(&adapter->rrd_ring.next_to_clean) dev_printk(KERN_DEBUG, &adapter->pdev->dev,
& MB_RRD_CONS_INDX_MASK) << MB_RRD_CONS_INDX_SHIFT) | "incomplete RRD DMA transfer\n");
((atomic_read(&adapter->rfd_ring.next_to_use) udelay(1);
& MB_RFD_PROD_INDX_MASK) << MB_RFD_PROD_INDX_SHIFT); goto chk_rrd;
iowrite32(value, hw->hw_addr + REG_MAILBOX); }
/* bad rrd */
dev_printk(KERN_DEBUG, &adapter->pdev->dev,
"bad RRD\n");
/* see if update RFD index */
if (rrd->num_buf > 1)
atl1_update_rfd_index(adapter, rrd);
/* config IPG/IFG */ /* update rrd */
value = (((u32) hw->ipgt & MAC_IPG_IFG_IPGT_MASK) rrd->xsz.valid = 0;
<< MAC_IPG_IFG_IPGT_SHIFT) | if (++rrd_next_to_clean == rrd_ring->count)
(((u32) hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) rrd_next_to_clean = 0;
<< MAC_IPG_IFG_MIFG_SHIFT) | count++;
(((u32) hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) continue;
<< MAC_IPG_IFG_IPGR1_SHIFT) | } else { /* current rrd still not be updated */
(((u32) hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK)
<< MAC_IPG_IFG_IPGR2_SHIFT);
iowrite32(value, hw->hw_addr + REG_MAC_IPG_IFG);
/* config Half-Duplex Control */ break;
value = ((u32) hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) | }
(((u32) hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) rrd_ok:
<< MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) | /* clean alloc flag for bad rrd */
MAC_HALF_DUPLX_CTRL_EXC_DEF_EN | atl1_clean_alloc_flag(adapter, rrd, 0);
(0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
(((u32) hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK)
<< MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
iowrite32(value, hw->hw_addr + REG_MAC_HALF_DUPLX_CTRL);
/* set Interrupt Moderator Timer */ buffer_info = &rfd_ring->buffer_info[rrd->buf_indx];
iowrite16(adapter->imt, hw->hw_addr + REG_IRQ_MODU_TIMER_INIT); if (++rfd_ring->next_to_clean == rfd_ring->count)
iowrite32(MASTER_CTRL_ITIMER_EN, hw->hw_addr + REG_MASTER_CTRL); rfd_ring->next_to_clean = 0;
/* set Interrupt Clear Timer */ /* update rrd next to clean */
iowrite16(adapter->ict, hw->hw_addr + REG_CMBDISDMA_TIMER); if (++rrd_next_to_clean == rrd_ring->count)
rrd_next_to_clean = 0;
count++;
/* set MTU, 4 : VLAN */ if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
iowrite32(hw->max_frame_size + 4, hw->hw_addr + REG_MTU); if (!(rrd->err_flg &
(ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM
| ERR_FLAG_LEN))) {
/* packet error, don't need upstream */
buffer_info->alloced = 0;
rrd->xsz.valid = 0;
continue;
}
}
/* jumbo size & rrd retirement timer */ /* Good Receive */
value = (((u32) hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK) pci_unmap_page(adapter->pdev, buffer_info->dma,
<< RXQ_JMBOSZ_TH_SHIFT) | buffer_info->length, PCI_DMA_FROMDEVICE);
(((u32) hw->rx_jumbo_lkah & RXQ_JMBO_LKAH_MASK) skb = buffer_info->skb;
<< RXQ_JMBO_LKAH_SHIFT) | length = le16_to_cpu(rrd->xsz.xsum_sz.pkt_size);
(((u32) hw->rrd_ret_timer & RXQ_RRD_TIMER_MASK)
<< RXQ_RRD_TIMER_SHIFT);
iowrite32(value, hw->hw_addr + REG_RXQ_JMBOSZ_RRDTIM);
/* Flow Control */ skb_put(skb, length - ETHERNET_FCS_SIZE);
switch (hw->dev_rev) {
case 0x8001:
case 0x9001:
case 0x9002:
case 0x9003:
set_flow_ctrl_old(adapter);
break;
default:
set_flow_ctrl_new(hw);
break;
}
/* config TXQ */ /* Receive Checksum Offload */
value = (((u32) hw->tpd_burst & TXQ_CTRL_TPD_BURST_NUM_MASK) atl1_rx_checksum(adapter, rrd, skb);
<< TXQ_CTRL_TPD_BURST_NUM_SHIFT) | skb->protocol = eth_type_trans(skb, adapter->netdev);
(((u32) hw->txf_burst & TXQ_CTRL_TXF_BURST_NUM_MASK)
<< TXQ_CTRL_TXF_BURST_NUM_SHIFT) |
(((u32) hw->tpd_fetch_th & TXQ_CTRL_TPD_FETCH_TH_MASK)
<< TXQ_CTRL_TPD_FETCH_TH_SHIFT) | TXQ_CTRL_ENH_MODE |
TXQ_CTRL_EN;
iowrite32(value, hw->hw_addr + REG_TXQ_CTRL);
/* min tpd fetch gap & tx jumbo packet size threshold for taskoffload */ if (adapter->vlgrp && (rrd->pkt_flg & PACKET_FLAG_VLAN_INS)) {
value = (((u32) hw->tx_jumbo_task_th & TX_JUMBO_TASK_TH_MASK) u16 vlan_tag = (rrd->vlan_tag >> 4) |
<< TX_JUMBO_TASK_TH_SHIFT) | ((rrd->vlan_tag & 7) << 13) |
(((u32) hw->tpd_fetch_gap & TX_TPD_MIN_IPG_MASK) ((rrd->vlan_tag & 8) << 9);
<< TX_TPD_MIN_IPG_SHIFT); vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag);
iowrite32(value, hw->hw_addr + REG_TX_JUMBO_TASK_TH_TPD_IPG); } else
netif_rx(skb);
/* config RXQ */ /* let protocol layer free skb */
value = (((u32) hw->rfd_burst & RXQ_CTRL_RFD_BURST_NUM_MASK) buffer_info->skb = NULL;
<< RXQ_CTRL_RFD_BURST_NUM_SHIFT) | buffer_info->alloced = 0;
(((u32) hw->rrd_burst & RXQ_CTRL_RRD_BURST_THRESH_MASK) rrd->xsz.valid = 0;
<< RXQ_CTRL_RRD_BURST_THRESH_SHIFT) |
(((u32) hw->rfd_fetch_gap & RXQ_CTRL_RFD_PREF_MIN_IPG_MASK)
<< RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT) | RXQ_CTRL_CUT_THRU_EN |
RXQ_CTRL_EN;
iowrite32(value, hw->hw_addr + REG_RXQ_CTRL);
/* config DMA Engine */ adapter->netdev->last_rx = jiffies;
value = ((((u32) hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK) }
<< DMA_CTRL_DMAR_BURST_LEN_SHIFT) |
((((u32) hw->dmaw_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
<< DMA_CTRL_DMAR_BURST_LEN_SHIFT) | DMA_CTRL_DMAR_EN |
DMA_CTRL_DMAW_EN;
value |= (u32) hw->dma_ord;
if (atl1_rcb_128 == hw->rcb_value)
value |= DMA_CTRL_RCB_VALUE;
iowrite32(value, hw->hw_addr + REG_DMA_CTRL);
/* config CMB / SMB */ atomic_set(&rrd_ring->next_to_clean, rrd_next_to_clean);
value = hw->cmb_rrd | ((u32) hw->cmb_tpd << 16);
iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TH);
value = hw->cmb_rx_timer | ((u32) hw->cmb_tx_timer << 16);
iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TIMER);
iowrite32(hw->smb_timer, hw->hw_addr + REG_SMB_TIMER);
/* --- enable CMB / SMB */ atl1_alloc_rx_buffers(adapter);
value = CSMB_CTRL_CMB_EN | CSMB_CTRL_SMB_EN;
iowrite32(value, hw->hw_addr + REG_CSMB_CTRL);
value = ioread32(adapter->hw.hw_addr + REG_ISR); /* update mailbox ? */
if (unlikely((value & ISR_PHY_LINKDOWN) != 0)) if (count) {
value = 1; /* config failed */ u32 tpd_next_to_use;
else u32 rfd_next_to_use;
value = 0; u32 rrd_next_to_clean;
/* clear all interrupt status */ spin_lock(&adapter->mb_lock);
iowrite32(0x3fffffff, adapter->hw.hw_addr + REG_ISR);
iowrite32(0, adapter->hw.hw_addr + REG_ISR);
return value;
}
/* tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
* atl1_irq_disable - Mask off interrupt generation on the NIC rfd_next_to_use =
* @adapter: board private structure atomic_read(&adapter->rfd_ring.next_to_use);
*/ rrd_next_to_clean =
static void atl1_irq_disable(struct atl1_adapter *adapter) atomic_read(&adapter->rrd_ring.next_to_clean);
{ value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
iowrite32(0, adapter->hw.hw_addr + REG_IMR); MB_RFD_PROD_INDX_SHIFT) |
ioread32(adapter->hw.hw_addr + REG_IMR); ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
synchronize_irq(adapter->pdev->irq); MB_RRD_CONS_INDX_SHIFT) |
((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
MB_TPD_PROD_INDX_SHIFT);
iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
spin_unlock(&adapter->mb_lock);
}
} }
static void atl1_vlan_rx_register(struct net_device *netdev, static void atl1_intr_tx(struct atl1_adapter *adapter)
struct vlan_group *grp)
{ {
struct atl1_adapter *adapter = netdev_priv(netdev); struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
unsigned long flags; struct atl1_buffer *buffer_info;
u32 ctrl; u16 sw_tpd_next_to_clean;
u16 cmb_tpd_next_to_clean;
spin_lock_irqsave(&adapter->lock, flags); sw_tpd_next_to_clean = atomic_read(&tpd_ring->next_to_clean);
/* atl1_irq_disable(adapter); */ cmb_tpd_next_to_clean = le16_to_cpu(adapter->cmb.cmb->tpd_cons_idx);
adapter->vlgrp = grp;
if (grp) { while (cmb_tpd_next_to_clean != sw_tpd_next_to_clean) {
/* enable VLAN tag insert/strip */ struct tx_packet_desc *tpd;
ctrl = ioread32(adapter->hw.hw_addr + REG_MAC_CTRL);
ctrl |= MAC_CTRL_RMV_VLAN;
iowrite32(ctrl, adapter->hw.hw_addr + REG_MAC_CTRL);
} else {
/* disable VLAN tag insert/strip */
ctrl = ioread32(adapter->hw.hw_addr + REG_MAC_CTRL);
ctrl &= ~MAC_CTRL_RMV_VLAN;
iowrite32(ctrl, adapter->hw.hw_addr + REG_MAC_CTRL);
}
/* atl1_irq_enable(adapter); */ tpd = ATL1_TPD_DESC(tpd_ring, sw_tpd_next_to_clean);
spin_unlock_irqrestore(&adapter->lock, flags); buffer_info = &tpd_ring->buffer_info[sw_tpd_next_to_clean];
} if (buffer_info->dma) {
pci_unmap_page(adapter->pdev, buffer_info->dma,
buffer_info->length, PCI_DMA_TODEVICE);
buffer_info->dma = 0;
}
static void atl1_restore_vlan(struct atl1_adapter *adapter) if (buffer_info->skb) {
{ dev_kfree_skb_irq(buffer_info->skb);
atl1_vlan_rx_register(adapter->netdev, adapter->vlgrp); buffer_info->skb = NULL;
}
tpd->buffer_addr = 0;
tpd->desc.data = 0;
if (++sw_tpd_next_to_clean == tpd_ring->count)
sw_tpd_next_to_clean = 0;
}
atomic_set(&tpd_ring->next_to_clean, sw_tpd_next_to_clean);
if (netif_queue_stopped(adapter->netdev)
&& netif_carrier_ok(adapter->netdev))
netif_wake_queue(adapter->netdev);
} }
static u16 tpd_avail(struct atl1_tpd_ring *tpd_ring) static u16 tpd_avail(struct atl1_tpd_ring *tpd_ring)
...@@ -1465,31 +1646,6 @@ static void atl1_tx_queue(struct atl1_adapter *adapter, int count, ...@@ -1465,31 +1646,6 @@ static void atl1_tx_queue(struct atl1_adapter *adapter, int count,
atomic_set(&tpd_ring->next_to_use, (int)tpd_next_to_use); atomic_set(&tpd_ring->next_to_use, (int)tpd_next_to_use);
} }
static void atl1_update_mailbox(struct atl1_adapter *adapter)
{
unsigned long flags;
u32 tpd_next_to_use;
u32 rfd_next_to_use;
u32 rrd_next_to_clean;
u32 value;
spin_lock_irqsave(&adapter->mb_lock, flags);
tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
rfd_next_to_use = atomic_read(&adapter->rfd_ring.next_to_use);
rrd_next_to_clean = atomic_read(&adapter->rrd_ring.next_to_clean);
value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
MB_RFD_PROD_INDX_SHIFT) |
((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
MB_RRD_CONS_INDX_SHIFT) |
((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
MB_TPD_PROD_INDX_SHIFT);
iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
spin_unlock_irqrestore(&adapter->mb_lock, flags);
}
static int atl1_xmit_frame(struct sk_buff *skb, struct net_device *netdev) static int atl1_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
{ {
struct atl1_adapter *adapter = netdev_priv(netdev); struct atl1_adapter *adapter = netdev_priv(netdev);
...@@ -1601,129 +1757,208 @@ static int atl1_xmit_frame(struct sk_buff *skb, struct net_device *netdev) ...@@ -1601,129 +1757,208 @@ static int atl1_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
} }
/* /*
* atl1_get_stats - Get System Network Statistics * atl1_intr - Interrupt Handler
* @netdev: network interface device structure * @irq: interrupt number
* * @data: pointer to a network interface device structure
* Returns the address of the device statistics structure. * @pt_regs: CPU registers structure
* The statistics are actually updated from the timer callback.
*/ */
static struct net_device_stats *atl1_get_stats(struct net_device *netdev) static irqreturn_t atl1_intr(int irq, void *data)
{ {
struct atl1_adapter *adapter = netdev_priv(netdev); struct atl1_adapter *adapter = netdev_priv(data);
return &adapter->net_stats; u32 status;
} u8 update_rx;
int max_ints = 10;
/* status = adapter->cmb.cmb->int_stats;
* atl1_clean_rx_ring - Free RFD Buffers if (!status)
* @adapter: board private structure return IRQ_NONE;
*/
static void atl1_clean_rx_ring(struct atl1_adapter *adapter)
{
struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
struct atl1_buffer *buffer_info;
struct pci_dev *pdev = adapter->pdev;
unsigned long size;
unsigned int i;
/* Free all the Rx ring sk_buffs */ update_rx = 0;
for (i = 0; i < rfd_ring->count; i++) {
buffer_info = &rfd_ring->buffer_info[i]; do {
if (buffer_info->dma) { /* clear CMB interrupt status at once */
pci_unmap_page(pdev, buffer_info->dma, adapter->cmb.cmb->int_stats = 0;
buffer_info->length, PCI_DMA_FROMDEVICE);
buffer_info->dma = 0; if (status & ISR_GPHY) /* clear phy status */
atl1_clear_phy_int(adapter);
/* clear ISR status, and Enable CMB DMA/Disable Interrupt */
iowrite32(status | ISR_DIS_INT, adapter->hw.hw_addr + REG_ISR);
/* check if SMB intr */
if (status & ISR_SMB)
atl1_inc_smb(adapter);
/* check if PCIE PHY Link down */
if (status & ISR_PHY_LINKDOWN) {
dev_printk(KERN_DEBUG, &adapter->pdev->dev,
"pcie phy link down %x\n", status);
if (netif_running(adapter->netdev)) { /* reset MAC */
iowrite32(0, adapter->hw.hw_addr + REG_IMR);
schedule_work(&adapter->pcie_dma_to_rst_task);
return IRQ_HANDLED;
}
} }
if (buffer_info->skb) {
dev_kfree_skb(buffer_info->skb); /* check if DMA read/write error ? */
buffer_info->skb = NULL; if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
dev_printk(KERN_DEBUG, &adapter->pdev->dev,
"pcie DMA r/w error (status = 0x%x)\n",
status);
iowrite32(0, adapter->hw.hw_addr + REG_IMR);
schedule_work(&adapter->pcie_dma_to_rst_task);
return IRQ_HANDLED;
} }
}
size = sizeof(struct atl1_buffer) * rfd_ring->count; /* link event */
memset(rfd_ring->buffer_info, 0, size); if (status & ISR_GPHY) {
adapter->soft_stats.tx_carrier_errors++;
atl1_check_for_link(adapter);
}
/* Zero out the descriptor ring */ /* transmit event */
memset(rfd_ring->desc, 0, rfd_ring->size); if (status & ISR_CMB_TX)
atl1_intr_tx(adapter);
rfd_ring->next_to_clean = 0; /* rx exception */
atomic_set(&rfd_ring->next_to_use, 0); if (unlikely(status & (ISR_RXF_OV | ISR_RFD_UNRUN |
ISR_RRD_OV | ISR_HOST_RFD_UNRUN |
ISR_HOST_RRD_OV | ISR_CMB_RX))) {
if (status & (ISR_RXF_OV | ISR_RFD_UNRUN |
ISR_RRD_OV | ISR_HOST_RFD_UNRUN |
ISR_HOST_RRD_OV))
dev_printk(KERN_DEBUG, &adapter->pdev->dev,
"rx exception, ISR = 0x%x\n", status);
atl1_intr_rx(adapter);
}
rrd_ring->next_to_use = 0; if (--max_ints < 0)
atomic_set(&rrd_ring->next_to_clean, 0); break;
} while ((status = adapter->cmb.cmb->int_stats));
/* re-enable Interrupt */
iowrite32(ISR_DIS_SMB | ISR_DIS_DMA, adapter->hw.hw_addr + REG_ISR);
return IRQ_HANDLED;
} }
/* /*
* atl1_clean_tx_ring - Free Tx Buffers * atl1_watchdog - Timer Call-back
* @adapter: board private structure * @data: pointer to netdev cast into an unsigned long
*/ */
static void atl1_clean_tx_ring(struct atl1_adapter *adapter) static void atl1_watchdog(unsigned long data)
{ {
struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; struct atl1_adapter *adapter = (struct atl1_adapter *)data;
struct atl1_buffer *buffer_info;
struct pci_dev *pdev = adapter->pdev;
unsigned long size;
unsigned int i;
/* Free all the Tx ring sk_buffs */ /* Reset the timer */
for (i = 0; i < tpd_ring->count; i++) { mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
buffer_info = &tpd_ring->buffer_info[i]; }
if (buffer_info->dma) {
pci_unmap_page(pdev, buffer_info->dma,
buffer_info->length, PCI_DMA_TODEVICE);
buffer_info->dma = 0;
}
}
for (i = 0; i < tpd_ring->count; i++) { /*
buffer_info = &tpd_ring->buffer_info[i]; * atl1_phy_config - Timer Call-back
if (buffer_info->skb) { * @data: pointer to netdev cast into an unsigned long
dev_kfree_skb_any(buffer_info->skb); */
buffer_info->skb = NULL; static void atl1_phy_config(unsigned long data)
} {
} struct atl1_adapter *adapter = (struct atl1_adapter *)data;
struct atl1_hw *hw = &adapter->hw;
unsigned long flags;
size = sizeof(struct atl1_buffer) * tpd_ring->count; spin_lock_irqsave(&adapter->lock, flags);
memset(tpd_ring->buffer_info, 0, size); adapter->phy_timer_pending = false;
atl1_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
atl1_write_phy_reg(hw, MII_AT001_CR, hw->mii_1000t_ctrl_reg);
atl1_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN);
spin_unlock_irqrestore(&adapter->lock, flags);
}
/* Zero out the descriptor ring */ /*
memset(tpd_ring->desc, 0, tpd_ring->size); * atl1_tx_timeout - Respond to a Tx Hang
* @netdev: network interface device structure
*/
static void atl1_tx_timeout(struct net_device *netdev)
{
struct atl1_adapter *adapter = netdev_priv(netdev);
/* Do the reset outside of interrupt context */
schedule_work(&adapter->tx_timeout_task);
}
/*
* Orphaned vendor comment left intact here:
* <vendor comment>
* If TPD Buffer size equal to 0, PCIE DMAR_TO_INT
* will assert. We do soft reset <0x1400=1> according
* with the SPEC. BUT, it seemes that PCIE or DMA
* state-machine will not be reset. DMAR_TO_INT will
* assert again and again.
* </vendor comment>
*/
static void atl1_tx_timeout_task(struct work_struct *work)
{
struct atl1_adapter *adapter =
container_of(work, struct atl1_adapter, tx_timeout_task);
struct net_device *netdev = adapter->netdev;
atomic_set(&tpd_ring->next_to_use, 0); netif_device_detach(netdev);
atomic_set(&tpd_ring->next_to_clean, 0); atl1_down(adapter);
atl1_up(adapter);
netif_device_attach(netdev);
} }
/* /*
* atl1_free_ring_resources - Free Tx / RX descriptor Resources * atl1_link_chg_task - deal with link change event Out of interrupt context
* @adapter: board private structure
*
* Free all transmit software resources
*/ */
void atl1_free_ring_resources(struct atl1_adapter *adapter) static void atl1_link_chg_task(struct work_struct *work)
{ {
struct pci_dev *pdev = adapter->pdev; struct atl1_adapter *adapter =
struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring; container_of(work, struct atl1_adapter, link_chg_task);
struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring; unsigned long flags;
struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
struct atl1_ring_header *ring_header = &adapter->ring_header;
atl1_clean_tx_ring(adapter); spin_lock_irqsave(&adapter->lock, flags);
atl1_clean_rx_ring(adapter); atl1_check_link(adapter);
spin_unlock_irqrestore(&adapter->lock, flags);
}
kfree(tpd_ring->buffer_info); static void atl1_vlan_rx_register(struct net_device *netdev,
pci_free_consistent(pdev, ring_header->size, ring_header->desc, struct vlan_group *grp)
ring_header->dma); {
struct atl1_adapter *adapter = netdev_priv(netdev);
unsigned long flags;
u32 ctrl;
tpd_ring->buffer_info = NULL; spin_lock_irqsave(&adapter->lock, flags);
tpd_ring->desc = NULL; /* atl1_irq_disable(adapter); */
tpd_ring->dma = 0; adapter->vlgrp = grp;
rfd_ring->buffer_info = NULL; if (grp) {
rfd_ring->desc = NULL; /* enable VLAN tag insert/strip */
rfd_ring->dma = 0; ctrl = ioread32(adapter->hw.hw_addr + REG_MAC_CTRL);
ctrl |= MAC_CTRL_RMV_VLAN;
iowrite32(ctrl, adapter->hw.hw_addr + REG_MAC_CTRL);
} else {
/* disable VLAN tag insert/strip */
ctrl = ioread32(adapter->hw.hw_addr + REG_MAC_CTRL);
ctrl &= ~MAC_CTRL_RMV_VLAN;
iowrite32(ctrl, adapter->hw.hw_addr + REG_MAC_CTRL);
}
rrd_ring->desc = NULL; /* atl1_irq_enable(adapter); */
rrd_ring->dma = 0; spin_unlock_irqrestore(&adapter->lock, flags);
}
static void atl1_restore_vlan(struct atl1_adapter *adapter)
{
atl1_vlan_rx_register(adapter->netdev, adapter->vlgrp);
}
int atl1_reset(struct atl1_adapter *adapter)
{
int ret;
ret = atl1_reset_hw(&adapter->hw);
if (ret != ATL1_SUCCESS)
return ret;
return atl1_init_hw(&adapter->hw);
} }
s32 atl1_up(struct atl1_adapter *adapter) s32 atl1_up(struct atl1_adapter *adapter)
...@@ -1792,173 +2027,6 @@ void atl1_down(struct atl1_adapter *adapter) ...@@ -1792,173 +2027,6 @@ void atl1_down(struct atl1_adapter *adapter)
atl1_clean_rx_ring(adapter); atl1_clean_rx_ring(adapter);
} }
/*
* atl1_change_mtu - Change the Maximum Transfer Unit
* @netdev: network interface device structure
* @new_mtu: new value for maximum frame size
*
* Returns 0 on success, negative on failure
*/
static int atl1_change_mtu(struct net_device *netdev, int new_mtu)
{
struct atl1_adapter *adapter = netdev_priv(netdev);
int old_mtu = netdev->mtu;
int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
if ((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
(max_frame > MAX_JUMBO_FRAME_SIZE)) {
dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
return -EINVAL;
}
adapter->hw.max_frame_size = max_frame;
adapter->hw.tx_jumbo_task_th = (max_frame + 7) >> 3;
adapter->rx_buffer_len = (max_frame + 7) & ~7;
adapter->hw.rx_jumbo_th = adapter->rx_buffer_len / 8;
netdev->mtu = new_mtu;
if ((old_mtu != new_mtu) && netif_running(netdev)) {
atl1_down(adapter);
atl1_up(adapter);
}
return 0;
}
/*
* atl1_set_mac - Change the Ethernet Address of the NIC
* @netdev: network interface device structure
* @p: pointer to an address structure
*
* Returns 0 on success, negative on failure
*/
static int atl1_set_mac(struct net_device *netdev, void *p)
{
struct atl1_adapter *adapter = netdev_priv(netdev);
struct sockaddr *addr = p;
if (netif_running(netdev))
return -EBUSY;
if (!is_valid_ether_addr(addr->sa_data))
return -EADDRNOTAVAIL;
memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
atl1_set_mac_addr(&adapter->hw);
return 0;
}
/*
* atl1_watchdog - Timer Call-back
* @data: pointer to netdev cast into an unsigned long
*/
static void atl1_watchdog(unsigned long data)
{
struct atl1_adapter *adapter = (struct atl1_adapter *)data;
/* Reset the timer */
mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
}
static int mdio_read(struct net_device *netdev, int phy_id, int reg_num)
{
struct atl1_adapter *adapter = netdev_priv(netdev);
u16 result;
atl1_read_phy_reg(&adapter->hw, reg_num & 0x1f, &result);
return result;
}
static void mdio_write(struct net_device *netdev, int phy_id, int reg_num,
int val)
{
struct atl1_adapter *adapter = netdev_priv(netdev);
atl1_write_phy_reg(&adapter->hw, reg_num, val);
}
/*
* atl1_mii_ioctl -
* @netdev:
* @ifreq:
* @cmd:
*/
static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
{
struct atl1_adapter *adapter = netdev_priv(netdev);
unsigned long flags;
int retval;
if (!netif_running(netdev))
return -EINVAL;
spin_lock_irqsave(&adapter->lock, flags);
retval = generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
spin_unlock_irqrestore(&adapter->lock, flags);
return retval;
}
/*
* atl1_ioctl -
* @netdev:
* @ifreq:
* @cmd:
*/
static int atl1_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
{
switch (cmd) {
case SIOCGMIIPHY:
case SIOCGMIIREG:
case SIOCSMIIREG:
return atl1_mii_ioctl(netdev, ifr, cmd);
default:
return -EOPNOTSUPP;
}
}
/*
* atl1_tx_timeout - Respond to a Tx Hang
* @netdev: network interface device structure
*/
static void atl1_tx_timeout(struct net_device *netdev)
{
struct atl1_adapter *adapter = netdev_priv(netdev);
/* Do the reset outside of interrupt context */
schedule_work(&adapter->tx_timeout_task);
}
/*
* atl1_phy_config - Timer Call-back
* @data: pointer to netdev cast into an unsigned long
*/
static void atl1_phy_config(unsigned long data)
{
struct atl1_adapter *adapter = (struct atl1_adapter *)data;
struct atl1_hw *hw = &adapter->hw;
unsigned long flags;
spin_lock_irqsave(&adapter->lock, flags);
adapter->phy_timer_pending = false;
atl1_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
atl1_write_phy_reg(hw, MII_AT001_CR, hw->mii_1000t_ctrl_reg);
atl1_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN);
spin_unlock_irqrestore(&adapter->lock, flags);
}
int atl1_reset(struct atl1_adapter *adapter)
{
int ret;
ret = atl1_reset_hw(&adapter->hw);
if (ret != ATL1_SUCCESS)
return ret;
return atl1_init_hw(&adapter->hw);
}
/* /*
* atl1_open - Called when a network interface is made active * atl1_open - Called when a network interface is made active
* @netdev: network interface device structure * @netdev: network interface device structure
...@@ -2011,82 +2079,113 @@ static int atl1_close(struct net_device *netdev) ...@@ -2011,82 +2079,113 @@ static int atl1_close(struct net_device *netdev)
return 0; return 0;
} }
#ifdef CONFIG_NET_POLL_CONTROLLER #ifdef CONFIG_PM
static void atl1_poll_controller(struct net_device *netdev) static int atl1_suspend(struct pci_dev *pdev, pm_message_t state)
{
disable_irq(netdev->irq);
atl1_intr(netdev->irq, netdev);
enable_irq(netdev->irq);
}
#endif
/*
* Orphaned vendor comment left intact here:
* <vendor comment>
* If TPD Buffer size equal to 0, PCIE DMAR_TO_INT
* will assert. We do soft reset <0x1400=1> according
* with the SPEC. BUT, it seemes that PCIE or DMA
* state-machine will not be reset. DMAR_TO_INT will
* assert again and again.
* </vendor comment>
*/
static void atl1_tx_timeout_task(struct work_struct *work)
{ {
struct atl1_adapter *adapter = struct net_device *netdev = pci_get_drvdata(pdev);
container_of(work, struct atl1_adapter, tx_timeout_task); struct atl1_adapter *adapter = netdev_priv(netdev);
struct net_device *netdev = adapter->netdev; struct atl1_hw *hw = &adapter->hw;
u32 ctrl = 0;
u32 wufc = adapter->wol;
netif_device_detach(netdev); netif_device_detach(netdev);
atl1_down(adapter); if (netif_running(netdev))
atl1_up(adapter); atl1_down(adapter);
netif_device_attach(netdev);
}
/* atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
* atl1_link_chg_task - deal with link change event Out of interrupt context atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
*/ if (ctrl & BMSR_LSTATUS)
static void atl1_link_chg_task(struct work_struct *work) wufc &= ~ATL1_WUFC_LNKC;
{
struct atl1_adapter *adapter =
container_of(work, struct atl1_adapter, link_chg_task);
unsigned long flags;
spin_lock_irqsave(&adapter->lock, flags); /* reduce speed to 10/100M */
atl1_check_link(adapter); if (wufc) {
spin_unlock_irqrestore(&adapter->lock, flags); atl1_phy_enter_power_saving(hw);
/* if resume, let driver to re- setup link */
hw->phy_configured = false;
atl1_set_mac_addr(hw);
atl1_set_multi(netdev);
ctrl = 0;
/* turn on magic packet wol */
if (wufc & ATL1_WUFC_MAG)
ctrl = WOL_MAGIC_EN | WOL_MAGIC_PME_EN;
/* turn on Link change WOL */
if (wufc & ATL1_WUFC_LNKC)
ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
/* turn on all-multi mode if wake on multicast is enabled */
ctrl = ioread32(hw->hw_addr + REG_MAC_CTRL);
ctrl &= ~MAC_CTRL_DBG;
ctrl &= ~MAC_CTRL_PROMIS_EN;
if (wufc & ATL1_WUFC_MC)
ctrl |= MAC_CTRL_MC_ALL_EN;
else
ctrl &= ~MAC_CTRL_MC_ALL_EN;
/* turn on broadcast mode if wake on-BC is enabled */
if (wufc & ATL1_WUFC_BC)
ctrl |= MAC_CTRL_BC_EN;
else
ctrl &= ~MAC_CTRL_BC_EN;
/* enable RX */
ctrl |= MAC_CTRL_RX_EN;
iowrite32(ctrl, hw->hw_addr + REG_MAC_CTRL);
pci_enable_wake(pdev, PCI_D3hot, 1);
pci_enable_wake(pdev, PCI_D3cold, 1);
} else {
iowrite32(0, hw->hw_addr + REG_WOL_CTRL);
pci_enable_wake(pdev, PCI_D3hot, 0);
pci_enable_wake(pdev, PCI_D3cold, 0);
}
pci_save_state(pdev);
pci_disable_device(pdev);
pci_set_power_state(pdev, PCI_D3hot);
return 0;
} }
/* static int atl1_resume(struct pci_dev *pdev)
* atl1_pcie_patch - Patch for PCIE module
*/
static void atl1_pcie_patch(struct atl1_adapter *adapter)
{ {
u32 value; struct net_device *netdev = pci_get_drvdata(pdev);
struct atl1_adapter *adapter = netdev_priv(netdev);
u32 ret_val;
/* much vendor magic here */ pci_set_power_state(pdev, 0);
value = 0x6500; pci_restore_state(pdev);
iowrite32(value, adapter->hw.hw_addr + 0x12FC);
/* pcie flow control mode change */ ret_val = pci_enable_device(pdev);
value = ioread32(adapter->hw.hw_addr + 0x1008); pci_enable_wake(pdev, PCI_D3hot, 0);
value |= 0x8000; pci_enable_wake(pdev, PCI_D3cold, 0);
iowrite32(value, adapter->hw.hw_addr + 0x1008);
iowrite32(0, adapter->hw.hw_addr + REG_WOL_CTRL);
atl1_reset(adapter);
if (netif_running(netdev))
atl1_up(adapter);
netif_device_attach(netdev);
atl1_via_workaround(adapter);
return 0;
} }
#else
#define atl1_suspend NULL
#define atl1_resume NULL
#endif
/* #ifdef CONFIG_NET_POLL_CONTROLLER
* When ACPI resume on some VIA MotherBoard, the Interrupt Disable bit/0x400 static void atl1_poll_controller(struct net_device *netdev)
* on PCI Command register is disable.
* The function enable this bit.
* Brackett, 2006/03/15
*/
static void atl1_via_workaround(struct atl1_adapter *adapter)
{ {
unsigned long value; disable_irq(netdev->irq);
atl1_intr(netdev->irq, netdev);
value = ioread16(adapter->hw.hw_addr + PCI_COMMAND); enable_irq(netdev->irq);
if (value & PCI_COMMAND_INTX_DISABLE)
value &= ~PCI_COMMAND_INTX_DISABLE;
iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND);
} }
#endif
/* /*
* atl1_probe - Device Initialization Routine * atl1_probe - Device Initialization Routine
...@@ -2320,105 +2419,6 @@ static void __devexit atl1_remove(struct pci_dev *pdev) ...@@ -2320,105 +2419,6 @@ static void __devexit atl1_remove(struct pci_dev *pdev)
pci_disable_device(pdev); pci_disable_device(pdev);
} }
#ifdef CONFIG_PM
static int atl1_suspend(struct pci_dev *pdev, pm_message_t state)
{
struct net_device *netdev = pci_get_drvdata(pdev);
struct atl1_adapter *adapter = netdev_priv(netdev);
struct atl1_hw *hw = &adapter->hw;
u32 ctrl = 0;
u32 wufc = adapter->wol;
netif_device_detach(netdev);
if (netif_running(netdev))
atl1_down(adapter);
atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
if (ctrl & BMSR_LSTATUS)
wufc &= ~ATL1_WUFC_LNKC;
/* reduce speed to 10/100M */
if (wufc) {
atl1_phy_enter_power_saving(hw);
/* if resume, let driver to re- setup link */
hw->phy_configured = false;
atl1_set_mac_addr(hw);
atl1_set_multi(netdev);
ctrl = 0;
/* turn on magic packet wol */
if (wufc & ATL1_WUFC_MAG)
ctrl = WOL_MAGIC_EN | WOL_MAGIC_PME_EN;
/* turn on Link change WOL */
if (wufc & ATL1_WUFC_LNKC)
ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
/* turn on all-multi mode if wake on multicast is enabled */
ctrl = ioread32(hw->hw_addr + REG_MAC_CTRL);
ctrl &= ~MAC_CTRL_DBG;
ctrl &= ~MAC_CTRL_PROMIS_EN;
if (wufc & ATL1_WUFC_MC)
ctrl |= MAC_CTRL_MC_ALL_EN;
else
ctrl &= ~MAC_CTRL_MC_ALL_EN;
/* turn on broadcast mode if wake on-BC is enabled */
if (wufc & ATL1_WUFC_BC)
ctrl |= MAC_CTRL_BC_EN;
else
ctrl &= ~MAC_CTRL_BC_EN;
/* enable RX */
ctrl |= MAC_CTRL_RX_EN;
iowrite32(ctrl, hw->hw_addr + REG_MAC_CTRL);
pci_enable_wake(pdev, PCI_D3hot, 1);
pci_enable_wake(pdev, PCI_D3cold, 1);
} else {
iowrite32(0, hw->hw_addr + REG_WOL_CTRL);
pci_enable_wake(pdev, PCI_D3hot, 0);
pci_enable_wake(pdev, PCI_D3cold, 0);
}
pci_save_state(pdev);
pci_disable_device(pdev);
pci_set_power_state(pdev, PCI_D3hot);
return 0;
}
static int atl1_resume(struct pci_dev *pdev)
{
struct net_device *netdev = pci_get_drvdata(pdev);
struct atl1_adapter *adapter = netdev_priv(netdev);
u32 ret_val;
pci_set_power_state(pdev, 0);
pci_restore_state(pdev);
ret_val = pci_enable_device(pdev);
pci_enable_wake(pdev, PCI_D3hot, 0);
pci_enable_wake(pdev, PCI_D3cold, 0);
iowrite32(0, adapter->hw.hw_addr + REG_WOL_CTRL);
atl1_reset(adapter);
if (netif_running(netdev))
atl1_up(adapter);
netif_device_attach(netdev);
atl1_via_workaround(adapter);
return 0;
}
#else
#define atl1_suspend NULL
#define atl1_resume NULL
#endif
static struct pci_driver atl1_driver = { static struct pci_driver atl1_driver = {
.name = atl1_driver_name, .name = atl1_driver_name,
.id_table = atl1_pci_tbl, .id_table = atl1_pci_tbl,
......
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