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Commit 064a6a88 authored by Andrew Lunn's avatar Andrew Lunn Committed by Jakub Kicinski
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net: nixge: Separate C22 and C45 transactions 

The nixge MDIO bus driver can perform both C22 and C45 transfers.
Create separate functions for each and register the C45 versions using
the new API calls where appropriate.
Signed-off-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarMichael Walle <michael@walle.cc>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent e078c8b5
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Showing with 85 additions and 56 deletions
drivers/net/ethernet/ni/nixge.c
View file @ 064a6a88
...@@ -1081,40 +1081,59 @@ static const struct ethtool_ops nixge_ethtool_ops = { ...@@ -1081,40 +1081,59 @@ static const struct ethtool_ops nixge_ethtool_ops = {
.get_link = ethtool_op_get_link, .get_link = ethtool_op_get_link,
}; };
static int nixge_mdio_read(struct mii_bus *bus, int phy_id, int reg) static int nixge_mdio_read_c22(struct mii_bus *bus, int phy_id, int reg)
{ {
struct nixge_priv *priv = bus->priv; struct nixge_priv *priv = bus->priv;
u32 status, tmp; u32 status, tmp;
int err; int err;
u16 device; u16 device;
if (reg & MII_ADDR_C45) { device = reg & 0x1f;
device = (reg >> 16) & 0x1f;
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_ADDR, reg & 0xffff); tmp = NIXGE_MDIO_CLAUSE22 | NIXGE_MDIO_OP(NIXGE_MDIO_C22_READ) |
NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_OP_ADDRESS) nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
| NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device); nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp); err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1); !status, 10, 1000);
if (err) {
dev_err(priv->dev, "timeout setting read command");
return err;
}
err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status, status = nixge_ctrl_read_reg(priv, NIXGE_REG_MDIO_DATA);
!status, 10, 1000);
if (err) {
dev_err(priv->dev, "timeout setting address");
return err;
}
tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_C45_READ) | return status;
NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device); }
} else {
device = reg & 0x1f;
tmp = NIXGE_MDIO_CLAUSE22 | NIXGE_MDIO_OP(NIXGE_MDIO_C22_READ) | static int nixge_mdio_read_c45(struct mii_bus *bus, int phy_id, int device,
NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device); int reg)
{
struct nixge_priv *priv = bus->priv;
u32 status, tmp;
int err;
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_ADDR, reg & 0xffff);
tmp = NIXGE_MDIO_CLAUSE45 |
NIXGE_MDIO_OP(NIXGE_MDIO_OP_ADDRESS) |
NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
!status, 10, 1000);
if (err) {
dev_err(priv->dev, "timeout setting address");
return err;
} }
tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_C45_READ) |
NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp); nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1); nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
...@@ -1130,57 +1149,65 @@ static int nixge_mdio_read(struct mii_bus *bus, int phy_id, int reg) ...@@ -1130,57 +1149,65 @@ static int nixge_mdio_read(struct mii_bus *bus, int phy_id, int reg)
return status; return status;
} }
static int nixge_mdio_write(struct mii_bus *bus, int phy_id, int reg, u16 val) static int nixge_mdio_write_c22(struct mii_bus *bus, int phy_id, int reg,
u16 val)
{ {
struct nixge_priv *priv = bus->priv; struct nixge_priv *priv = bus->priv;
u32 status, tmp; u32 status, tmp;
u16 device; u16 device;
int err; int err;
if (reg & MII_ADDR_C45) { device = reg & 0x1f;
device = (reg >> 16) & 0x1f;
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_ADDR, reg & 0xffff); tmp = NIXGE_MDIO_CLAUSE22 | NIXGE_MDIO_OP(NIXGE_MDIO_C22_WRITE) |
NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_OP_ADDRESS) nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_DATA, val);
| NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device); nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp); err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1); !status, 10, 1000);
if (err)
dev_err(priv->dev, "timeout setting write command");
err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status, return err;
!status, 10, 1000); }
if (err) {
dev_err(priv->dev, "timeout setting address");
return err;
}
tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_C45_WRITE) static int nixge_mdio_write_c45(struct mii_bus *bus, int phy_id,
| NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device); int device, int reg, u16 val)
{
struct nixge_priv *priv = bus->priv;
u32 status, tmp;
int err;
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_DATA, val); nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_ADDR, reg & 0xffff);
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
!status, 10, 1000);
if (err)
dev_err(priv->dev, "timeout setting write command");
} else {
device = reg & 0x1f;
tmp = NIXGE_MDIO_CLAUSE22 | tmp = NIXGE_MDIO_CLAUSE45 |
NIXGE_MDIO_OP(NIXGE_MDIO_C22_WRITE) | NIXGE_MDIO_OP(NIXGE_MDIO_OP_ADDRESS) |
NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device); NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_DATA, val); nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp); nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status, err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
!status, 10, 1000); !status, 10, 1000);
if (err) if (err) {
dev_err(priv->dev, "timeout setting write command"); dev_err(priv->dev, "timeout setting address");
return err;
} }
tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_C45_WRITE) |
NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_DATA, val);
nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
!status, 10, 1000);
if (err)
dev_err(priv->dev, "timeout setting write command");
return err; return err;
} }
...@@ -1195,8 +1222,10 @@ static int nixge_mdio_setup(struct nixge_priv *priv, struct device_node *np) ...@@ -1195,8 +1222,10 @@ static int nixge_mdio_setup(struct nixge_priv *priv, struct device_node *np)
snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(priv->dev)); snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(priv->dev));
bus->priv = priv; bus->priv = priv;
bus->name = "nixge_mii_bus"; bus->name = "nixge_mii_bus";
bus->read = nixge_mdio_read; bus->read = nixge_mdio_read_c22;
bus->write = nixge_mdio_write; bus->write = nixge_mdio_write_c22;
bus->read_c45 = nixge_mdio_read_c45;
bus->write_c45 = nixge_mdio_write_c45;
bus->parent = priv->dev; bus->parent = priv->dev;
priv->mii_bus = bus; priv->mii_bus = bus;
......
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