Commit 08c8833b authored by Alexander Duyck's avatar Alexander Duyck Committed by Jeff Kirsher

ixgbe: add structure for containing RX/TX rings to q_vector

This patch adds support for a ring container structure to be used within
the q_vector.  The basic idea is to provide a means of separating the RX
and TX rings while maintaining a common structure for their containment.
The advantage to this is that later we should be able to pass this
structure to the update_itr functions without needing to pass individual
rings.
Signed-off-by: default avatarAlexander Duyck <alexander.h.duyck@intel.com>
Tested-by: default avatarRoss Brattain <ross.b.brattain@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 82d4e46e
...@@ -277,6 +277,15 @@ struct ixgbe_ring_feature { ...@@ -277,6 +277,15 @@ struct ixgbe_ring_feature {
int mask; int mask;
} ____cacheline_internodealigned_in_smp; } ____cacheline_internodealigned_in_smp;
struct ixgbe_ring_container {
#if MAX_RX_QUEUES > MAX_TX_QUEUES
DECLARE_BITMAP(idx, MAX_RX_QUEUES);
#else
DECLARE_BITMAP(idx, MAX_TX_QUEUES);
#endif
u8 count; /* total number of rings in vector */
u8 itr; /* current ITR setting for ring */
};
#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
? 8 : 1) ? 8 : 1)
...@@ -294,12 +303,7 @@ struct ixgbe_q_vector { ...@@ -294,12 +303,7 @@ struct ixgbe_q_vector {
int cpu; /* CPU for DCA */ int cpu; /* CPU for DCA */
#endif #endif
struct napi_struct napi; struct napi_struct napi;
DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */ struct ixgbe_ring_container rx, tx;
DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
u8 rxr_count; /* Rx ring count assigned to this vector */
u8 txr_count; /* Tx ring count assigned to this vector */
u8 tx_itr;
u8 rx_itr;
u32 eitr; u32 eitr;
cpumask_var_t affinity_mask; cpumask_var_t affinity_mask;
char name[IFNAMSIZ + 9]; char name[IFNAMSIZ + 9];
......
...@@ -2122,7 +2122,7 @@ static int ixgbe_get_coalesce(struct net_device *netdev, ...@@ -2122,7 +2122,7 @@ static int ixgbe_get_coalesce(struct net_device *netdev,
} }
/* if in mixed tx/rx queues per vector mode, report only rx settings */ /* if in mixed tx/rx queues per vector mode, report only rx settings */
if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count) if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
return 0; return 0;
/* only valid if in constant ITR mode */ /* only valid if in constant ITR mode */
...@@ -2187,7 +2187,7 @@ static int ixgbe_set_coalesce(struct net_device *netdev, ...@@ -2187,7 +2187,7 @@ static int ixgbe_set_coalesce(struct net_device *netdev,
bool need_reset = false; bool need_reset = false;
/* don't accept tx specific changes if we've got mixed RxTx vectors */ /* don't accept tx specific changes if we've got mixed RxTx vectors */
if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count
&& ec->tx_coalesce_usecs) && ec->tx_coalesce_usecs)
return -EINVAL; return -EINVAL;
...@@ -2261,7 +2261,7 @@ static int ixgbe_set_coalesce(struct net_device *netdev, ...@@ -2261,7 +2261,7 @@ static int ixgbe_set_coalesce(struct net_device *netdev,
int num_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; int num_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
for (i = 0; i < num_vectors; i++) { for (i = 0; i < num_vectors; i++) {
q_vector = adapter->q_vector[i]; q_vector = adapter->q_vector[i];
if (q_vector->txr_count && !q_vector->rxr_count) if (q_vector->tx.count && !q_vector->rx.count)
/* tx only */ /* tx only */
q_vector->eitr = adapter->tx_eitr_param; q_vector->eitr = adapter->tx_eitr_param;
else else
......
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