Commit 08f41f7c authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'armsoc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
 "The latest and greatest fixes for ARM platform code.  Worth pointing
  out are:

   - Lines-wise, largest is a PXA fix for dealing with interrupts on DT
     that was quite broken.  It's still newish code so while we could
     have held this off, it seemed appropriate to include now

   - Some GPIO fixes for OMAP platforms added a few lines.  This was
     also fixes for code recently added (this release).

   - Small OMAP timer fix to behave better with partially upstreamed
     platforms, which is quite welcome.

   - Allwinner fixes about operating point control, reducing
     overclocking in some cases for better stability.

  plus a handful of other smaller fixes across the map"

* tag 'armsoc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  arm64: juno: Fix misleading name of UART reference clock
  ARM: dts: sunxi: Remove overclocked/overvoltaged OPP
  ARM: dts: sun4i: a10-lime: Override and remove 1008MHz OPP setting
  ARM: socfpga: dts: fix spi1 interrupt
  ARM: dts: Fix gpio interrupts for dm816x
  ARM: dts: dra7: remove ti,hwmod property from pcie phy
  ARM: OMAP: dmtimer: disable pm runtime on remove
  ARM: OMAP: dmtimer: check for pm_runtime_get_sync() failure
  ARM: OMAP2+: Fix socbus family info for AM33xx devices
  ARM: dts: omap3: Add missing dmas for crypto
  ARM: dts: rockchip: disable gmac by default in rk3288.dtsi
  MAINTAINERS: add rockchip regexp to the ARM/Rockchip entry
  ARM: pxa: fix pxa interrupts handling in DT
  ARM: pxa: Fix typo in zeus.c
  ARM: sunxi: Have ARCH_SUNXI select RESET_CONTROLLER for clock driver usage
parents 7fc377ec 4550bdb0
...@@ -1362,6 +1362,7 @@ F: drivers/i2c/busses/i2c-rk3x.c ...@@ -1362,6 +1362,7 @@ F: drivers/i2c/busses/i2c-rk3x.c
F: drivers/*/*rockchip* F: drivers/*/*rockchip*
F: drivers/*/*/*rockchip* F: drivers/*/*/*rockchip*
F: sound/soc/rockchip/ F: sound/soc/rockchip/
N: rockchip
ARM/SAMSUNG EXYNOS ARM ARCHITECTURES ARM/SAMSUNG EXYNOS ARM ARCHITECTURES
M: Kukjin Kim <kgene@kernel.org> M: Kukjin Kim <kgene@kernel.org>
......
...@@ -619,6 +619,7 @@ config ARCH_PXA ...@@ -619,6 +619,7 @@ config ARCH_PXA
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select GPIO_PXA select GPIO_PXA
select HAVE_IDE select HAVE_IDE
select IRQ_DOMAIN
select MULTI_IRQ_HANDLER select MULTI_IRQ_HANDLER
select PLAT_PXA select PLAT_PXA
select SPARSE_IRQ select SPARSE_IRQ
......
...@@ -36,6 +36,20 @@ DM816X_IOPAD(0x0aac, PIN_INPUT | MUX_MODE0) /* SPI_D1 */ ...@@ -36,6 +36,20 @@ DM816X_IOPAD(0x0aac, PIN_INPUT | MUX_MODE0) /* SPI_D1 */
>; >;
}; };
mmc_pins: pinmux_mmc_pins {
pinctrl-single,pins = <
DM816X_IOPAD(0x0a70, MUX_MODE0) /* SD_POW */
DM816X_IOPAD(0x0a74, MUX_MODE0) /* SD_CLK */
DM816X_IOPAD(0x0a78, MUX_MODE0) /* SD_CMD */
DM816X_IOPAD(0x0a7C, MUX_MODE0) /* SD_DAT0 */
DM816X_IOPAD(0x0a80, MUX_MODE0) /* SD_DAT1 */
DM816X_IOPAD(0x0a84, MUX_MODE0) /* SD_DAT2 */
DM816X_IOPAD(0x0a88, MUX_MODE0) /* SD_DAT2 */
DM816X_IOPAD(0x0a8c, MUX_MODE2) /* GP1[7] */
DM816X_IOPAD(0x0a90, MUX_MODE2) /* GP1[8] */
>;
};
usb0_pins: pinmux_usb0_pins { usb0_pins: pinmux_usb0_pins {
pinctrl-single,pins = < pinctrl-single,pins = <
DM816X_IOPAD(0x0d00, MUX_MODE0) /* USB0_DRVVBUS */ DM816X_IOPAD(0x0d00, MUX_MODE0) /* USB0_DRVVBUS */
...@@ -137,7 +151,12 @@ m25p80@0 { ...@@ -137,7 +151,12 @@ m25p80@0 {
}; };
&mmc1 { &mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc_pins>;
vmmc-supply = <&vmmcsd_fixed>; vmmc-supply = <&vmmcsd_fixed>;
bus-width = <4>;
cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
}; };
/* At least dm8168-evm rev c won't support multipoint, later may */ /* At least dm8168-evm rev c won't support multipoint, later may */
......
...@@ -150,17 +150,27 @@ elm: elm@48080000 { ...@@ -150,17 +150,27 @@ elm: elm@48080000 {
}; };
gpio1: gpio@48032000 { gpio1: gpio@48032000 {
compatible = "ti,omap3-gpio"; compatible = "ti,omap4-gpio";
ti,hwmods = "gpio1"; ti,hwmods = "gpio1";
ti,gpio-always-on;
reg = <0x48032000 0x1000>; reg = <0x48032000 0x1000>;
interrupts = <97>; interrupts = <96>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
}; };
gpio2: gpio@4804c000 { gpio2: gpio@4804c000 {
compatible = "ti,omap3-gpio"; compatible = "ti,omap4-gpio";
ti,hwmods = "gpio2"; ti,hwmods = "gpio2";
ti,gpio-always-on;
reg = <0x4804c000 0x1000>; reg = <0x4804c000 0x1000>;
interrupts = <99>; interrupts = <98>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
}; };
gpmc: gpmc@50000000 { gpmc: gpmc@50000000 {
......
...@@ -1111,7 +1111,6 @@ pcie1_phy: pciephy@4a094000 { ...@@ -1111,7 +1111,6 @@ pcie1_phy: pciephy@4a094000 {
"wkupclk", "refclk", "wkupclk", "refclk",
"div-clk", "phy-div"; "div-clk", "phy-div";
#phy-cells = <0>; #phy-cells = <0>;
ti,hwmods = "pcie1-phy";
}; };
pcie2_phy: pciephy@4a095000 { pcie2_phy: pciephy@4a095000 {
...@@ -1130,7 +1129,6 @@ pcie2_phy: pciephy@4a095000 { ...@@ -1130,7 +1129,6 @@ pcie2_phy: pciephy@4a095000 {
"wkupclk", "refclk", "wkupclk", "refclk",
"div-clk", "phy-div"; "div-clk", "phy-div";
#phy-cells = <0>; #phy-cells = <0>;
ti,hwmods = "pcie2-phy";
status = "disabled"; status = "disabled";
}; };
}; };
......
...@@ -92,6 +92,8 @@ aes: aes@480c5000 { ...@@ -92,6 +92,8 @@ aes: aes@480c5000 {
ti,hwmods = "aes"; ti,hwmods = "aes";
reg = <0x480c5000 0x50>; reg = <0x480c5000 0x50>;
interrupts = <0>; interrupts = <0>;
dmas = <&sdma 65 &sdma 66>;
dma-names = "tx", "rx";
}; };
prm: prm@48306000 { prm: prm@48306000 {
...@@ -550,6 +552,8 @@ sham: sham@480c3000 { ...@@ -550,6 +552,8 @@ sham: sham@480c3000 {
ti,hwmods = "sham"; ti,hwmods = "sham";
reg = <0x480c3000 0x64>; reg = <0x480c3000 0x64>;
interrupts = <49>; interrupts = <49>;
dmas = <&sdma 69>;
dma-names = "rx";
}; };
smartreflex_core: smartreflex@480cb000 { smartreflex_core: smartreflex@480cb000 {
......
...@@ -411,6 +411,7 @@ gmac: ethernet@ff290000 { ...@@ -411,6 +411,7 @@ gmac: ethernet@ff290000 {
"mac_clk_rx", "mac_clk_tx", "mac_clk_rx", "mac_clk_tx",
"clk_mac_ref", "clk_mac_refout", "clk_mac_ref", "clk_mac_refout",
"aclk_mac", "pclk_mac"; "aclk_mac", "pclk_mac";
status = "disabled";
}; };
usb_host0_ehci: usb@ff500000 { usb_host0_ehci: usb@ff500000 {
......
...@@ -660,7 +660,7 @@ spi1: spi@fff01000 { ...@@ -660,7 +660,7 @@ spi1: spi@fff01000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <0xfff01000 0x1000>; reg = <0xfff01000 0x1000>;
interrupts = <0 156 4>; interrupts = <0 155 4>;
num-cs = <4>; num-cs = <4>;
clocks = <&spi_m_clk>; clocks = <&spi_m_clk>;
status = "disabled"; status = "disabled";
......
...@@ -56,6 +56,22 @@ / { ...@@ -56,6 +56,22 @@ / {
model = "Olimex A10-OLinuXino-LIME"; model = "Olimex A10-OLinuXino-LIME";
compatible = "olimex,a10-olinuxino-lime", "allwinner,sun4i-a10"; compatible = "olimex,a10-olinuxino-lime", "allwinner,sun4i-a10";
cpus {
cpu0: cpu@0 {
/*
* The A10-Lime is known to be unstable
* when running at 1008 MHz
*/
operating-points = <
/* kHz uV */
912000 1350000
864000 1300000
624000 1250000
>;
cooling-max-level = <2>;
};
};
soc@01c00000 { soc@01c00000 {
emac: ethernet@01c0b000 { emac: ethernet@01c0b000 {
pinctrl-names = "default"; pinctrl-names = "default";
......
...@@ -75,7 +75,6 @@ cpu0: cpu@0 { ...@@ -75,7 +75,6 @@ cpu0: cpu@0 {
clock-latency = <244144>; /* 8 32k periods */ clock-latency = <244144>; /* 8 32k periods */
operating-points = < operating-points = <
/* kHz uV */ /* kHz uV */
1056000 1500000
1008000 1400000 1008000 1400000
912000 1350000 912000 1350000
864000 1300000 864000 1300000
...@@ -83,7 +82,7 @@ cpu0: cpu@0 { ...@@ -83,7 +82,7 @@ cpu0: cpu@0 {
>; >;
#cooling-cells = <2>; #cooling-cells = <2>;
cooling-min-level = <0>; cooling-min-level = <0>;
cooling-max-level = <4>; cooling-max-level = <3>;
}; };
}; };
......
...@@ -47,7 +47,6 @@ cpu0: cpu@0 { ...@@ -47,7 +47,6 @@ cpu0: cpu@0 {
clock-latency = <244144>; /* 8 32k periods */ clock-latency = <244144>; /* 8 32k periods */
operating-points = < operating-points = <
/* kHz uV */ /* kHz uV */
1104000 1500000
1008000 1400000 1008000 1400000
912000 1350000 912000 1350000
864000 1300000 864000 1300000
...@@ -57,7 +56,7 @@ cpu0: cpu@0 { ...@@ -57,7 +56,7 @@ cpu0: cpu@0 {
>; >;
#cooling-cells = <2>; #cooling-cells = <2>;
cooling-min-level = <0>; cooling-min-level = <0>;
cooling-max-level = <6>; cooling-max-level = <5>;
}; };
}; };
......
...@@ -105,7 +105,6 @@ cpu0: cpu@0 { ...@@ -105,7 +105,6 @@ cpu0: cpu@0 {
clock-latency = <244144>; /* 8 32k periods */ clock-latency = <244144>; /* 8 32k periods */
operating-points = < operating-points = <
/* kHz uV */ /* kHz uV */
1008000 1450000
960000 1400000 960000 1400000
912000 1400000 912000 1400000
864000 1300000 864000 1300000
...@@ -116,7 +115,7 @@ cpu0: cpu@0 { ...@@ -116,7 +115,7 @@ cpu0: cpu@0 {
>; >;
#cooling-cells = <2>; #cooling-cells = <2>;
cooling-min-level = <0>; cooling-min-level = <0>;
cooling-max-level = <7>; cooling-max-level = <6>;
}; };
cpu@1 { cpu@1 {
......
...@@ -720,6 +720,8 @@ static const char * __init omap_get_family(void) ...@@ -720,6 +720,8 @@ static const char * __init omap_get_family(void)
return kasprintf(GFP_KERNEL, "OMAP4"); return kasprintf(GFP_KERNEL, "OMAP4");
else if (soc_is_omap54xx()) else if (soc_is_omap54xx())
return kasprintf(GFP_KERNEL, "OMAP5"); return kasprintf(GFP_KERNEL, "OMAP5");
else if (soc_is_am33xx() || soc_is_am335x())
return kasprintf(GFP_KERNEL, "AM33xx");
else if (soc_is_am43xx()) else if (soc_is_am43xx())
return kasprintf(GFP_KERNEL, "AM43xx"); return kasprintf(GFP_KERNEL, "AM43xx");
else if (soc_is_dra7xx()) else if (soc_is_dra7xx())
......
...@@ -11,6 +11,7 @@ ...@@ -11,6 +11,7 @@
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation. * published by the Free Software Foundation.
*/ */
#include <linux/bitops.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
...@@ -40,7 +41,6 @@ ...@@ -40,7 +41,6 @@
#define ICHP_VAL_IRQ (1 << 31) #define ICHP_VAL_IRQ (1 << 31)
#define ICHP_IRQ(i) (((i) >> 16) & 0x7fff) #define ICHP_IRQ(i) (((i) >> 16) & 0x7fff)
#define IPR_VALID (1 << 31) #define IPR_VALID (1 << 31)
#define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f)
#define MAX_INTERNAL_IRQS 128 #define MAX_INTERNAL_IRQS 128
...@@ -51,6 +51,7 @@ ...@@ -51,6 +51,7 @@
static void __iomem *pxa_irq_base; static void __iomem *pxa_irq_base;
static int pxa_internal_irq_nr; static int pxa_internal_irq_nr;
static bool cpu_has_ipr; static bool cpu_has_ipr;
static struct irq_domain *pxa_irq_domain;
static inline void __iomem *irq_base(int i) static inline void __iomem *irq_base(int i)
{ {
...@@ -66,18 +67,20 @@ static inline void __iomem *irq_base(int i) ...@@ -66,18 +67,20 @@ static inline void __iomem *irq_base(int i)
void pxa_mask_irq(struct irq_data *d) void pxa_mask_irq(struct irq_data *d)
{ {
void __iomem *base = irq_data_get_irq_chip_data(d); void __iomem *base = irq_data_get_irq_chip_data(d);
irq_hw_number_t irq = irqd_to_hwirq(d);
uint32_t icmr = __raw_readl(base + ICMR); uint32_t icmr = __raw_readl(base + ICMR);
icmr &= ~(1 << IRQ_BIT(d->irq)); icmr &= ~BIT(irq & 0x1f);
__raw_writel(icmr, base + ICMR); __raw_writel(icmr, base + ICMR);
} }
void pxa_unmask_irq(struct irq_data *d) void pxa_unmask_irq(struct irq_data *d)
{ {
void __iomem *base = irq_data_get_irq_chip_data(d); void __iomem *base = irq_data_get_irq_chip_data(d);
irq_hw_number_t irq = irqd_to_hwirq(d);
uint32_t icmr = __raw_readl(base + ICMR); uint32_t icmr = __raw_readl(base + ICMR);
icmr |= 1 << IRQ_BIT(d->irq); icmr |= BIT(irq & 0x1f);
__raw_writel(icmr, base + ICMR); __raw_writel(icmr, base + ICMR);
} }
...@@ -118,40 +121,63 @@ asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs) ...@@ -118,40 +121,63 @@ asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs)
} while (1); } while (1);
} }
void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int)) static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{ {
int irq, i, n; void __iomem *base = irq_base(hw / 32);
BUG_ON(irq_nr > MAX_INTERNAL_IRQS); /* initialize interrupt priority */
if (cpu_has_ipr)
__raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw));
irq_set_chip_and_handler(virq, &pxa_internal_irq_chip,
handle_level_irq);
irq_set_chip_data(virq, base);
set_irq_flags(virq, IRQF_VALID);
return 0;
}
static struct irq_domain_ops pxa_irq_ops = {
.map = pxa_irq_map,
.xlate = irq_domain_xlate_onecell,
};
static __init void
pxa_init_irq_common(struct device_node *node, int irq_nr,
int (*fn)(struct irq_data *, unsigned int))
{
int n;
pxa_internal_irq_nr = irq_nr; pxa_internal_irq_nr = irq_nr;
cpu_has_ipr = !cpu_is_pxa25x(); pxa_irq_domain = irq_domain_add_legacy(node, irq_nr,
pxa_irq_base = io_p2v(0x40d00000); PXA_IRQ(0), 0,
&pxa_irq_ops, NULL);
if (!pxa_irq_domain)
panic("Unable to add PXA IRQ domain\n");
irq_set_default_host(pxa_irq_domain);
for (n = 0; n < irq_nr; n += 32) { for (n = 0; n < irq_nr; n += 32) {
void __iomem *base = irq_base(n >> 5); void __iomem *base = irq_base(n >> 5);
__raw_writel(0, base + ICMR); /* disable all IRQs */ __raw_writel(0, base + ICMR); /* disable all IRQs */
__raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */
for (i = n; (i < (n + 32)) && (i < irq_nr); i++) {
/* initialize interrupt priority */
if (cpu_has_ipr)
__raw_writel(i | IPR_VALID, pxa_irq_base + IPR(i));
irq = PXA_IRQ(i);
irq_set_chip_and_handler(irq, &pxa_internal_irq_chip,
handle_level_irq);
irq_set_chip_data(irq, base);
set_irq_flags(irq, IRQF_VALID);
}
} }
/* only unmasked interrupts kick us out of idle */ /* only unmasked interrupts kick us out of idle */
__raw_writel(1, irq_base(0) + ICCR); __raw_writel(1, irq_base(0) + ICCR);
pxa_internal_irq_chip.irq_set_wake = fn; pxa_internal_irq_chip.irq_set_wake = fn;
} }
void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))
{
BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
pxa_irq_base = io_p2v(0x40d00000);
cpu_has_ipr = !cpu_is_pxa25x();
pxa_init_irq_common(NULL, irq_nr, fn);
}
#ifdef CONFIG_PM #ifdef CONFIG_PM
static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32]; static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32];
static unsigned long saved_ipr[MAX_INTERNAL_IRQS]; static unsigned long saved_ipr[MAX_INTERNAL_IRQS];
...@@ -203,30 +229,6 @@ struct syscore_ops pxa_irq_syscore_ops = { ...@@ -203,30 +229,6 @@ struct syscore_ops pxa_irq_syscore_ops = {
}; };
#ifdef CONFIG_OF #ifdef CONFIG_OF
static struct irq_domain *pxa_irq_domain;
static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
void __iomem *base = irq_base(hw / 32);
/* initialize interrupt priority */
if (cpu_has_ipr)
__raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw));
irq_set_chip_and_handler(hw, &pxa_internal_irq_chip,
handle_level_irq);
irq_set_chip_data(hw, base);
set_irq_flags(hw, IRQF_VALID);
return 0;
}
static struct irq_domain_ops pxa_irq_ops = {
.map = pxa_irq_map,
.xlate = irq_domain_xlate_onecell,
};
static const struct of_device_id intc_ids[] __initconst = { static const struct of_device_id intc_ids[] __initconst = {
{ .compatible = "marvell,pxa-intc", }, { .compatible = "marvell,pxa-intc", },
{} {}
...@@ -236,7 +238,7 @@ void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int)) ...@@ -236,7 +238,7 @@ void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int))
{ {
struct device_node *node; struct device_node *node;
struct resource res; struct resource res;
int n, ret; int ret;
node = of_find_matching_node(NULL, intc_ids); node = of_find_matching_node(NULL, intc_ids);
if (!node) { if (!node) {
...@@ -267,23 +269,6 @@ void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int)) ...@@ -267,23 +269,6 @@ void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int))
return; return;
} }
pxa_irq_domain = irq_domain_add_legacy(node, pxa_internal_irq_nr, 0, 0, pxa_init_irq_common(node, pxa_internal_irq_nr, fn);
&pxa_irq_ops, NULL);
if (!pxa_irq_domain)
panic("Unable to add PXA IRQ domain\n");
irq_set_default_host(pxa_irq_domain);
for (n = 0; n < pxa_internal_irq_nr; n += 32) {
void __iomem *base = irq_base(n >> 5);
__raw_writel(0, base + ICMR); /* disable all IRQs */
__raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */
}
/* only unmasked interrupts kick us out of idle */
__raw_writel(1, irq_base(0) + ICCR);
pxa_internal_irq_chip.irq_set_wake = fn;
} }
#endif /* CONFIG_OF */ #endif /* CONFIG_OF */
...@@ -412,7 +412,7 @@ static struct fixed_voltage_config can_regulator_pdata = { ...@@ -412,7 +412,7 @@ static struct fixed_voltage_config can_regulator_pdata = {
}; };
static struct platform_device can_regulator_device = { static struct platform_device can_regulator_device = {
.name = "reg-fixed-volage", .name = "reg-fixed-voltage",
.id = 0, .id = 0,
.dev = { .dev = {
.platform_data = &can_regulator_pdata, .platform_data = &can_regulator_pdata,
......
menuconfig ARCH_SUNXI menuconfig ARCH_SUNXI
bool "Allwinner SoCs" if ARCH_MULTI_V7 bool "Allwinner SoCs" if ARCH_MULTI_V7
select ARCH_REQUIRE_GPIOLIB select ARCH_REQUIRE_GPIOLIB
select ARCH_HAS_RESET_CONTROLLER
select CLKSRC_MMIO select CLKSRC_MMIO
select GENERIC_IRQ_CHIP select GENERIC_IRQ_CHIP
select PINCTRL select PINCTRL
select SUN4I_TIMER select SUN4I_TIMER
select RESET_CONTROLLER
if ARCH_SUNXI if ARCH_SUNXI
...@@ -20,10 +22,8 @@ config MACH_SUN5I ...@@ -20,10 +22,8 @@ config MACH_SUN5I
config MACH_SUN6I config MACH_SUN6I
bool "Allwinner A31 (sun6i) SoCs support" bool "Allwinner A31 (sun6i) SoCs support"
default ARCH_SUNXI default ARCH_SUNXI
select ARCH_HAS_RESET_CONTROLLER
select ARM_GIC select ARM_GIC
select MFD_SUN6I_PRCM select MFD_SUN6I_PRCM
select RESET_CONTROLLER
select SUN5I_HSTIMER select SUN5I_HSTIMER
config MACH_SUN7I config MACH_SUN7I
...@@ -37,16 +37,12 @@ config MACH_SUN7I ...@@ -37,16 +37,12 @@ config MACH_SUN7I
config MACH_SUN8I config MACH_SUN8I
bool "Allwinner A23 (sun8i) SoCs support" bool "Allwinner A23 (sun8i) SoCs support"
default ARCH_SUNXI default ARCH_SUNXI
select ARCH_HAS_RESET_CONTROLLER
select ARM_GIC select ARM_GIC
select MFD_SUN6I_PRCM select MFD_SUN6I_PRCM
select RESET_CONTROLLER
config MACH_SUN9I config MACH_SUN9I
bool "Allwinner (sun9i) SoCs support" bool "Allwinner (sun9i) SoCs support"
default ARCH_SUNXI default ARCH_SUNXI
select ARCH_HAS_RESET_CONTROLLER
select ARM_GIC select ARM_GIC
select RESET_CONTROLLER
endif endif
...@@ -799,6 +799,7 @@ static int omap_dm_timer_probe(struct platform_device *pdev) ...@@ -799,6 +799,7 @@ static int omap_dm_timer_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev; struct device *dev = &pdev->dev;
const struct of_device_id *match; const struct of_device_id *match;
const struct dmtimer_platform_data *pdata; const struct dmtimer_platform_data *pdata;
int ret;
match = of_match_device(of_match_ptr(omap_timer_match), dev); match = of_match_device(of_match_ptr(omap_timer_match), dev);
pdata = match ? match->data : dev->platform_data; pdata = match ? match->data : dev->platform_data;
...@@ -860,7 +861,12 @@ static int omap_dm_timer_probe(struct platform_device *pdev) ...@@ -860,7 +861,12 @@ static int omap_dm_timer_probe(struct platform_device *pdev)
} }
if (!timer->reserved) { if (!timer->reserved) {
pm_runtime_get_sync(dev); ret = pm_runtime_get_sync(dev);
if (ret < 0) {
dev_err(dev, "%s: pm_runtime_get_sync failed!\n",
__func__);
goto err_get_sync;
}
__omap_dm_timer_init_regs(timer); __omap_dm_timer_init_regs(timer);
pm_runtime_put(dev); pm_runtime_put(dev);
} }
...@@ -873,6 +879,11 @@ static int omap_dm_timer_probe(struct platform_device *pdev) ...@@ -873,6 +879,11 @@ static int omap_dm_timer_probe(struct platform_device *pdev)
dev_dbg(dev, "Device Probed.\n"); dev_dbg(dev, "Device Probed.\n");
return 0; return 0;
err_get_sync:
pm_runtime_put_noidle(dev);
pm_runtime_disable(dev);
return ret;
} }
/** /**
...@@ -899,6 +910,8 @@ static int omap_dm_timer_remove(struct platform_device *pdev) ...@@ -899,6 +910,8 @@ static int omap_dm_timer_remove(struct platform_device *pdev)
} }
spin_unlock_irqrestore(&dm_timer_lock, flags); spin_unlock_irqrestore(&dm_timer_lock, flags);
pm_runtime_disable(&pdev->dev);
return ret; return ret;
} }
......
...@@ -8,7 +8,7 @@ ...@@ -8,7 +8,7 @@
*/ */
/* SoC fixed clocks */ /* SoC fixed clocks */
soc_uartclk: refclk72738khz { soc_uartclk: refclk7273800hz {
compatible = "fixed-clock"; compatible = "fixed-clock";
#clock-cells = <0>; #clock-cells = <0>;
clock-frequency = <7273800>; clock-frequency = <7273800>;
......
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