Commit 094526b2 authored by Bolarinwa Olayemi Saheed's avatar Bolarinwa Olayemi Saheed Committed by Kelsey Skunberg

iwlegacy: Check the return value of pcie_capability_read_*()

BugLink: https://bugs.launchpad.net/bugs/1892822

[ Upstream commit 9018fd7f ]

On failure pcie_capability_read_dword() sets it's last parameter, val
to 0. However, with Patch 14/14, it is possible that val is set to ~0 on
failure. This would introduce a bug because (x & x) == (~0 & x).

This bug can be avoided without changing the function's behaviour if the
return value of pcie_capability_read_dword is checked to confirm success.

Check the return value of pcie_capability_read_dword() to ensure success.
Suggested-by: default avatarBjorn Helgaas <bjorn@helgaas.com>
Signed-off-by: default avatarBolarinwa Olayemi Saheed <refactormyself@gmail.com>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20200713175529.29715-3-refactormyself@gmail.comSigned-off-by: default avatarSasha Levin <sashal@kernel.org>
Signed-off-by: default avatarKhalid Elmously <khalid.elmously@canonical.com>
Signed-off-by: default avatarIan May <ian.may@canonical.com>
Signed-off-by: default avatarKelsey Skunberg <kelsey.skunberg@canonical.com>
parent c88a5909
...@@ -4294,8 +4294,8 @@ il_apm_init(struct il_priv *il) ...@@ -4294,8 +4294,8 @@ il_apm_init(struct il_priv *il)
* power savings, even without L1. * power savings, even without L1.
*/ */
if (il->cfg->set_l0s) { if (il->cfg->set_l0s) {
pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &lctl); ret = pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &lctl);
if (lctl & PCI_EXP_LNKCTL_ASPM_L1) { if (!ret && (lctl & PCI_EXP_LNKCTL_ASPM_L1)) {
/* L1-ASPM enabled; disable(!) L0S */ /* L1-ASPM enabled; disable(!) L0S */
il_set_bit(il, CSR_GIO_REG, il_set_bit(il, CSR_GIO_REG,
CSR_GIO_REG_VAL_L0S_ENABLED); CSR_GIO_REG_VAL_L0S_ENABLED);
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment