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Commit 097a8888 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Stephen Boyd
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clk: qcom: gcc-sm8350: use parent_hws where possible 

Switch to using parent_hws instead of parent_data when parents are
defined in this driver and so accessible using clk_hw.
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-25-dmitry.baryshkov@linaro.orgSigned-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 31192234
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Showing with 154 additions and 156 deletions
drivers/clk/qcom/gcc-sm8350.c
View file @ 097a8888
...@@ -70,8 +70,8 @@ static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { ...@@ -70,8 +70,8 @@ static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gpll0_out_even", .name = "gcc_gpll0_out_even",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_gpll0.clkr.hw, &gcc_gpll0.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_5lpe_ops, .ops = &clk_alpha_pll_postdiv_lucid_5lpe_ops,
...@@ -1246,8 +1246,8 @@ static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { ...@@ -1246,8 +1246,8 @@ static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
.width = 4, .width = 4,
.clkr.hw.init = &(struct clk_init_data) { .clkr.hw.init = &(struct clk_init_data) {
.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1261,8 +1261,8 @@ static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = { ...@@ -1261,8 +1261,8 @@ static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {
.width = 4, .width = 4,
.clkr.hw.init = &(struct clk_init_data) { .clkr.hw.init = &(struct clk_init_data) {
.name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src", .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw, &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1323,8 +1323,8 @@ static struct clk_branch gcc_aggre_ufs_card_axi_clk = { ...@@ -1323,8 +1323,8 @@ static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_card_axi_clk", .name = "gcc_aggre_ufs_card_axi_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_card_axi_clk_src.clkr.hw, &gcc_ufs_card_axi_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1343,8 +1343,8 @@ static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = { ...@@ -1343,8 +1343,8 @@ static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = {
.enable_mask = BIT(1), .enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_card_axi_hw_ctl_clk", .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_card_axi_clk_src.clkr.hw, &gcc_ufs_card_axi_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1363,8 +1363,8 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { ...@@ -1363,8 +1363,8 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_phy_axi_clk", .name = "gcc_aggre_ufs_phy_axi_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, &gcc_ufs_phy_axi_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1383,8 +1383,8 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = { ...@@ -1383,8 +1383,8 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
.enable_mask = BIT(1), .enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk", .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, &gcc_ufs_phy_axi_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1403,8 +1403,8 @@ static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { ...@@ -1403,8 +1403,8 @@ static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_aggre_usb3_prim_axi_clk", .name = "gcc_aggre_usb3_prim_axi_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb30_prim_master_clk_src.clkr.hw, &gcc_usb30_prim_master_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1423,8 +1423,8 @@ static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { ...@@ -1423,8 +1423,8 @@ static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_aggre_usb3_sec_axi_clk", .name = "gcc_aggre_usb3_sec_axi_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb30_sec_master_clk_src.clkr.hw, &gcc_usb30_sec_master_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1490,8 +1490,8 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { ...@@ -1490,8 +1490,8 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_prim_axi_clk", .name = "gcc_cfg_noc_usb3_prim_axi_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb30_prim_master_clk_src.clkr.hw, &gcc_usb30_prim_master_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1510,8 +1510,8 @@ static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { ...@@ -1510,8 +1510,8 @@ static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_sec_axi_clk", .name = "gcc_cfg_noc_usb3_sec_axi_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb30_sec_master_clk_src.clkr.hw, &gcc_usb30_sec_master_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1592,8 +1592,8 @@ static struct clk_branch gcc_gp1_clk = { ...@@ -1592,8 +1592,8 @@ static struct clk_branch gcc_gp1_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk", .name = "gcc_gp1_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_gp1_clk_src.clkr.hw, &gcc_gp1_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1610,8 +1610,8 @@ static struct clk_branch gcc_gp2_clk = { ...@@ -1610,8 +1610,8 @@ static struct clk_branch gcc_gp2_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk", .name = "gcc_gp2_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_gp2_clk_src.clkr.hw, &gcc_gp2_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1628,8 +1628,8 @@ static struct clk_branch gcc_gp3_clk = { ...@@ -1628,8 +1628,8 @@ static struct clk_branch gcc_gp3_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk", .name = "gcc_gp3_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_gp3_clk_src.clkr.hw, &gcc_gp3_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1646,8 +1646,8 @@ static struct clk_branch gcc_gpu_gpll0_clk_src = { ...@@ -1646,8 +1646,8 @@ static struct clk_branch gcc_gpu_gpll0_clk_src = {
.enable_mask = BIT(15), .enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_clk_src", .name = "gcc_gpu_gpll0_clk_src",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_gpll0.clkr.hw, &gcc_gpll0.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1664,8 +1664,8 @@ static struct clk_branch gcc_gpu_gpll0_div_clk_src = { ...@@ -1664,8 +1664,8 @@ static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
.enable_mask = BIT(16), .enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_div_clk_src", .name = "gcc_gpu_gpll0_div_clk_src",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_gpll0_out_even.clkr.hw, &gcc_gpll0_out_even.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1723,8 +1723,8 @@ static struct clk_branch gcc_pcie0_phy_rchng_clk = { ...@@ -1723,8 +1723,8 @@ static struct clk_branch gcc_pcie0_phy_rchng_clk = {
.enable_mask = BIT(22), .enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_phy_rchng_clk", .name = "gcc_pcie0_phy_rchng_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, &gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1741,8 +1741,8 @@ static struct clk_branch gcc_pcie1_phy_rchng_clk = { ...@@ -1741,8 +1741,8 @@ static struct clk_branch gcc_pcie1_phy_rchng_clk = {
.enable_mask = BIT(23), .enable_mask = BIT(23),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie1_phy_rchng_clk", .name = "gcc_pcie1_phy_rchng_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, &gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1759,8 +1759,8 @@ static struct clk_branch gcc_pcie_0_aux_clk = { ...@@ -1759,8 +1759,8 @@ static struct clk_branch gcc_pcie_0_aux_clk = {
.enable_mask = BIT(3), .enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk", .name = "gcc_pcie_0_aux_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_pcie_0_aux_clk_src.clkr.hw, &gcc_pcie_0_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1822,8 +1822,8 @@ static struct clk_branch gcc_pcie_0_pipe_clk = { ...@@ -1822,8 +1822,8 @@ static struct clk_branch gcc_pcie_0_pipe_clk = {
.enable_mask = BIT(4), .enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk", .name = "gcc_pcie_0_pipe_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_pcie_0_pipe_clk_src.clkr.hw, &gcc_pcie_0_pipe_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1868,8 +1868,8 @@ static struct clk_branch gcc_pcie_1_aux_clk = { ...@@ -1868,8 +1868,8 @@ static struct clk_branch gcc_pcie_1_aux_clk = {
.enable_mask = BIT(29), .enable_mask = BIT(29),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_aux_clk", .name = "gcc_pcie_1_aux_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_pcie_1_aux_clk_src.clkr.hw, &gcc_pcie_1_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1931,8 +1931,8 @@ static struct clk_branch gcc_pcie_1_pipe_clk = { ...@@ -1931,8 +1931,8 @@ static struct clk_branch gcc_pcie_1_pipe_clk = {
.enable_mask = BIT(30), .enable_mask = BIT(30),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_pipe_clk", .name = "gcc_pcie_1_pipe_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_pcie_1_pipe_clk_src.clkr.hw, &gcc_pcie_1_pipe_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1977,8 +1977,8 @@ static struct clk_branch gcc_pdm2_clk = { ...@@ -1977,8 +1977,8 @@ static struct clk_branch gcc_pdm2_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk", .name = "gcc_pdm2_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_pdm2_clk_src.clkr.hw, &gcc_pdm2_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2124,8 +2124,8 @@ static struct clk_branch gcc_qupv3_wrap0_s0_clk = { ...@@ -2124,8 +2124,8 @@ static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
.enable_mask = BIT(10), .enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s0_clk", .name = "gcc_qupv3_wrap0_s0_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2142,8 +2142,8 @@ static struct clk_branch gcc_qupv3_wrap0_s1_clk = { ...@@ -2142,8 +2142,8 @@ static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
.enable_mask = BIT(11), .enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s1_clk", .name = "gcc_qupv3_wrap0_s1_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2160,8 +2160,8 @@ static struct clk_branch gcc_qupv3_wrap0_s2_clk = { ...@@ -2160,8 +2160,8 @@ static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
.enable_mask = BIT(12), .enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s2_clk", .name = "gcc_qupv3_wrap0_s2_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2178,8 +2178,8 @@ static struct clk_branch gcc_qupv3_wrap0_s3_clk = { ...@@ -2178,8 +2178,8 @@ static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
.enable_mask = BIT(13), .enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s3_clk", .name = "gcc_qupv3_wrap0_s3_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2196,8 +2196,8 @@ static struct clk_branch gcc_qupv3_wrap0_s4_clk = { ...@@ -2196,8 +2196,8 @@ static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
.enable_mask = BIT(14), .enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s4_clk", .name = "gcc_qupv3_wrap0_s4_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2214,8 +2214,8 @@ static struct clk_branch gcc_qupv3_wrap0_s5_clk = { ...@@ -2214,8 +2214,8 @@ static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
.enable_mask = BIT(15), .enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s5_clk", .name = "gcc_qupv3_wrap0_s5_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2232,8 +2232,8 @@ static struct clk_branch gcc_qupv3_wrap0_s6_clk = { ...@@ -2232,8 +2232,8 @@ static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
.enable_mask = BIT(16), .enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s6_clk", .name = "gcc_qupv3_wrap0_s6_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, &gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2250,8 +2250,8 @@ static struct clk_branch gcc_qupv3_wrap0_s7_clk = { ...@@ -2250,8 +2250,8 @@ static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
.enable_mask = BIT(17), .enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s7_clk", .name = "gcc_qupv3_wrap0_s7_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, &gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2324,8 +2324,8 @@ static struct clk_branch gcc_qupv3_wrap1_s0_clk = { ...@@ -2324,8 +2324,8 @@ static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
.enable_mask = BIT(22), .enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s0_clk", .name = "gcc_qupv3_wrap1_s0_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2342,8 +2342,8 @@ static struct clk_branch gcc_qupv3_wrap1_s1_clk = { ...@@ -2342,8 +2342,8 @@ static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
.enable_mask = BIT(23), .enable_mask = BIT(23),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s1_clk", .name = "gcc_qupv3_wrap1_s1_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2360,8 +2360,8 @@ static struct clk_branch gcc_qupv3_wrap1_s2_clk = { ...@@ -2360,8 +2360,8 @@ static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
.enable_mask = BIT(24), .enable_mask = BIT(24),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s2_clk", .name = "gcc_qupv3_wrap1_s2_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2378,8 +2378,8 @@ static struct clk_branch gcc_qupv3_wrap1_s3_clk = { ...@@ -2378,8 +2378,8 @@ static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
.enable_mask = BIT(25), .enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s3_clk", .name = "gcc_qupv3_wrap1_s3_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2396,8 +2396,8 @@ static struct clk_branch gcc_qupv3_wrap1_s4_clk = { ...@@ -2396,8 +2396,8 @@ static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
.enable_mask = BIT(26), .enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s4_clk", .name = "gcc_qupv3_wrap1_s4_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2414,8 +2414,8 @@ static struct clk_branch gcc_qupv3_wrap1_s5_clk = { ...@@ -2414,8 +2414,8 @@ static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
.enable_mask = BIT(27), .enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s5_clk", .name = "gcc_qupv3_wrap1_s5_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2458,8 +2458,8 @@ static struct clk_branch gcc_qupv3_wrap2_s0_clk = { ...@@ -2458,8 +2458,8 @@ static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
.enable_mask = BIT(4), .enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s0_clk", .name = "gcc_qupv3_wrap2_s0_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, &gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2476,8 +2476,8 @@ static struct clk_branch gcc_qupv3_wrap2_s1_clk = { ...@@ -2476,8 +2476,8 @@ static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
.enable_mask = BIT(5), .enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s1_clk", .name = "gcc_qupv3_wrap2_s1_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, &gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2494,8 +2494,8 @@ static struct clk_branch gcc_qupv3_wrap2_s2_clk = { ...@@ -2494,8 +2494,8 @@ static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
.enable_mask = BIT(6), .enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s2_clk", .name = "gcc_qupv3_wrap2_s2_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, &gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2512,8 +2512,8 @@ static struct clk_branch gcc_qupv3_wrap2_s3_clk = { ...@@ -2512,8 +2512,8 @@ static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
.enable_mask = BIT(7), .enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s3_clk", .name = "gcc_qupv3_wrap2_s3_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, &gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2530,8 +2530,8 @@ static struct clk_branch gcc_qupv3_wrap2_s4_clk = { ...@@ -2530,8 +2530,8 @@ static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
.enable_mask = BIT(8), .enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s4_clk", .name = "gcc_qupv3_wrap2_s4_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, &gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2548,8 +2548,8 @@ static struct clk_branch gcc_qupv3_wrap2_s5_clk = { ...@@ -2548,8 +2548,8 @@ static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
.enable_mask = BIT(9), .enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s5_clk", .name = "gcc_qupv3_wrap2_s5_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, &gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2639,8 +2639,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = { ...@@ -2639,8 +2639,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk", .name = "gcc_sdcc2_apps_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_sdcc2_apps_clk_src.clkr.hw, &gcc_sdcc2_apps_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2670,8 +2670,8 @@ static struct clk_branch gcc_sdcc4_apps_clk = { ...@@ -2670,8 +2670,8 @@ static struct clk_branch gcc_sdcc4_apps_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk", .name = "gcc_sdcc4_apps_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_sdcc4_apps_clk_src.clkr.hw, &gcc_sdcc4_apps_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2731,8 +2731,8 @@ static struct clk_branch gcc_ufs_card_axi_clk = { ...@@ -2731,8 +2731,8 @@ static struct clk_branch gcc_ufs_card_axi_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_axi_clk", .name = "gcc_ufs_card_axi_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_card_axi_clk_src.clkr.hw, &gcc_ufs_card_axi_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2751,8 +2751,8 @@ static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = { ...@@ -2751,8 +2751,8 @@ static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = {
.enable_mask = BIT(1), .enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_axi_hw_ctl_clk", .name = "gcc_ufs_card_axi_hw_ctl_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_card_axi_clk_src.clkr.hw, &gcc_ufs_card_axi_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2771,8 +2771,8 @@ static struct clk_branch gcc_ufs_card_ice_core_clk = { ...@@ -2771,8 +2771,8 @@ static struct clk_branch gcc_ufs_card_ice_core_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_ice_core_clk", .name = "gcc_ufs_card_ice_core_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_card_ice_core_clk_src.clkr.hw, &gcc_ufs_card_ice_core_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2791,8 +2791,8 @@ static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = { ...@@ -2791,8 +2791,8 @@ static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = {
.enable_mask = BIT(1), .enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_ice_core_hw_ctl_clk", .name = "gcc_ufs_card_ice_core_hw_ctl_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_card_ice_core_clk_src.clkr.hw, &gcc_ufs_card_ice_core_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2811,8 +2811,8 @@ static struct clk_branch gcc_ufs_card_phy_aux_clk = { ...@@ -2811,8 +2811,8 @@ static struct clk_branch gcc_ufs_card_phy_aux_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_phy_aux_clk", .name = "gcc_ufs_card_phy_aux_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_card_phy_aux_clk_src.clkr.hw, &gcc_ufs_card_phy_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2831,8 +2831,8 @@ static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = { ...@@ -2831,8 +2831,8 @@ static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
.enable_mask = BIT(1), .enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_phy_aux_hw_ctl_clk", .name = "gcc_ufs_card_phy_aux_hw_ctl_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_card_phy_aux_clk_src.clkr.hw, &gcc_ufs_card_phy_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2850,8 +2850,8 @@ static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = { ...@@ -2850,8 +2850,8 @@ static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_rx_symbol_0_clk", .name = "gcc_ufs_card_rx_symbol_0_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_card_rx_symbol_0_clk_src.clkr.hw, &gcc_ufs_card_rx_symbol_0_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2869,8 +2869,8 @@ static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = { ...@@ -2869,8 +2869,8 @@ static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_rx_symbol_1_clk", .name = "gcc_ufs_card_rx_symbol_1_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_card_rx_symbol_1_clk_src.clkr.hw, &gcc_ufs_card_rx_symbol_1_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2888,8 +2888,8 @@ static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = { ...@@ -2888,8 +2888,8 @@ static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_tx_symbol_0_clk", .name = "gcc_ufs_card_tx_symbol_0_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_card_tx_symbol_0_clk_src.clkr.hw, &gcc_ufs_card_tx_symbol_0_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2908,8 +2908,8 @@ static struct clk_branch gcc_ufs_card_unipro_core_clk = { ...@@ -2908,8 +2908,8 @@ static struct clk_branch gcc_ufs_card_unipro_core_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_unipro_core_clk", .name = "gcc_ufs_card_unipro_core_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_card_unipro_core_clk_src.clkr.hw, &gcc_ufs_card_unipro_core_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2928,8 +2928,8 @@ static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = { ...@@ -2928,8 +2928,8 @@ static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = {
.enable_mask = BIT(1), .enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_unipro_core_hw_ctl_clk", .name = "gcc_ufs_card_unipro_core_hw_ctl_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_card_unipro_core_clk_src.clkr.hw, &gcc_ufs_card_unipro_core_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2963,8 +2963,8 @@ static struct clk_branch gcc_ufs_phy_axi_clk = { ...@@ -2963,8 +2963,8 @@ static struct clk_branch gcc_ufs_phy_axi_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk", .name = "gcc_ufs_phy_axi_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, &gcc_ufs_phy_axi_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2983,8 +2983,8 @@ static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = { ...@@ -2983,8 +2983,8 @@ static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
.enable_mask = BIT(1), .enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_hw_ctl_clk", .name = "gcc_ufs_phy_axi_hw_ctl_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, &gcc_ufs_phy_axi_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -3003,8 +3003,8 @@ static struct clk_branch gcc_ufs_phy_ice_core_clk = { ...@@ -3003,8 +3003,8 @@ static struct clk_branch gcc_ufs_phy_ice_core_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk", .name = "gcc_ufs_phy_ice_core_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw, &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -3023,8 +3023,8 @@ static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = { ...@@ -3023,8 +3023,8 @@ static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
.enable_mask = BIT(1), .enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_hw_ctl_clk", .name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw, &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -3043,8 +3043,8 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk = { ...@@ -3043,8 +3043,8 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk", .name = "gcc_ufs_phy_phy_aux_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -3063,8 +3063,8 @@ static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { ...@@ -3063,8 +3063,8 @@ static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
.enable_mask = BIT(1), .enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_hw_ctl_clk", .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -3082,8 +3082,8 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { ...@@ -3082,8 +3082,8 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_0_clk", .name = "gcc_ufs_phy_rx_symbol_0_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -3101,8 +3101,8 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { ...@@ -3101,8 +3101,8 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_rx_symbol_1_clk", .name = "gcc_ufs_phy_rx_symbol_1_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -3120,8 +3120,8 @@ static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { ...@@ -3120,8 +3120,8 @@ static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_tx_symbol_0_clk", .name = "gcc_ufs_phy_tx_symbol_0_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -3140,8 +3140,8 @@ static struct clk_branch gcc_ufs_phy_unipro_core_clk = { ...@@ -3140,8 +3140,8 @@ static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk", .name = "gcc_ufs_phy_unipro_core_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -3160,8 +3160,8 @@ static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = { ...@@ -3160,8 +3160,8 @@ static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
.enable_mask = BIT(1), .enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_hw_ctl_clk", .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -3178,8 +3178,8 @@ static struct clk_branch gcc_usb30_prim_master_clk = { ...@@ -3178,8 +3178,8 @@ static struct clk_branch gcc_usb30_prim_master_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk", .name = "gcc_usb30_prim_master_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb30_prim_master_clk_src.clkr.hw, &gcc_usb30_prim_master_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -3209,8 +3209,7 @@ static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { ...@@ -3209,8 +3209,7 @@ static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk", .name = "gcc_usb30_prim_mock_utmi_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw =
&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
...@@ -3241,8 +3240,8 @@ static struct clk_branch gcc_usb30_sec_master_clk = { ...@@ -3241,8 +3240,8 @@ static struct clk_branch gcc_usb30_sec_master_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_master_clk", .name = "gcc_usb30_sec_master_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb30_sec_master_clk_src.clkr.hw, &gcc_usb30_sec_master_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -3272,8 +3271,7 @@ static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { ...@@ -3272,8 +3271,7 @@ static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_mock_utmi_clk", .name = "gcc_usb30_sec_mock_utmi_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw =
&gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw, &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
...@@ -3304,8 +3302,8 @@ static struct clk_branch gcc_usb3_prim_phy_aux_clk = { ...@@ -3304,8 +3302,8 @@ static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk", .name = "gcc_usb3_prim_phy_aux_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -3322,8 +3320,8 @@ static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { ...@@ -3322,8 +3320,8 @@ static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_com_aux_clk", .name = "gcc_usb3_prim_phy_com_aux_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -3343,8 +3341,8 @@ static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { ...@@ -3343,8 +3341,8 @@ static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_pipe_clk", .name = "gcc_usb3_prim_phy_pipe_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -3374,8 +3372,8 @@ static struct clk_branch gcc_usb3_sec_phy_aux_clk = { ...@@ -3374,8 +3372,8 @@ static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_aux_clk", .name = "gcc_usb3_sec_phy_aux_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -3392,8 +3390,8 @@ static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { ...@@ -3392,8 +3390,8 @@ static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_com_aux_clk", .name = "gcc_usb3_sec_phy_com_aux_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -3411,8 +3409,8 @@ static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { ...@@ -3411,8 +3409,8 @@ static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_pipe_clk", .name = "gcc_usb3_sec_phy_pipe_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw, &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
......
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