Commit 0a4f2520 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher

drm/amdgpu: split ip hw_init into 2 phases

We need to do some IPs earlier to deal with ordering issues
similar to how resume is split into two phases.

Will do fw loading via smu/psp between the two phases.
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 735f654e
...@@ -1525,6 +1525,51 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) ...@@ -1525,6 +1525,51 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
return 0; return 0;
} }
static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev)
{
int i, r;
for (i = 0; i < adev->num_ip_blocks; i++) {
if (!adev->ip_blocks[i].status.sw)
continue;
if (adev->ip_blocks[i].status.hw)
continue;
if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) {
r = adev->ip_blocks[i].version->funcs->hw_init(adev);
if (r) {
DRM_ERROR("hw_init of IP block <%s> failed %d\n",
adev->ip_blocks[i].version->funcs->name, r);
return r;
}
adev->ip_blocks[i].status.hw = true;
}
}
return 0;
}
static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev)
{
int i, r;
for (i = 0; i < adev->num_ip_blocks; i++) {
if (!adev->ip_blocks[i].status.sw)
continue;
if (adev->ip_blocks[i].status.hw)
continue;
r = adev->ip_blocks[i].version->funcs->hw_init(adev);
if (r) {
DRM_ERROR("hw_init of IP block <%s> failed %d\n",
adev->ip_blocks[i].version->funcs->name, r);
return r;
}
adev->ip_blocks[i].status.hw = true;
}
return 0;
}
/** /**
* amdgpu_device_ip_init - run init for hardware IPs * amdgpu_device_ip_init - run init for hardware IPs
* *
...@@ -1584,19 +1629,14 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) ...@@ -1584,19 +1629,14 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/ r = amdgpu_ucode_create_bo(adev); /* create ucode bo when sw_init complete*/
if (r) if (r)
return r; return r;
for (i = 0; i < adev->num_ip_blocks; i++) {
if (!adev->ip_blocks[i].status.sw) r = amdgpu_device_ip_hw_init_phase1(adev);
continue; if (r)
if (adev->ip_blocks[i].status.hw) return r;
continue;
r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); r = amdgpu_device_ip_hw_init_phase2(adev);
if (r) { if (r)
DRM_ERROR("hw_init of IP block <%s> failed %d\n",
adev->ip_blocks[i].version->funcs->name, r);
return r; return r;
}
adev->ip_blocks[i].status.hw = true;
}
amdgpu_xgmi_add_device(adev); amdgpu_xgmi_add_device(adev);
amdgpu_amdkfd_device_init(adev); amdgpu_amdkfd_device_init(adev);
......
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