Commit 0aa38df7 authored by Michael Chan's avatar Michael Chan Committed by David S. Miller

[BNX2]: Enable DMA on 5709.

Add missing code to enable DMA on 5709 A1.  The bit is a no-op on A0
and therefore can be set on all 5709 chips.
Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Acked-by: default avatarJeff Garzik <jeff@garzik.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 641bdcd5
...@@ -3815,6 +3815,11 @@ bnx2_init_chip(struct bnx2 *bp) ...@@ -3815,6 +3815,11 @@ bnx2_init_chip(struct bnx2 *bp)
/* Initialize the receive filter. */ /* Initialize the receive filter. */
bnx2_set_rx_mode(bp->dev); bnx2_set_rx_mode(bp->dev);
if (CHIP_NUM(bp) == CHIP_NUM_5709) {
val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
}
rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET, rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
0); 0);
......
...@@ -1373,6 +1373,7 @@ struct l2_fhdr { ...@@ -1373,6 +1373,7 @@ struct l2_fhdr {
#define BNX2_MISC_NEW_CORE_CTL 0x000008c8 #define BNX2_MISC_NEW_CORE_CTL 0x000008c8
#define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS (1L<<0) #define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS (1L<<0)
#define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ (1L<<1) #define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ (1L<<1)
#define BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE (1L<<16)
#define BNX2_MISC_NEW_CORE_CTL_RESERVED_CMN (0x3fffL<<2) #define BNX2_MISC_NEW_CORE_CTL_RESERVED_CMN (0x3fffL<<2)
#define BNX2_MISC_NEW_CORE_CTL_RESERVED_TC (0xffffL<<16) #define BNX2_MISC_NEW_CORE_CTL_RESERVED_TC (0xffffL<<16)
......
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