Commit 0b590970 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher

drm/amd/powerplay: correct the supported pcie GenSpeed and LaneCount

The LCLK dpm table setup should be performed in .update_pcie_parameters().
Otherwise, the updated GenSpeed and LaneCount information will be lost.
Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 778f8e6a
...@@ -693,7 +693,6 @@ static int navi10_set_default_dpm_table(struct smu_context *smu) ...@@ -693,7 +693,6 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
PPTable_t *driver_ppt = smu->smu_table.driver_pptable; PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
struct smu_11_0_dpm_table *dpm_table; struct smu_11_0_dpm_table *dpm_table;
int ret = 0; int ret = 0;
int i;
/* socclk dpm table setup */ /* socclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.soc_table; dpm_table = &dpm_context->dpm_tables.soc_table;
...@@ -857,12 +856,6 @@ static int navi10_set_default_dpm_table(struct smu_context *smu) ...@@ -857,12 +856,6 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
dpm_table->max = dpm_table->dpm_levels[0].value; dpm_table->max = dpm_table->dpm_levels[0].value;
} }
/* lclk dpm table setup */
for (i = 0; i < MAX_PCIE_CONF; i++) {
dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i];
dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i];
}
return 0; return 0;
} }
...@@ -1936,12 +1929,16 @@ static int navi10_update_pcie_parameters(struct smu_context *smu, ...@@ -1936,12 +1929,16 @@ static int navi10_update_pcie_parameters(struct smu_context *smu,
uint32_t pcie_gen_cap, uint32_t pcie_gen_cap,
uint32_t pcie_width_cap) uint32_t pcie_width_cap)
{ {
struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
PPTable_t *pptable = smu->smu_table.driver_pptable; PPTable_t *pptable = smu->smu_table.driver_pptable;
int ret, i;
uint32_t smu_pcie_arg; uint32_t smu_pcie_arg;
int ret, i;
struct smu_dpm_context *smu_dpm = &smu->smu_dpm; /* lclk dpm table setup */
struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; for (i = 0; i < MAX_PCIE_CONF; i++) {
dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i];
dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i];
}
for (i = 0; i < NUM_LINK_LEVELS; i++) { for (i = 0; i < NUM_LINK_LEVELS; i++) {
smu_pcie_arg = (i << 16) | smu_pcie_arg = (i << 16) |
......
...@@ -602,7 +602,6 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) ...@@ -602,7 +602,6 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
PPTable_t *driver_ppt = smu->smu_table.driver_pptable; PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
struct smu_11_0_dpm_table *dpm_table; struct smu_11_0_dpm_table *dpm_table;
int ret = 0; int ret = 0;
int i;
/* socclk dpm table setup */ /* socclk dpm table setup */
dpm_table = &dpm_context->dpm_tables.soc_table; dpm_table = &dpm_context->dpm_tables.soc_table;
...@@ -820,12 +819,6 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) ...@@ -820,12 +819,6 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
dpm_table->max = dpm_table->dpm_levels[0].value; dpm_table->max = dpm_table->dpm_levels[0].value;
} }
/* lclk dpm table setup */
for (i = 0; i < MAX_PCIE_CONF; i++) {
dpm_context->dpm_tables.pcie_table.pcie_gen[i] = driver_ppt->PcieGenSpeed[i];
dpm_context->dpm_tables.pcie_table.pcie_lane[i] = driver_ppt->PcieLaneCount[i];
}
return 0; return 0;
} }
...@@ -1723,12 +1716,16 @@ static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu, ...@@ -1723,12 +1716,16 @@ static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
uint32_t pcie_gen_cap, uint32_t pcie_gen_cap,
uint32_t pcie_width_cap) uint32_t pcie_width_cap)
{ {
struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
PPTable_t *pptable = smu->smu_table.driver_pptable; PPTable_t *pptable = smu->smu_table.driver_pptable;
int ret, i;
uint32_t smu_pcie_arg; uint32_t smu_pcie_arg;
int ret, i;
struct smu_dpm_context *smu_dpm = &smu->smu_dpm; /* lclk dpm table setup */
struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; for (i = 0; i < MAX_PCIE_CONF; i++) {
dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i];
dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i];
}
for (i = 0; i < NUM_LINK_LEVELS; i++) { for (i = 0; i < NUM_LINK_LEVELS; i++) {
smu_pcie_arg = (i << 16) | smu_pcie_arg = (i << 16) |
......
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