Commit 0b65f83f authored by Dave Airlie's avatar Dave Airlie Committed by Dave Airlie

drm/radeon/cayman: setup hdp to invalidate and flush when asked

On cayman we need to set the bit to cause HDP flushes to invalidate the
HDP cache also.
Reviewed-by: default avatarAlex Deucher <alexdeucher@gmail.com>
cc: stable@kernel.org
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent f25a5c63
...@@ -931,6 +931,10 @@ static void cayman_gpu_init(struct radeon_device *rdev) ...@@ -931,6 +931,10 @@ static void cayman_gpu_init(struct radeon_device *rdev)
WREG32(CB_PERF_CTR3_SEL_0, 0); WREG32(CB_PERF_CTR3_SEL_0, 0);
WREG32(CB_PERF_CTR3_SEL_1, 0); WREG32(CB_PERF_CTR3_SEL_1, 0);
tmp = RREG32(HDP_MISC_CNTL);
tmp |= HDP_FLUSH_INVALIDATE_CACHE;
WREG32(HDP_MISC_CNTL, tmp);
hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
......
...@@ -136,6 +136,8 @@ ...@@ -136,6 +136,8 @@
#define HDP_NONSURFACE_INFO 0x2C08 #define HDP_NONSURFACE_INFO 0x2C08
#define HDP_NONSURFACE_SIZE 0x2C0C #define HDP_NONSURFACE_SIZE 0x2C0C
#define HDP_ADDR_CONFIG 0x2F48 #define HDP_ADDR_CONFIG 0x2F48
#define HDP_MISC_CNTL 0x2F4C
#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
#define CC_SYS_RB_BACKEND_DISABLE 0x3F88 #define CC_SYS_RB_BACKEND_DISABLE 0x3F88
#define GC_USER_SYS_RB_BACKEND_DISABLE 0x3F8C #define GC_USER_SYS_RB_BACKEND_DISABLE 0x3F8C
......
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