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Commit 0b9c5cdd authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'hisi-arm64-dt-for-5.12v2' of git://github.com/hisilicon/linux-hisi into arm/dt 

ARM64: DT: Hisilicon ARM64 DT updates for 5.12

- Further cleanups of the hisilicon DTS to align with the dtschema
- Add or update the I2C, pinctrl and reset nodes for Hikey970

* tag 'hisi-arm64-dt-for-5.12v2' of git://github.com/hisilicon/linux-hisi:
  arm64: dts: hisilicon: hi3670.dtsi: add I2C settings
  arm64: dts: hisilicon: hikey970-pinctrl.dtsi: add missing pinctrl settings
  arm64: dts: hisilicon: hi3670.dtsi: add iomcu_rst
  arm64: dts: hisilicon: delete unused property smmu-cb-memtype
  arm64: dts: hisilicon: avoid irrelevant nodes being mistakenly identified as PHY nodes
  arm64: dts: hisilicon: normalize the node name of the localbus
  arm64: dts: hisilicon: normalize the node name of the module thermal
  arm64: dts: hisilicon: place clock-names "bus" before "core"
  arm64: dts: hisilicon: separate each group of data in the property "ranges"

Link: https://lore.kernel.org/r/6013D1C7.90902@hisilicon.comSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 1f99bd1a b6e141ee
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arch/arm64/boot/dts/hisilicon/hi3660.dtsi
View file @ 0b9c5cdd
......@@ -1113,7 +1113,7 @@ tsensor: tsensor@fff30000 {
thermal-zones {
cls0: cls0 {
cls0: cls0-thermal {
polling-delay = <1000>;
polling-delay-passive = <100>;
sustainable-power = <4500>;
......@@ -1122,13 +1122,13 @@ cls0: cls0 {
thermal-sensors = <&tsensor 1>;
trips {
threshold: trip-point@0 {
threshold: trip-point0 {
temperature = <65000>;
hysteresis = <1000>;
type = "passive";
};
target: trip-point@1 {
target: trip-point1 {
temperature = <75000>;
hysteresis = <1000>;
type = "passive";
......
arch/arm64/boot/dts/hisilicon/hi3670.dtsi
View file @ 0b9c5cdd
......@@ -194,6 +194,12 @@ media2_crg: media2_crgctrl@e8900000 {
#clock-cells = <1>;
};
iomcu_rst: reset {
compatible = "hisilicon,hi3660-reset";
hisi,rst-syscon = <&iomcu>;
#reset-cells = <2>;
};
uart0: serial@fdf02000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xfdf02000 0x0 0x1000>;
......@@ -708,5 +714,76 @@ dwmmc2: dwmmc2@fc183000 {
card-detect-delay = <200>;
status = "disabled";
};
/* I2C */
i2c0: i2c@ffd71000 {
compatible = "snps,designware-i2c";
reg = <0x0 0xffd71000 0x0 0x1000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
clocks = <&iomcu HI3670_CLK_GATE_I2C0>;
resets = <&iomcu_rst 0x20 3>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
status = "disabled";
};
i2c1: i2c@ffd72000 {
compatible = "snps,designware-i2c";
reg = <0x0 0xffd72000 0x0 0x1000>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
clocks = <&iomcu HI3670_CLK_GATE_I2C1>;
resets = <&iomcu_rst 0x20 4>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
status = "disabled";
};
i2c2: i2c@ffd73000 {
compatible = "snps,designware-i2c";
reg = <0x0 0xffd73000 0x0 0x1000>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
clocks = <&iomcu HI3670_CLK_GATE_I2C2>;
resets = <&iomcu_rst 0x20 5>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
status = "disabled";
};
i2c3: i2c@fdf0c000 {
compatible = "snps,designware-i2c";
reg = <0x0 0xfdf0c000 0x0 0x1000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
clocks = <&crg_ctrl HI3670_CLK_GATE_I2C3>;
resets = <&crg_rst 0x78 7>;
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
status = "disabled";
};
i2c4: i2c@fdf0d000 {
compatible = "snps,designware-i2c";
reg = <0x0 0xfdf0d000 0x0 0x1000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
clocks = <&crg_ctrl HI3670_CLK_GATE_I2C4>;
resets = <&crg_rst 0x78 27>;
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pmx_func &i2c4_cfg_func>;
status = "disabled";
};
};
};
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
View file @ 0b9c5cdd
......@@ -113,7 +113,7 @@ perictrl: peripheral-controller@8a20000 {
#size-cells = <1>;
ranges = <0x0 0x8a20000 0x1000>;
usb2_phy1: usb2-phy@120 {
usb2_phy1: usb2_phy@120 {
compatible = "hisilicon,hi3798cv200-usb2-phy";
reg = <0x120 0x4>;
clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
......@@ -134,7 +134,7 @@ usb2_phy1_port1: phy@1 {
};
};
usb2_phy2: usb2-phy@124 {
usb2_phy2: usb2_phy@124 {
compatible = "hisilicon,hi3798cv200-usb2-phy";
reg = <0x124 0x4>;
clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
......@@ -565,8 +565,8 @@ pcie: pcie@9860000 {
device_type = "pci";
bus-range = <0x00 0xff>;
num-lanes = <1>;
ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000
0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>;
ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000>,
<0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
......
arch/arm64/boot/dts/hisilicon/hi6220.dtsi
View file @ 0b9c5cdd
......@@ -872,7 +872,7 @@ i2s0: i2s@f7118000{
thermal-zones {
cls0: cls0 {
cls0: cls0-thermal {
polling-delay = <1000>;
polling-delay-passive = <100>;
sustainable-power = <3326>;
......@@ -881,13 +881,13 @@ cls0: cls0 {
thermal-sensors = <&tsensor 2>;
trips {
threshold: trip-point@0 {
threshold: trip-point0 {
temperature = <65000>;
hysteresis = <0>;
type = "passive";
};
target: trip-point@1 {
target: trip-point1 {
temperature = <75000>;
hysteresis = <0>;
type = "passive";
......@@ -1053,7 +1053,7 @@ mali: gpu@f4080000 {
"ppmmu3";
clocks = <&media_ctrl HI6220_G3D_CLK>,
<&media_ctrl HI6220_G3D_PCLK>;
clock-names = "core", "bus";
clock-names = "bus", "core";
assigned-clocks = <&media_ctrl HI6220_G3D_CLK>,
<&media_ctrl HI6220_G3D_PCLK>;
assigned-clock-rates = <500000000>, <144000000>;
......
arch/arm64/boot/dts/hisilicon/hikey970-pinctrl.dtsi
View file @ 0b9c5cdd
......@@ -61,6 +61,153 @@ uart6_pmx_func: uart6_pmx_func {
0x060 MUX_M1 /* UART6_TXD */
>;
};
i2c3_pmx_func: i2c3_pmx_func {
pinctrl-single,pins = <
0x010 MUX_M1 /* I2C3_SCL */
0x014 MUX_M1 /* I2C3_SDA */
>;
};
i2c4_pmx_func: i2c4_pmx_func {
pinctrl-single,pins = <
0x03c MUX_M1 /* I2C4_SCL */
0x040 MUX_M1 /* I2C4_SDA */
>;
};
cam0_rst_pmx_func: cam0_rst_pmx_func {
pinctrl-single,pins = <
0x714 MUX_M0 /* CAM0_RST */
>;
};
cam1_rst_pmx_func: cam1_rst_pmx_func {
pinctrl-single,pins = <
0x048 MUX_M0 /* CAM1_RST */
>;
};
cam0_pwd_n_pmx_func: cam0_pwd_n_pmx_func {
pinctrl-single,pins = <
0x098 MUX_M0 /* CAM0_PWD_N */
>;
};
cam1_pwd_n_pmx_func: cam1_pwd_n_pmx_func {
pinctrl-single,pins = <
0x044 MUX_M0 /* CAM1_PWD_N */
>;
};
isp0_pmx_func: isp0_pmx_func {
pinctrl-single,pins = <
0x018 MUX_M1 /* ISP_CLK0 */
0x024 MUX_M1 /* ISP_SCL0 */
0x028 MUX_M1 /* ISP_SDA0 */
>;
};
isp1_pmx_func: isp1_pmx_func {
pinctrl-single,pins = <
0x01c MUX_M1 /* ISP_CLK1 */
0x02c MUX_M1 /* ISP_SCL1 */
0x030 MUX_M1 /* ISP_SDA1 */
>;
};
};
pmx1: pinmux@fff11000 {
compatible = "pinctrl-single";
reg = <0x0 0xfff11000 0x0 0x73c>;
#gpio-range-cells = <0x3>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <0x20>;
pinctrl-single,function-mask = <0x7>;
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 46 0>;
pwr_key_pmx_func: pwr_key_pmx_func {
pinctrl-single,pins = <
0x064 MUX_M0 /* GPIO_203 */
>;
};
pd_pmx_func: pd_pmx_func{
pinctrl-single,pins = <
0x080 MUX_M0 /* GPIO_221 */
>;
};
i2s2_pmx_func: i2s2_pmx_func {
pinctrl-single,pins = <
0x050 MUX_M1 /* I2S2_DI */
0x054 MUX_M1 /* I2S2_DO */
0x058 MUX_M1 /* I2S2_XCLK */
0x05c MUX_M1 /* I2S2_XFS */
>;
};
spi0_pmx_func: spi0_pmx_func {
pinctrl-single,pins = <
0x094 MUX_M1 /* SPI0_CLK */
0x098 MUX_M1 /* SPI0_DI */
0x09c MUX_M1 /* SPI0_DO */
0x0a0 MUX_M1 /* SPI0_CS0_N */
>;
};
spi2_pmx_func: spi2_pmx_func {
pinctrl-single,pins = <
0x710 MUX_M1 /* SPI2_CLK */
0x714 MUX_M1 /* SPI2_DI */
0x718 MUX_M1 /* SPI2_DO */
0x71c MUX_M1 /* SPI2_CS0_N */
>;
};
spi3_pmx_func: spi3_pmx_func {
pinctrl-single,pins = <
0x72c MUX_M1 /* SPI3_CLK */
0x730 MUX_M1 /* SPI3_DI */
0x734 MUX_M1 /* SPI3_DO */
0x738 MUX_M1 /* SPI3_CS0_N */
>;
};
i2c0_pmx_func: i2c0_pmx_func {
pinctrl-single,pins = <
0x020 MUX_M1 /* I2C0_SCL */
0x024 MUX_M1 /* I2C0_SDA */
>;
};
i2c1_pmx_func: i2c1_pmx_func {
pinctrl-single,pins = <
0x028 MUX_M1 /* I2C1_SCL */
0x02c MUX_M1 /* I2C1_SDA */
>;
};
i2c2_pmx_func: i2c2_pmx_func {
pinctrl-single,pins = <
0x030 MUX_M1 /* I2C2_SCL */
0x034 MUX_M1 /* I2C2_SDA */
>;
};
pcie_clkreq_pmx_func: pcie_clkreq_pmx_func {
pinctrl-single,pins = <
0x084 MUX_M1 /* PCIE0_CLKREQ_N */
>;
};
gpio185_pmx_func: gpio185_pmx_func {
pinctrl-single,pins = <0x01C 0x1>;
};
gpio185_pmx_idle: gpio185_pmx_idle {
pinctrl-single,pins = <0x01C 0x0>;
};
};
pmx2: pinmux@e896c800 {
......@@ -184,6 +331,180 @@ PULL_UP
DRIVE7_02MA DRIVE6_MASK
>;
};
i2c3_cfg_func: i2c3_cfg_func {
pinctrl-single,pins = <
0x014 0x0 /* I2C3_SCL */
0x018 0x0 /* I2C3_SDA */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_04MA DRIVE6_MASK
>;
};
i2c4_cfg_func: i2c4_cfg_func {
pinctrl-single,pins = <
0x040 0x0 /* I2C4_SCL */
0x044 0x0 /* I2C4_SDA */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_04MA DRIVE6_MASK
>;
};
cam0_rst_cfg_func: cam0_rst_cfg_func {
pinctrl-single,pins = <
0x714 0x0 /* CAM0_RST */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_04MA DRIVE6_MASK
>;
};
cam1_rst_cfg_func: cam1_rst_cfg_func {
pinctrl-single,pins = <
0x04C 0x0 /* CAM1_RST */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_04MA DRIVE6_MASK
>;
};
cam0_pwd_n_cfg_func: cam0_pwd_n_cfg_func {
pinctrl-single,pins = <
0x09C 0x0 /* CAM0_PWD_N */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_04MA DRIVE6_MASK
>;
};
cam1_pwd_n_cfg_func: cam1_pwd_n_cfg_func {
pinctrl-single,pins = <
0x048 0x0 /* CAM1_PWD_N */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_04MA DRIVE6_MASK
>;
};
isp0_cfg_func: isp0_cfg_func {
pinctrl-single,pins = <
0x01C 0x0 /* ISP_CLK0 */
0x028 0x0 /* ISP_SCL0 */
0x02C 0x0 /* ISP_SDA0 */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_04MA DRIVE6_MASK
>;
};
isp1_cfg_func: isp1_cfg_func {
pinctrl-single,pins = <
0x020 0x0 /* ISP_CLK1 */
0x030 0x0 /* ISP_SCL1 */
0x034 0x0 /* ISP_SDA1 */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_04MA DRIVE6_MASK
>;
};
};
pmx5: pinmux@fc182000 {
......@@ -338,22 +659,311 @@ DRIVE6_MASK
};
};
pmx1: pinmux@fff11000 {
compatible = "pinctrl-single";
reg = <0x0 0xfff11000 0x0 0x73c>;
#gpio-range-cells = <0x3>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <0x20>;
pinctrl-single,function-mask = <0x7>;
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 46 0>;
};
pmx16: pinmux@fff11800 {
compatible = "pinconf-single";
reg = <0x0 0xfff11800 0x0 0x73c>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <0x20>;
pwr_key_cfg_func: pwr_key_cfg_func {
pinctrl-single,pins = <
0x090 0x0 /* GPIO_203 */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_UP
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_02MA DRIVE6_MASK
>;
};
usb_cfg_func: usb_cfg_func {
pinctrl-single,pins = <
0x0AC 0x0 /* GPIO_221 */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_UP
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_02MA DRIVE6_MASK
>;
};
spi0_cfg_func: spi0_cfg_func {
pinctrl-single,pins = <
0x0c8 0x0 /* SPI0_DI */
0x0cc 0x0 /* SPI0_DO */
0x0d0 0x0 /* SPI0_CS0_N */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_06MA DRIVE6_MASK
>;
};
spi2_cfg_func: spi2_cfg_func {
pinctrl-single,pins = <
0x714 0x0 /* SPI2_DI */
0x718 0x0 /* SPI2_DO */
0x71c 0x0 /* SPI2_CS0_N */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_06MA DRIVE6_MASK
>;
};
spi3_cfg_func: spi3_cfg_func {
pinctrl-single,pins = <
0x730 0x0 /* SPI3_DI */
0x734 0x0 /* SPI3_DO */
0x738 0x0 /* SPI3_CS0_N */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_06MA DRIVE6_MASK
>;
};
spi0_clk_cfg_func: spi0_clk_cfg_func {
pinctrl-single,pins = <
0x0c4 0x0 /* SPI0_CLK */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_10MA DRIVE6_MASK
>;
};
spi2_clk_cfg_func: spi2_clk_cfg_func {
pinctrl-single,pins = <
0x710 0x0 /* SPI2_CLK */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_10MA DRIVE6_MASK
>;
};
spi3_clk_cfg_func: spi3_clk_cfg_func {
pinctrl-single,pins = <
0x72c 0x0 /* SPI3_CLK */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_10MA DRIVE6_MASK
>;
};
i2c0_cfg_func: i2c0_cfg_func {
pinctrl-single,pins = <
0x04c 0x0 /* I2C0_SCL */
0x050 0x0 /* I2C0_SDA */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_04MA DRIVE6_MASK
>;
};
i2c1_cfg_func: i2c1_cfg_func {
pinctrl-single,pins = <
0x054 0x0 /* I2C1_SCL */
0x058 0x0 /* I2C1_SDA */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_04MA DRIVE6_MASK
>;
};
i2c2_cfg_func: i2c2_cfg_func {
pinctrl-single,pins = <
0x05c 0x0 /* I2C2_SCL */
0x060 0x0 /* I2C2_SDA */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_04MA DRIVE6_MASK
>;
};
pcie_clkreq_cfg_func: pcie_clkreq_cfg_func {
pinctrl-single,pins = <
0x0b0 0x0
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_DIS
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_06MA DRIVE6_MASK
>;
};
i2s2_cfg_func: i2s2_cfg_func {
pinctrl-single,pins = <
0x07c 0x0 /* I2S2_DI */
0x080 0x0 /* I2S2_DO */
0x084 0x0 /* I2S2_XCLK */
0x088 0x0 /* I2S2_XFS */
>;
pinctrl-single,bias-pulldown = <
PULL_DIS
PULL_DOWN
PULL_DIS
PULL_DOWN
>;
pinctrl-single,bias-pullup = <
PULL_UP
PULL_UP
PULL_DIS
PULL_UP
>;
pinctrl-single,drive-strength = <
DRIVE7_02MA DRIVE6_MASK
>;
};
gpio185_cfg_func: gpio185_cfg_func {
pinctrl-single,pins = <0x048 0>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x00 0x70>;
pinctrl-single,slew-rate = <0x0 0x80>;
};
gpio185_cfg_idle: gpio185_cfg_idle {
pinctrl-single,pins = <0x048 0>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x00 0x70>;
pinctrl-single,slew-rate = <0x0 0x80>;
};
};
};
};
arch/arm64/boot/dts/hisilicon/hip05.dtsi
View file @ 0b9c5cdd
......@@ -318,7 +318,7 @@ uart1: serial@80310000 {
status = "disabled";
};
lbc: localbus@80380000 {
lbc: local-bus@80380000 {
compatible = "hisilicon,hisi-localbus", "simple-bus";
reg = <0x0 0x80380000 0x0 0x10000>;
status = "disabled";
......
arch/arm64/boot/dts/hisilicon/hip06.dtsi
View file @ 0b9c5cdd
......@@ -335,7 +335,6 @@ smmu0: iommu@a0040000 {
reg = <0x0 0xa0040000 0x0 0x20000>;
#iommu-cells = <1>;
dma-coherent;
smmu-cb-memtype = <0x0 0x1>;
hisilicon,broken-prefetch-cmd;
status = "disabled";
};
......@@ -737,9 +736,8 @@ pcie0: pcie@a0090000 {
#size-cells = <2>;
device_type = "pci";
dma-coherent;
ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0
0x5ff0000 0x01000000 0 0 0 0xb7ff0000
0 0x10000>;
ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0 0x5ff0000>,
<0x01000000 0 0 0 0xb7ff0000 0 0x10000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4
......
arch/arm64/boot/dts/hisilicon/hip07.dtsi
View file @ 0b9c5cdd
......@@ -1166,7 +1166,6 @@ smmu0: iommu@a0040000 {
reg = <0x0 0xa0040000 0x0 0x20000>;
#iommu-cells = <1>;
dma-coherent;
smmu-cb-memtype = <0x0 0x1>;
hisilicon,broken-prefetch-cmd;
status = "disabled";
};
......@@ -1181,7 +1180,6 @@ p0_smmu_alg_a: iommu@d0040000 {
#iommu-cells = <1>;
dma-coherent;
hisilicon,broken-prefetch-cmd;
/* smmu-cb-memtype = <0x0 0x1>;*/
};
p0_smmu_alg_b: iommu@8d0040000 {
compatible = "arm,smmu-v3";
......@@ -1194,7 +1192,6 @@ p0_smmu_alg_b: iommu@8d0040000 {
#iommu-cells = <1>;
dma-coherent;
hisilicon,broken-prefetch-cmd;
/* smmu-cb-memtype = <0x0 0x1>;*/
};
p1_smmu_alg_a: iommu@400d0040000 {
compatible = "arm,smmu-v3";
......@@ -1207,7 +1204,6 @@ p1_smmu_alg_a: iommu@400d0040000 {
#iommu-cells = <1>;
dma-coherent;
hisilicon,broken-prefetch-cmd;
/* smmu-cb-memtype = <0x0 0x1>;*/
};
p1_smmu_alg_b: iommu@408d0040000 {
compatible = "arm,smmu-v3";
......@@ -1220,7 +1216,6 @@ p1_smmu_alg_b: iommu@408d0040000 {
#iommu-cells = <1>;
dma-coherent;
hisilicon,broken-prefetch-cmd;
/* smmu-cb-memtype = <0x0 0x1>;*/
};
soc {
......@@ -1708,8 +1703,8 @@ p0_pcie2_a: pcie@a00a0000 {
#size-cells = <2>;
device_type = "pci";
dma-coherent;
ranges = <0x02000000 0 0xa8000000 0 0xa8000000 0 0x77f0000
0x01000000 0 0 0 0xaf7f0000 0 0x10000>;
ranges = <0x02000000 0 0xa8000000 0 0xa8000000 0 0x77f0000>,
<0x01000000 0 0 0 0xaf7f0000 0 0x10000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0x0 0 0 1 &mbigen_pcie2_a 671 4
......
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