Commit 0ba8b9b2 authored by Russell King's avatar Russell King Committed by Russell King

[ARM] cputype: separate definitions, use them

Add asm/cputype.h, moving functions and definitions from asm/system.h
there.  Convert all users of 'processor_id' to the more efficient
read_cpuid_id() function.
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent b8e6c91c
#ifndef __ASM_ARM_CPUTYPE_H
#define __ASM_ARM_CPUTYPE_H
#include <linux/stringify.h>
#define CPUID_ID 0
#define CPUID_CACHETYPE 1
#define CPUID_TCM 2
#define CPUID_TLBTYPE 3
#ifdef CONFIG_CPU_CP15
#define read_cpuid(reg) \
({ \
unsigned int __val; \
asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \
: "=r" (__val) \
: \
: "cc"); \
__val; \
})
#else
extern unsigned int processor_id;
#define read_cpuid(reg) (processor_id)
#endif
/*
* The CPU ID never changes at run time, so we might as well tell the
* compiler that it's constant. Use this function to read the CPU ID
* rather than directly reading processor_id or read_cpuid() directly.
*/
static inline unsigned int __attribute_const__ read_cpuid_id(void)
{
return read_cpuid(CPUID_ID);
}
static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
{
return read_cpuid(CPUID_CACHETYPE);
}
/*
* Intel's XScale3 core supports some v6 features (supersections, L2)
* but advertises itself as v5 as it does not support the v6 ISA. For
* this reason, we need a way to explicitly test for this type of CPU.
*/
#ifndef CONFIG_CPU_XSC3
#define cpu_is_xsc3() 0
#else
static inline int cpu_is_xsc3(void)
{
if ((read_cpuid_id() & 0xffffe000) == 0x69056000)
return 1;
return 0;
}
#endif
#if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
#define cpu_is_xscale() 0
#else
#define cpu_is_xscale() 1
#endif
#endif
...@@ -43,11 +43,6 @@ ...@@ -43,11 +43,6 @@
#define CR_XP (1 << 23) /* Extended page tables */ #define CR_XP (1 << 23) /* Extended page tables */
#define CR_VE (1 << 24) /* Vectored interrupts */ #define CR_VE (1 << 24) /* Vectored interrupts */
#define CPUID_ID 0
#define CPUID_CACHETYPE 1
#define CPUID_TCM 2
#define CPUID_TLBTYPE 3
/* /*
* This is used to ensure the compiler did actually allocate the register we * This is used to ensure the compiler did actually allocate the register we
* asked it for some inline assembly sequences. Apparently we can't trust * asked it for some inline assembly sequences. Apparently we can't trust
...@@ -61,36 +56,8 @@ ...@@ -61,36 +56,8 @@
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
#include <linux/linkage.h> #include <linux/linkage.h>
#include <linux/stringify.h>
#include <linux/irqflags.h> #include <linux/irqflags.h>
#ifdef CONFIG_CPU_CP15
#define read_cpuid(reg) \
({ \
unsigned int __val; \
asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \
: "=r" (__val) \
: \
: "cc"); \
__val; \
})
#else
extern unsigned int processor_id;
#define read_cpuid(reg) (processor_id)
#endif
/*
* The CPU ID never changes at run time, so we might as well tell the
* compiler that it's constant. Use this function to read the CPU ID
* rather than directly reading processor_id or read_cpuid() directly.
*/
static inline unsigned int read_cpuid_id(void) __attribute_const__;
static inline unsigned int read_cpuid_id(void)
{
return read_cpuid(CPUID_ID);
}
#define __exception __attribute__((section(".exception.text"))) #define __exception __attribute__((section(".exception.text")))
struct thread_info; struct thread_info;
...@@ -131,31 +98,6 @@ extern void cpu_init(void); ...@@ -131,31 +98,6 @@ extern void cpu_init(void);
void arm_machine_restart(char mode); void arm_machine_restart(char mode);
extern void (*arm_pm_restart)(char str); extern void (*arm_pm_restart)(char str);
/*
* Intel's XScale3 core supports some v6 features (supersections, L2)
* but advertises itself as v5 as it does not support the v6 ISA. For
* this reason, we need a way to explicitly test for this type of CPU.
*/
#ifndef CONFIG_CPU_XSC3
#define cpu_is_xsc3() 0
#else
static inline int cpu_is_xsc3(void)
{
extern unsigned int processor_id;
if ((processor_id & 0xffffe000) == 0x69056000)
return 1;
return 0;
}
#endif
#if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
#define cpu_is_xscale() 0
#else
#define cpu_is_xscale() 1
#endif
#define UDBG_UNDEFINED (1 << 0) #define UDBG_UNDEFINED (1 << 0)
#define UDBG_SYSCALL (1 << 1) #define UDBG_SYSCALL (1 << 1)
#define UDBG_BADABORT (1 << 2) #define UDBG_BADABORT (1 << 2)
......
...@@ -26,6 +26,7 @@ ...@@ -26,6 +26,7 @@
#include <linux/fs.h> #include <linux/fs.h>
#include <asm/cpu.h> #include <asm/cpu.h>
#include <asm/cputype.h>
#include <asm/elf.h> #include <asm/elf.h>
#include <asm/procinfo.h> #include <asm/procinfo.h>
#include <asm/setup.h> #include <asm/setup.h>
...@@ -280,9 +281,9 @@ static inline void dump_cache(const char *prefix, int cpu, unsigned int cache) ...@@ -280,9 +281,9 @@ static inline void dump_cache(const char *prefix, int cpu, unsigned int cache)
static void __init dump_cpu_info(int cpu) static void __init dump_cpu_info(int cpu)
{ {
unsigned int info = read_cpuid(CPUID_CACHETYPE); unsigned int info = read_cpuid_cachetype();
if (info != processor_id) { if (info != read_cpuid_id()) {
printk("CPU%u: D %s %s cache\n", cpu, cache_is_vivt() ? "VIVT" : "VIPT", printk("CPU%u: D %s %s cache\n", cpu, cache_is_vivt() ? "VIVT" : "VIPT",
cache_types[CACHE_TYPE(info)]); cache_types[CACHE_TYPE(info)]);
if (CACHE_S(info)) { if (CACHE_S(info)) {
...@@ -301,15 +302,15 @@ int cpu_architecture(void) ...@@ -301,15 +302,15 @@ int cpu_architecture(void)
{ {
int cpu_arch; int cpu_arch;
if ((processor_id & 0x0008f000) == 0) { if ((read_cpuid_id() & 0x0008f000) == 0) {
cpu_arch = CPU_ARCH_UNKNOWN; cpu_arch = CPU_ARCH_UNKNOWN;
} else if ((processor_id & 0x0008f000) == 0x00007000) { } else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
cpu_arch = (processor_id & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3; cpu_arch = (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
} else if ((processor_id & 0x00080000) == 0x00000000) { } else if ((read_cpuid_id() & 0x00080000) == 0x00000000) {
cpu_arch = (processor_id >> 16) & 7; cpu_arch = (read_cpuid_id() >> 16) & 7;
if (cpu_arch) if (cpu_arch)
cpu_arch += CPU_ARCH_ARMv3; cpu_arch += CPU_ARCH_ARMv3;
} else if ((processor_id & 0x000f0000) == 0x000f0000) { } else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
unsigned int mmfr0; unsigned int mmfr0;
/* Revised CPUID format. Read the Memory Model Feature /* Revised CPUID format. Read the Memory Model Feature
...@@ -346,10 +347,10 @@ static void __init setup_processor(void) ...@@ -346,10 +347,10 @@ static void __init setup_processor(void)
* types. The linker builds this table for us from the * types. The linker builds this table for us from the
* entries in arch/arm/mm/proc-*.S * entries in arch/arm/mm/proc-*.S
*/ */
list = lookup_processor_type(processor_id); list = lookup_processor_type(read_cpuid_id());
if (!list) { if (!list) {
printk("CPU configuration botched (ID %08x), unable " printk("CPU configuration botched (ID %08x), unable "
"to continue.\n", processor_id); "to continue.\n", read_cpuid_id());
while (1); while (1);
} }
...@@ -369,7 +370,7 @@ static void __init setup_processor(void) ...@@ -369,7 +370,7 @@ static void __init setup_processor(void)
#endif #endif
printk("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n", printk("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
cpu_name, processor_id, (int)processor_id & 15, cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
proc_arch[cpu_architecture()], cr_alignment); proc_arch[cpu_architecture()], cr_alignment);
sprintf(init_utsname()->machine, "%s%c", list->arch_name, ENDIANNESS); sprintf(init_utsname()->machine, "%s%c", list->arch_name, ENDIANNESS);
...@@ -922,7 +923,7 @@ static int c_show(struct seq_file *m, void *v) ...@@ -922,7 +923,7 @@ static int c_show(struct seq_file *m, void *v)
int i; int i;
seq_printf(m, "Processor\t: %s rev %d (%s)\n", seq_printf(m, "Processor\t: %s rev %d (%s)\n",
cpu_name, (int)processor_id & 15, elf_platform); cpu_name, read_cpuid_id() & 15, elf_platform);
#if defined(CONFIG_SMP) #if defined(CONFIG_SMP)
for_each_online_cpu(i) { for_each_online_cpu(i) {
...@@ -949,30 +950,30 @@ static int c_show(struct seq_file *m, void *v) ...@@ -949,30 +950,30 @@ static int c_show(struct seq_file *m, void *v)
if (elf_hwcap & (1 << i)) if (elf_hwcap & (1 << i))
seq_printf(m, "%s ", hwcap_str[i]); seq_printf(m, "%s ", hwcap_str[i]);
seq_printf(m, "\nCPU implementer\t: 0x%02x\n", processor_id >> 24); seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24);
seq_printf(m, "CPU architecture: %s\n", proc_arch[cpu_architecture()]); seq_printf(m, "CPU architecture: %s\n", proc_arch[cpu_architecture()]);
if ((processor_id & 0x0008f000) == 0x00000000) { if ((read_cpuid_id() & 0x0008f000) == 0x00000000) {
/* pre-ARM7 */ /* pre-ARM7 */
seq_printf(m, "CPU part\t: %07x\n", processor_id >> 4); seq_printf(m, "CPU part\t: %07x\n", read_cpuid_id() >> 4);
} else { } else {
if ((processor_id & 0x0008f000) == 0x00007000) { if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
/* ARM7 */ /* ARM7 */
seq_printf(m, "CPU variant\t: 0x%02x\n", seq_printf(m, "CPU variant\t: 0x%02x\n",
(processor_id >> 16) & 127); (read_cpuid_id() >> 16) & 127);
} else { } else {
/* post-ARM7 */ /* post-ARM7 */
seq_printf(m, "CPU variant\t: 0x%x\n", seq_printf(m, "CPU variant\t: 0x%x\n",
(processor_id >> 20) & 15); (read_cpuid_id() >> 20) & 15);
} }
seq_printf(m, "CPU part\t: 0x%03x\n", seq_printf(m, "CPU part\t: 0x%03x\n",
(processor_id >> 4) & 0xfff); (read_cpuid_id() >> 4) & 0xfff);
} }
seq_printf(m, "CPU revision\t: %d\n", processor_id & 15); seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15);
{ {
unsigned int cache_info = read_cpuid(CPUID_CACHETYPE); unsigned int cache_info = read_cpuid_cachetype();
if (cache_info != processor_id) { if (cache_info != read_cpuid_id()) {
seq_printf(m, "Cache type\t: %s\n" seq_printf(m, "Cache type\t: %s\n"
"Cache clean\t: %s\n" "Cache clean\t: %s\n"
"Cache lockdown\t: %s\n" "Cache lockdown\t: %s\n"
......
...@@ -27,6 +27,7 @@ ...@@ -27,6 +27,7 @@
#include <linux/mtd/physmap.h> #include <linux/mtd/physmap.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include <asm/cputype.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/irq.h> #include <asm/irq.h>
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
...@@ -49,8 +50,7 @@ static int force_ep80219; ...@@ -49,8 +50,7 @@ static int force_ep80219;
static int is_80219(void) static int is_80219(void)
{ {
extern int processor_id; return !!((read_cpuid_id() & 0xffffffe0) == 0x69052e20);
return !!((processor_id & 0xffffffe0) == 0x69052e20);
} }
static int is_ep80219(void) static int is_ep80219(void)
......
...@@ -27,6 +27,7 @@ ...@@ -27,6 +27,7 @@
#include <linux/device.h> #include <linux/device.h>
#include <asm/dma-mapping.h> #include <asm/dma-mapping.h>
#include <asm/cputype.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/irq.h> #include <asm/irq.h>
#include <asm/sizes.h> #include <asm/sizes.h>
...@@ -366,15 +367,13 @@ void __init ixp4xx_adjust_zones(int node, unsigned long *zone_size, ...@@ -366,15 +367,13 @@ void __init ixp4xx_adjust_zones(int node, unsigned long *zone_size,
void __init ixp4xx_pci_preinit(void) void __init ixp4xx_pci_preinit(void)
{ {
unsigned long processor_id; unsigned long cpuid = read_cpuid_id();
asm("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(processor_id) :);
/* /*
* Determine which PCI read method to use. * Determine which PCI read method to use.
* Rev 0 IXP425 requires workaround. * Rev 0 IXP425 requires workaround.
*/ */
if (!(processor_id & 0xf) && cpu_is_ixp42x()) { if (!(cpuid & 0xf) && cpu_is_ixp42x()) {
printk("PCI: IXP42x A0 silicon detected - " printk("PCI: IXP42x A0 silicon detected - "
"PCI Non-Prefetch Workaround Enabled\n"); "PCI Non-Prefetch Workaround Enabled\n");
ixp4xx_pci_read = ixp4xx_pci_read_errata; ixp4xx_pci_read = ixp4xx_pci_read_errata;
......
...@@ -14,18 +14,19 @@ ...@@ -14,18 +14,19 @@
#ifndef __ASM_ARCH_CPU_H__ #ifndef __ASM_ARCH_CPU_H__
#define __ASM_ARCH_CPU_H__ #define __ASM_ARCH_CPU_H__
extern unsigned int processor_id; #include <asm/cputype.h>
/* Processor id value in CP15 Register 0 */ /* Processor id value in CP15 Register 0 */
#define IXP425_PROCESSOR_ID_VALUE 0x690541c0 #define IXP425_PROCESSOR_ID_VALUE 0x690541c0
#define IXP435_PROCESSOR_ID_VALUE 0x69054040 #define IXP435_PROCESSOR_ID_VALUE 0x69054040
#define IXP465_PROCESSOR_ID_VALUE 0x69054200 #define IXP465_PROCESSOR_ID_VALUE 0x69054200
#define IXP4XX_PROCESSOR_ID_MASK 0xfffffff0 #define IXP4XX_PROCESSOR_ID_MASK 0xfffffff0
#define cpu_is_ixp42x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \ #define cpu_is_ixp42x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \
IXP425_PROCESSOR_ID_VALUE) IXP425_PROCESSOR_ID_VALUE)
#define cpu_is_ixp43x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \ #define cpu_is_ixp43x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \
IXP435_PROCESSOR_ID_VALUE) IXP435_PROCESSOR_ID_VALUE)
#define cpu_is_ixp46x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \ #define cpu_is_ixp46x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \
IXP465_PROCESSOR_ID_VALUE) IXP465_PROCESSOR_ID_VALUE)
static inline u32 ixp4xx_read_feature_bits(void) static inline u32 ixp4xx_read_feature_bits(void)
......
...@@ -15,6 +15,7 @@ ...@@ -15,6 +15,7 @@
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/init.h> #include <linux/init.h>
#include <asm/cputype.h>
#include <asm/io.h> #include <asm/io.h>
#include <mach/control.h> #include <mach/control.h>
......
...@@ -62,6 +62,8 @@ ...@@ -62,6 +62,8 @@
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
#include <asm/cputype.h>
#ifdef CONFIG_PXA25x #ifdef CONFIG_PXA25x
#define __cpu_is_pxa21x(id) \ #define __cpu_is_pxa21x(id) \
({ \ ({ \
......
...@@ -88,6 +88,8 @@ ...@@ -88,6 +88,8 @@
#include <linux/init.h> #include <linux/init.h>
#include <linux/cpufreq.h> #include <linux/cpufreq.h>
#include <asm/cputype.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include "generic.h" #include "generic.h"
...@@ -240,7 +242,7 @@ static struct cpufreq_driver sa1100_driver = { ...@@ -240,7 +242,7 @@ static struct cpufreq_driver sa1100_driver = {
static int __init sa1100_dram_init(void) static int __init sa1100_dram_init(void)
{ {
if ((processor_id & CPU_SA1100_MASK) == CPU_SA1100_ID) if (cpu_is_sa1100())
return cpufreq_register_driver(&sa1100_driver); return cpufreq_register_driver(&sa1100_driver);
else else
return -ENODEV; return -ENODEV;
......
...@@ -25,6 +25,7 @@ ...@@ -25,6 +25,7 @@
#include <linux/init.h> #include <linux/init.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include <asm/cputype.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/system.h> #include <asm/system.h>
......
...@@ -2054,19 +2054,3 @@ ...@@ -2054,19 +2054,3 @@
/* active display mode) */ /* active display mode) */
#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */ #define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */
#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */ #define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */
#ifndef __ASSEMBLY__
extern unsigned int processor_id;
#endif
#define CPU_REVISION (processor_id & 15)
#define CPU_SA1110_A0 (0)
#define CPU_SA1110_B0 (4)
#define CPU_SA1110_B1 (5)
#define CPU_SA1110_B2 (6)
#define CPU_SA1110_B4 (8)
#define CPU_SA1100_ID (0x4401a110)
#define CPU_SA1100_MASK (0xfffffff0)
#define CPU_SA1110_ID (0x6901b110)
#define CPU_SA1110_MASK (0xfffffff0)
...@@ -36,8 +36,26 @@ ...@@ -36,8 +36,26 @@
#define io_v2p( x ) \ #define io_v2p( x ) \
( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START ) ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START )
#define CPU_SA1110_A0 (0)
#define CPU_SA1110_B0 (4)
#define CPU_SA1110_B1 (5)
#define CPU_SA1110_B2 (6)
#define CPU_SA1110_B4 (8)
#define CPU_SA1100_ID (0x4401a110)
#define CPU_SA1100_MASK (0xfffffff0)
#define CPU_SA1110_ID (0x6901b110)
#define CPU_SA1110_MASK (0xfffffff0)
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
#include <asm/cputype.h>
#define CPU_REVISION (read_cpuid_id() & 15)
#define cpu_is_sa1100() ((read_cpuid_id() & CPU_SA1100_MASK) == CPU_SA1100_ID)
#define cpu_is_sa1110() ((read_cpuid_id() & CPU_SA1110_MASK) == CPU_SA1110_ID)
# define __REG(x) (*((volatile unsigned long *)io_p2v(x))) # define __REG(x) (*((volatile unsigned long *)io_p2v(x)))
# define __PREG(x) (io_v2p((unsigned long)&(x))) # define __PREG(x) (io_v2p((unsigned long)&(x)))
......
...@@ -18,10 +18,11 @@ ...@@ -18,10 +18,11 @@
*/ */
#include <linux/init.h> #include <linux/init.h>
#include <linux/spinlock.h> #include <linux/spinlock.h>
#include <linux/io.h>
#include <asm/system.h> #include <asm/system.h>
#include <asm/cputype.h>
#include <asm/cacheflush.h> #include <asm/cacheflush.h>
#include <asm/io.h>
#define CR_L2 (1 << 26) #define CR_L2 (1 << 26)
......
...@@ -25,6 +25,7 @@ ...@@ -25,6 +25,7 @@
#include <linux/mm.h> #include <linux/mm.h>
#include <linux/vmalloc.h> #include <linux/vmalloc.h>
#include <asm/cputype.h>
#include <asm/cacheflush.h> #include <asm/cacheflush.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/mmu_context.h> #include <asm/mmu_context.h>
......
...@@ -6,6 +6,7 @@ ...@@ -6,6 +6,7 @@
#include <linux/mman.h> #include <linux/mman.h>
#include <linux/shm.h> #include <linux/shm.h>
#include <linux/sched.h> #include <linux/sched.h>
#include <asm/cputype.h>
#include <asm/system.h> #include <asm/system.h>
#define COLOUR_ALIGN(addr,pgoff) \ #define COLOUR_ALIGN(addr,pgoff) \
...@@ -37,8 +38,8 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr, ...@@ -37,8 +38,8 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,
* caches alias. This is indicated by bits 9 and 21 of the * caches alias. This is indicated by bits 9 and 21 of the
* cache type register. * cache type register.
*/ */
cache_type = read_cpuid(CPUID_CACHETYPE); cache_type = read_cpuid_cachetype();
if (cache_type != read_cpuid(CPUID_ID)) { if (cache_type != read_cpuid_id()) {
aliasing = (cache_type | cache_type >> 12) & (1 << 11); aliasing = (cache_type | cache_type >> 12) & (1 << 11);
if (aliasing) if (aliasing)
do_align = filp || flags & MAP_SHARED; do_align = filp || flags & MAP_SHARED;
......
...@@ -15,6 +15,7 @@ ...@@ -15,6 +15,7 @@
#include <linux/mman.h> #include <linux/mman.h>
#include <linux/nodemask.h> #include <linux/nodemask.h>
#include <asm/cputype.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/setup.h> #include <asm/setup.h>
#include <asm/sizes.h> #include <asm/sizes.h>
......
...@@ -22,7 +22,7 @@ ...@@ -22,7 +22,7 @@
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/irq.h> #include <linux/irq.h>
#include <asm/system.h> #include <asm/cputype.h>
#include "op_counter.h" #include "op_counter.h"
#include "op_arm_model.h" #include "op_arm_model.h"
......
...@@ -174,10 +174,8 @@ static struct miscdevice ixp4xx_wdt_miscdev = { ...@@ -174,10 +174,8 @@ static struct miscdevice ixp4xx_wdt_miscdev = {
static int __init ixp4xx_wdt_init(void) static int __init ixp4xx_wdt_init(void)
{ {
int ret; int ret;
unsigned long processor_id;
asm("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(processor_id) :); if (!(read_cpuid_id() & 0xf) && !cpu_is_ixp46x()) {
if (!(processor_id & 0xf) && !cpu_is_ixp46x()) {
printk(KERN_ERR "IXP4XXX Watchdog: Rev. A0 IXP42x CPU detected" printk(KERN_ERR "IXP4XXX Watchdog: Rev. A0 IXP42x CPU detected"
" - watchdog disabled\n"); " - watchdog disabled\n");
......
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