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Commit 0cc3bd80 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson
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clk: qcom: camcc-sdm845: convert to parent_hws/_data 

Convert the clock driver to specify parent hws/data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names.
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211228045415.20543-11-dmitry.baryshkov@linaro.org
parent b4e2d27e
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Showing with 158 additions and 142 deletions
drivers/clk/qcom/camcc-sdm845.c
View file @ 0cc3bd80
...@@ -31,7 +31,9 @@ static struct clk_alpha_pll cam_cc_pll0 = { ...@@ -31,7 +31,9 @@ static struct clk_alpha_pll cam_cc_pll0 = {
.clkr = { .clkr = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_pll0", .name = "cam_cc_pll0",
.parent_names = (const char *[]){ "bi_tcxo" }, .parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo", .name = "bi_tcxo",
},
.num_parents = 1, .num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops, .ops = &clk_alpha_pll_fabia_ops,
}, },
...@@ -53,7 +55,9 @@ static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { ...@@ -53,7 +55,9 @@ static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll0_out_even", .name = "cam_cc_pll0_out_even",
.parent_names = (const char *[]){ "cam_cc_pll0" }, .parent_hws = (const struct clk_hw*[]){
&cam_cc_pll0.clkr.hw,
},
.num_parents = 1, .num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops, .ops = &clk_alpha_pll_postdiv_fabia_ops,
}, },
...@@ -65,7 +69,9 @@ static struct clk_alpha_pll cam_cc_pll1 = { ...@@ -65,7 +69,9 @@ static struct clk_alpha_pll cam_cc_pll1 = {
.clkr = { .clkr = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_pll1", .name = "cam_cc_pll1",
.parent_names = (const char *[]){ "bi_tcxo" }, .parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo", .name = "bi_tcxo",
},
.num_parents = 1, .num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops, .ops = &clk_alpha_pll_fabia_ops,
}, },
...@@ -81,7 +87,9 @@ static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { ...@@ -81,7 +87,9 @@ static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll1_out_even", .name = "cam_cc_pll1_out_even",
.parent_names = (const char *[]){ "cam_cc_pll1" }, .parent_hws = (const struct clk_hw*[]){
&cam_cc_pll1.clkr.hw,
},
.num_parents = 1, .num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops, .ops = &clk_alpha_pll_postdiv_fabia_ops,
}, },
...@@ -93,7 +101,9 @@ static struct clk_alpha_pll cam_cc_pll2 = { ...@@ -93,7 +101,9 @@ static struct clk_alpha_pll cam_cc_pll2 = {
.clkr = { .clkr = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_pll2", .name = "cam_cc_pll2",
.parent_names = (const char *[]){ "bi_tcxo" }, .parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo", .name = "bi_tcxo",
},
.num_parents = 1, .num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops, .ops = &clk_alpha_pll_fabia_ops,
}, },
...@@ -109,7 +119,9 @@ static struct clk_alpha_pll_postdiv cam_cc_pll2_out_even = { ...@@ -109,7 +119,9 @@ static struct clk_alpha_pll_postdiv cam_cc_pll2_out_even = {
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll2_out_even", .name = "cam_cc_pll2_out_even",
.parent_names = (const char *[]){ "cam_cc_pll2" }, .parent_hws = (const struct clk_hw*[]){
&cam_cc_pll2.clkr.hw,
},
.num_parents = 1, .num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops, .ops = &clk_alpha_pll_postdiv_fabia_ops,
}, },
...@@ -121,7 +133,9 @@ static struct clk_alpha_pll cam_cc_pll3 = { ...@@ -121,7 +133,9 @@ static struct clk_alpha_pll cam_cc_pll3 = {
.clkr = { .clkr = {
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_pll3", .name = "cam_cc_pll3",
.parent_names = (const char *[]){ "bi_tcxo" }, .parent_data = &(const struct clk_parent_data){
.fw_name = "bi_tcxo", .name = "bi_tcxo",
},
.num_parents = 1, .num_parents = 1,
.ops = &clk_alpha_pll_fabia_ops, .ops = &clk_alpha_pll_fabia_ops,
}, },
...@@ -137,7 +151,9 @@ static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { ...@@ -137,7 +151,9 @@ static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA], .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_pll3_out_even", .name = "cam_cc_pll3_out_even",
.parent_names = (const char *[]){ "cam_cc_pll3" }, .parent_hws = (const struct clk_hw*[]){
&cam_cc_pll3.clkr.hw,
},
.num_parents = 1, .num_parents = 1,
.ops = &clk_alpha_pll_postdiv_fabia_ops, .ops = &clk_alpha_pll_postdiv_fabia_ops,
}, },
...@@ -151,12 +167,12 @@ static const struct parent_map cam_cc_parent_map_0[] = { ...@@ -151,12 +167,12 @@ static const struct parent_map cam_cc_parent_map_0[] = {
{ P_CAM_CC_PLL0_OUT_EVEN, 6 }, { P_CAM_CC_PLL0_OUT_EVEN, 6 },
}; };
static const char * const cam_cc_parent_names_0[] = { static const struct clk_parent_data cam_cc_parent_data_0[] = {
"bi_tcxo", { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
"cam_cc_pll2_out_even", { .hw = &cam_cc_pll2_out_even.clkr.hw },
"cam_cc_pll1_out_even", { .hw = &cam_cc_pll1_out_even.clkr.hw },
"cam_cc_pll3_out_even", { .hw = &cam_cc_pll3_out_even.clkr.hw },
"cam_cc_pll0_out_even", { .hw = &cam_cc_pll0_out_even.clkr.hw },
}; };
static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
...@@ -186,8 +202,8 @@ static struct clk_rcg2 cam_cc_bps_clk_src = { ...@@ -186,8 +202,8 @@ static struct clk_rcg2 cam_cc_bps_clk_src = {
.freq_tbl = ftbl_cam_cc_bps_clk_src, .freq_tbl = ftbl_cam_cc_bps_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_clk_src", .name = "cam_cc_bps_clk_src",
.parent_names = cam_cc_parent_names_0, .parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops, .ops = &clk_rcg2_shared_ops,
}, },
...@@ -209,8 +225,8 @@ static struct clk_rcg2 cam_cc_cci_clk_src = { ...@@ -209,8 +225,8 @@ static struct clk_rcg2 cam_cc_cci_clk_src = {
.freq_tbl = ftbl_cam_cc_cci_clk_src, .freq_tbl = ftbl_cam_cc_cci_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_cci_clk_src", .name = "cam_cc_cci_clk_src",
.parent_names = cam_cc_parent_names_0, .parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -229,8 +245,8 @@ static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { ...@@ -229,8 +245,8 @@ static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_cphy_rx_clk_src", .name = "cam_cc_cphy_rx_clk_src",
.parent_names = cam_cc_parent_names_0, .parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -250,8 +266,8 @@ static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { ...@@ -250,8 +266,8 @@ static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi0phytimer_clk_src", .name = "cam_cc_csi0phytimer_clk_src",
.parent_names = cam_cc_parent_names_0, .parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -265,8 +281,8 @@ static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { ...@@ -265,8 +281,8 @@ static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi1phytimer_clk_src", .name = "cam_cc_csi1phytimer_clk_src",
.parent_names = cam_cc_parent_names_0, .parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -280,8 +296,8 @@ static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { ...@@ -280,8 +296,8 @@ static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi2phytimer_clk_src", .name = "cam_cc_csi2phytimer_clk_src",
.parent_names = cam_cc_parent_names_0, .parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -295,8 +311,8 @@ static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { ...@@ -295,8 +311,8 @@ static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_csi3phytimer_clk_src", .name = "cam_cc_csi3phytimer_clk_src",
.parent_names = cam_cc_parent_names_0, .parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -320,8 +336,8 @@ static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { ...@@ -320,8 +336,8 @@ static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
.freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_fast_ahb_clk_src", .name = "cam_cc_fast_ahb_clk_src",
.parent_names = cam_cc_parent_names_0, .parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
}; };
...@@ -343,8 +359,8 @@ static struct clk_rcg2 cam_cc_fd_core_clk_src = { ...@@ -343,8 +359,8 @@ static struct clk_rcg2 cam_cc_fd_core_clk_src = {
.freq_tbl = ftbl_cam_cc_fd_core_clk_src, .freq_tbl = ftbl_cam_cc_fd_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_fd_core_clk_src", .name = "cam_cc_fd_core_clk_src",
.parent_names = cam_cc_parent_names_0, .parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops, .ops = &clk_rcg2_shared_ops,
}, },
}; };
...@@ -366,8 +382,8 @@ static struct clk_rcg2 cam_cc_icp_clk_src = { ...@@ -366,8 +382,8 @@ static struct clk_rcg2 cam_cc_icp_clk_src = {
.freq_tbl = ftbl_cam_cc_icp_clk_src, .freq_tbl = ftbl_cam_cc_icp_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_icp_clk_src", .name = "cam_cc_icp_clk_src",
.parent_names = cam_cc_parent_names_0, .parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops, .ops = &clk_rcg2_shared_ops,
}, },
}; };
...@@ -390,8 +406,8 @@ static struct clk_rcg2 cam_cc_ife_0_clk_src = { ...@@ -390,8 +406,8 @@ static struct clk_rcg2 cam_cc_ife_0_clk_src = {
.freq_tbl = ftbl_cam_cc_ife_0_clk_src, .freq_tbl = ftbl_cam_cc_ife_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_clk_src", .name = "cam_cc_ife_0_clk_src",
.parent_names = cam_cc_parent_names_0, .parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops, .ops = &clk_rcg2_shared_ops,
}, },
...@@ -413,8 +429,8 @@ static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = { ...@@ -413,8 +429,8 @@ static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = {
.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_csid_clk_src", .name = "cam_cc_ife_0_csid_clk_src",
.parent_names = cam_cc_parent_names_0, .parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops, .ops = &clk_rcg2_shared_ops,
}, },
}; };
...@@ -427,8 +443,8 @@ static struct clk_rcg2 cam_cc_ife_1_clk_src = { ...@@ -427,8 +443,8 @@ static struct clk_rcg2 cam_cc_ife_1_clk_src = {
.freq_tbl = ftbl_cam_cc_ife_0_clk_src, .freq_tbl = ftbl_cam_cc_ife_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_clk_src", .name = "cam_cc_ife_1_clk_src",
.parent_names = cam_cc_parent_names_0, .parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops, .ops = &clk_rcg2_shared_ops,
}, },
...@@ -442,8 +458,8 @@ static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = { ...@@ -442,8 +458,8 @@ static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = {
.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_csid_clk_src", .name = "cam_cc_ife_1_csid_clk_src",
.parent_names = cam_cc_parent_names_0, .parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops, .ops = &clk_rcg2_shared_ops,
}, },
}; };
...@@ -456,8 +472,8 @@ static struct clk_rcg2 cam_cc_ife_lite_clk_src = { ...@@ -456,8 +472,8 @@ static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
.freq_tbl = ftbl_cam_cc_ife_0_clk_src, .freq_tbl = ftbl_cam_cc_ife_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_clk_src", .name = "cam_cc_ife_lite_clk_src",
.parent_names = cam_cc_parent_names_0, .parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops, .ops = &clk_rcg2_shared_ops,
}, },
...@@ -471,8 +487,8 @@ static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { ...@@ -471,8 +487,8 @@ static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src, .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_csid_clk_src", .name = "cam_cc_ife_lite_csid_clk_src",
.parent_names = cam_cc_parent_names_0, .parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.ops = &clk_rcg2_shared_ops, .ops = &clk_rcg2_shared_ops,
}, },
}; };
...@@ -496,8 +512,8 @@ static struct clk_rcg2 cam_cc_ipe_0_clk_src = { ...@@ -496,8 +512,8 @@ static struct clk_rcg2 cam_cc_ipe_0_clk_src = {
.freq_tbl = ftbl_cam_cc_ipe_0_clk_src, .freq_tbl = ftbl_cam_cc_ipe_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_clk_src", .name = "cam_cc_ipe_0_clk_src",
.parent_names = cam_cc_parent_names_0, .parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops, .ops = &clk_rcg2_shared_ops,
}, },
...@@ -511,8 +527,8 @@ static struct clk_rcg2 cam_cc_ipe_1_clk_src = { ...@@ -511,8 +527,8 @@ static struct clk_rcg2 cam_cc_ipe_1_clk_src = {
.freq_tbl = ftbl_cam_cc_ipe_0_clk_src, .freq_tbl = ftbl_cam_cc_ipe_0_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_1_clk_src", .name = "cam_cc_ipe_1_clk_src",
.parent_names = cam_cc_parent_names_0, .parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops, .ops = &clk_rcg2_shared_ops,
}, },
...@@ -526,8 +542,8 @@ static struct clk_rcg2 cam_cc_jpeg_clk_src = { ...@@ -526,8 +542,8 @@ static struct clk_rcg2 cam_cc_jpeg_clk_src = {
.freq_tbl = ftbl_cam_cc_bps_clk_src, .freq_tbl = ftbl_cam_cc_bps_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_jpeg_clk_src", .name = "cam_cc_jpeg_clk_src",
.parent_names = cam_cc_parent_names_0, .parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops, .ops = &clk_rcg2_shared_ops,
}, },
...@@ -551,8 +567,8 @@ static struct clk_rcg2 cam_cc_lrme_clk_src = { ...@@ -551,8 +567,8 @@ static struct clk_rcg2 cam_cc_lrme_clk_src = {
.freq_tbl = ftbl_cam_cc_lrme_clk_src, .freq_tbl = ftbl_cam_cc_lrme_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_lrme_clk_src", .name = "cam_cc_lrme_clk_src",
.parent_names = cam_cc_parent_names_0, .parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops, .ops = &clk_rcg2_shared_ops,
}, },
...@@ -574,8 +590,8 @@ static struct clk_rcg2 cam_cc_mclk0_clk_src = { ...@@ -574,8 +590,8 @@ static struct clk_rcg2 cam_cc_mclk0_clk_src = {
.freq_tbl = ftbl_cam_cc_mclk0_clk_src, .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk0_clk_src", .name = "cam_cc_mclk0_clk_src",
.parent_names = cam_cc_parent_names_0, .parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -589,8 +605,8 @@ static struct clk_rcg2 cam_cc_mclk1_clk_src = { ...@@ -589,8 +605,8 @@ static struct clk_rcg2 cam_cc_mclk1_clk_src = {
.freq_tbl = ftbl_cam_cc_mclk0_clk_src, .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk1_clk_src", .name = "cam_cc_mclk1_clk_src",
.parent_names = cam_cc_parent_names_0, .parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -604,8 +620,8 @@ static struct clk_rcg2 cam_cc_mclk2_clk_src = { ...@@ -604,8 +620,8 @@ static struct clk_rcg2 cam_cc_mclk2_clk_src = {
.freq_tbl = ftbl_cam_cc_mclk0_clk_src, .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk2_clk_src", .name = "cam_cc_mclk2_clk_src",
.parent_names = cam_cc_parent_names_0, .parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -619,8 +635,8 @@ static struct clk_rcg2 cam_cc_mclk3_clk_src = { ...@@ -619,8 +635,8 @@ static struct clk_rcg2 cam_cc_mclk3_clk_src = {
.freq_tbl = ftbl_cam_cc_mclk0_clk_src, .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk3_clk_src", .name = "cam_cc_mclk3_clk_src",
.parent_names = cam_cc_parent_names_0, .parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -643,8 +659,8 @@ static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { ...@@ -643,8 +659,8 @@ static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
.freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "cam_cc_slow_ahb_clk_src", .name = "cam_cc_slow_ahb_clk_src",
.parent_names = cam_cc_parent_names_0, .parent_data = cam_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_cc_parent_names_0), .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
...@@ -658,8 +674,8 @@ static struct clk_branch cam_cc_bps_ahb_clk = { ...@@ -658,8 +674,8 @@ static struct clk_branch cam_cc_bps_ahb_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_ahb_clk", .name = "cam_cc_bps_ahb_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_slow_ahb_clk_src", &cam_cc_slow_ahb_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -676,8 +692,8 @@ static struct clk_branch cam_cc_bps_areg_clk = { ...@@ -676,8 +692,8 @@ static struct clk_branch cam_cc_bps_areg_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_areg_clk", .name = "cam_cc_bps_areg_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_fast_ahb_clk_src", &cam_cc_fast_ahb_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -707,8 +723,8 @@ static struct clk_branch cam_cc_bps_clk = { ...@@ -707,8 +723,8 @@ static struct clk_branch cam_cc_bps_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_bps_clk", .name = "cam_cc_bps_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_bps_clk_src", &cam_cc_bps_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -751,8 +767,8 @@ static struct clk_branch cam_cc_cci_clk = { ...@@ -751,8 +767,8 @@ static struct clk_branch cam_cc_cci_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_cci_clk", .name = "cam_cc_cci_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_cci_clk_src", &cam_cc_cci_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -769,8 +785,8 @@ static struct clk_branch cam_cc_cpas_ahb_clk = { ...@@ -769,8 +785,8 @@ static struct clk_branch cam_cc_cpas_ahb_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_cpas_ahb_clk", .name = "cam_cc_cpas_ahb_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_slow_ahb_clk_src", &cam_cc_slow_ahb_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -787,8 +803,8 @@ static struct clk_branch cam_cc_csi0phytimer_clk = { ...@@ -787,8 +803,8 @@ static struct clk_branch cam_cc_csi0phytimer_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_csi0phytimer_clk", .name = "cam_cc_csi0phytimer_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_csi0phytimer_clk_src", &cam_cc_csi0phytimer_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -805,8 +821,8 @@ static struct clk_branch cam_cc_csi1phytimer_clk = { ...@@ -805,8 +821,8 @@ static struct clk_branch cam_cc_csi1phytimer_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_csi1phytimer_clk", .name = "cam_cc_csi1phytimer_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_csi1phytimer_clk_src", &cam_cc_csi1phytimer_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -823,8 +839,8 @@ static struct clk_branch cam_cc_csi2phytimer_clk = { ...@@ -823,8 +839,8 @@ static struct clk_branch cam_cc_csi2phytimer_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_csi2phytimer_clk", .name = "cam_cc_csi2phytimer_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_csi2phytimer_clk_src", &cam_cc_csi2phytimer_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -841,8 +857,8 @@ static struct clk_branch cam_cc_csi3phytimer_clk = { ...@@ -841,8 +857,8 @@ static struct clk_branch cam_cc_csi3phytimer_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_csi3phytimer_clk", .name = "cam_cc_csi3phytimer_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_csi3phytimer_clk_src", &cam_cc_csi3phytimer_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -859,8 +875,8 @@ static struct clk_branch cam_cc_csiphy0_clk = { ...@@ -859,8 +875,8 @@ static struct clk_branch cam_cc_csiphy0_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_csiphy0_clk", .name = "cam_cc_csiphy0_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_cphy_rx_clk_src", &cam_cc_cphy_rx_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -877,8 +893,8 @@ static struct clk_branch cam_cc_csiphy1_clk = { ...@@ -877,8 +893,8 @@ static struct clk_branch cam_cc_csiphy1_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_csiphy1_clk", .name = "cam_cc_csiphy1_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_cphy_rx_clk_src", &cam_cc_cphy_rx_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -895,8 +911,8 @@ static struct clk_branch cam_cc_csiphy2_clk = { ...@@ -895,8 +911,8 @@ static struct clk_branch cam_cc_csiphy2_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_csiphy2_clk", .name = "cam_cc_csiphy2_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_cphy_rx_clk_src", &cam_cc_cphy_rx_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -913,8 +929,8 @@ static struct clk_branch cam_cc_csiphy3_clk = { ...@@ -913,8 +929,8 @@ static struct clk_branch cam_cc_csiphy3_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_csiphy3_clk", .name = "cam_cc_csiphy3_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_cphy_rx_clk_src", &cam_cc_cphy_rx_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -931,8 +947,8 @@ static struct clk_branch cam_cc_fd_core_clk = { ...@@ -931,8 +947,8 @@ static struct clk_branch cam_cc_fd_core_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_fd_core_clk", .name = "cam_cc_fd_core_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_fd_core_clk_src", &cam_cc_fd_core_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -949,8 +965,8 @@ static struct clk_branch cam_cc_fd_core_uar_clk = { ...@@ -949,8 +965,8 @@ static struct clk_branch cam_cc_fd_core_uar_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_fd_core_uar_clk", .name = "cam_cc_fd_core_uar_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_fd_core_clk_src", &cam_cc_fd_core_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.ops = &clk_branch2_ops, .ops = &clk_branch2_ops,
...@@ -992,8 +1008,8 @@ static struct clk_branch cam_cc_icp_clk = { ...@@ -992,8 +1008,8 @@ static struct clk_branch cam_cc_icp_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_icp_clk", .name = "cam_cc_icp_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_icp_clk_src", &cam_cc_icp_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1049,8 +1065,8 @@ static struct clk_branch cam_cc_ife_0_clk = { ...@@ -1049,8 +1065,8 @@ static struct clk_branch cam_cc_ife_0_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_clk", .name = "cam_cc_ife_0_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_ife_0_clk_src", &cam_cc_ife_0_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1067,8 +1083,8 @@ static struct clk_branch cam_cc_ife_0_cphy_rx_clk = { ...@@ -1067,8 +1083,8 @@ static struct clk_branch cam_cc_ife_0_cphy_rx_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_cphy_rx_clk", .name = "cam_cc_ife_0_cphy_rx_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_cphy_rx_clk_src", &cam_cc_cphy_rx_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1085,8 +1101,8 @@ static struct clk_branch cam_cc_ife_0_csid_clk = { ...@@ -1085,8 +1101,8 @@ static struct clk_branch cam_cc_ife_0_csid_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_csid_clk", .name = "cam_cc_ife_0_csid_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_ife_0_csid_clk_src", &cam_cc_ife_0_csid_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1103,8 +1119,8 @@ static struct clk_branch cam_cc_ife_0_dsp_clk = { ...@@ -1103,8 +1119,8 @@ static struct clk_branch cam_cc_ife_0_dsp_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_0_dsp_clk", .name = "cam_cc_ife_0_dsp_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_ife_0_clk_src", &cam_cc_ife_0_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.ops = &clk_branch2_ops, .ops = &clk_branch2_ops,
...@@ -1133,8 +1149,8 @@ static struct clk_branch cam_cc_ife_1_clk = { ...@@ -1133,8 +1149,8 @@ static struct clk_branch cam_cc_ife_1_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_clk", .name = "cam_cc_ife_1_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_ife_1_clk_src", &cam_cc_ife_1_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1151,8 +1167,8 @@ static struct clk_branch cam_cc_ife_1_cphy_rx_clk = { ...@@ -1151,8 +1167,8 @@ static struct clk_branch cam_cc_ife_1_cphy_rx_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_cphy_rx_clk", .name = "cam_cc_ife_1_cphy_rx_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_cphy_rx_clk_src", &cam_cc_cphy_rx_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1169,8 +1185,8 @@ static struct clk_branch cam_cc_ife_1_csid_clk = { ...@@ -1169,8 +1185,8 @@ static struct clk_branch cam_cc_ife_1_csid_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_csid_clk", .name = "cam_cc_ife_1_csid_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_ife_1_csid_clk_src", &cam_cc_ife_1_csid_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1187,8 +1203,8 @@ static struct clk_branch cam_cc_ife_1_dsp_clk = { ...@@ -1187,8 +1203,8 @@ static struct clk_branch cam_cc_ife_1_dsp_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_1_dsp_clk", .name = "cam_cc_ife_1_dsp_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_ife_1_clk_src", &cam_cc_ife_1_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.ops = &clk_branch2_ops, .ops = &clk_branch2_ops,
...@@ -1204,8 +1220,8 @@ static struct clk_branch cam_cc_ife_lite_clk = { ...@@ -1204,8 +1220,8 @@ static struct clk_branch cam_cc_ife_lite_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_clk", .name = "cam_cc_ife_lite_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_ife_lite_clk_src", &cam_cc_ife_lite_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1222,8 +1238,8 @@ static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { ...@@ -1222,8 +1238,8 @@ static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_cphy_rx_clk", .name = "cam_cc_ife_lite_cphy_rx_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_cphy_rx_clk_src", &cam_cc_cphy_rx_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1240,8 +1256,8 @@ static struct clk_branch cam_cc_ife_lite_csid_clk = { ...@@ -1240,8 +1256,8 @@ static struct clk_branch cam_cc_ife_lite_csid_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_ife_lite_csid_clk", .name = "cam_cc_ife_lite_csid_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_ife_lite_csid_clk_src", &cam_cc_ife_lite_csid_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1258,8 +1274,8 @@ static struct clk_branch cam_cc_ipe_0_ahb_clk = { ...@@ -1258,8 +1274,8 @@ static struct clk_branch cam_cc_ipe_0_ahb_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_ahb_clk", .name = "cam_cc_ipe_0_ahb_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_slow_ahb_clk_src", &cam_cc_slow_ahb_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1276,8 +1292,8 @@ static struct clk_branch cam_cc_ipe_0_areg_clk = { ...@@ -1276,8 +1292,8 @@ static struct clk_branch cam_cc_ipe_0_areg_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_areg_clk", .name = "cam_cc_ipe_0_areg_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_fast_ahb_clk_src", &cam_cc_fast_ahb_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1307,8 +1323,8 @@ static struct clk_branch cam_cc_ipe_0_clk = { ...@@ -1307,8 +1323,8 @@ static struct clk_branch cam_cc_ipe_0_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_0_clk", .name = "cam_cc_ipe_0_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_ipe_0_clk_src", &cam_cc_ipe_0_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1325,8 +1341,8 @@ static struct clk_branch cam_cc_ipe_1_ahb_clk = { ...@@ -1325,8 +1341,8 @@ static struct clk_branch cam_cc_ipe_1_ahb_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_1_ahb_clk", .name = "cam_cc_ipe_1_ahb_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_slow_ahb_clk_src", &cam_cc_slow_ahb_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1343,8 +1359,8 @@ static struct clk_branch cam_cc_ipe_1_areg_clk = { ...@@ -1343,8 +1359,8 @@ static struct clk_branch cam_cc_ipe_1_areg_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_1_areg_clk", .name = "cam_cc_ipe_1_areg_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_fast_ahb_clk_src", &cam_cc_fast_ahb_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1374,8 +1390,8 @@ static struct clk_branch cam_cc_ipe_1_clk = { ...@@ -1374,8 +1390,8 @@ static struct clk_branch cam_cc_ipe_1_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_ipe_1_clk", .name = "cam_cc_ipe_1_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_ipe_1_clk_src", &cam_cc_ipe_1_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1392,8 +1408,8 @@ static struct clk_branch cam_cc_jpeg_clk = { ...@@ -1392,8 +1408,8 @@ static struct clk_branch cam_cc_jpeg_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_jpeg_clk", .name = "cam_cc_jpeg_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_jpeg_clk_src", &cam_cc_jpeg_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1410,8 +1426,8 @@ static struct clk_branch cam_cc_lrme_clk = { ...@@ -1410,8 +1426,8 @@ static struct clk_branch cam_cc_lrme_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_lrme_clk", .name = "cam_cc_lrme_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_lrme_clk_src", &cam_cc_lrme_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1428,8 +1444,8 @@ static struct clk_branch cam_cc_mclk0_clk = { ...@@ -1428,8 +1444,8 @@ static struct clk_branch cam_cc_mclk0_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk0_clk", .name = "cam_cc_mclk0_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_mclk0_clk_src", &cam_cc_mclk0_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1446,8 +1462,8 @@ static struct clk_branch cam_cc_mclk1_clk = { ...@@ -1446,8 +1462,8 @@ static struct clk_branch cam_cc_mclk1_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk1_clk", .name = "cam_cc_mclk1_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_mclk1_clk_src", &cam_cc_mclk1_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1464,8 +1480,8 @@ static struct clk_branch cam_cc_mclk2_clk = { ...@@ -1464,8 +1480,8 @@ static struct clk_branch cam_cc_mclk2_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk2_clk", .name = "cam_cc_mclk2_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_mclk2_clk_src", &cam_cc_mclk2_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1482,8 +1498,8 @@ static struct clk_branch cam_cc_mclk3_clk = { ...@@ -1482,8 +1498,8 @@ static struct clk_branch cam_cc_mclk3_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "cam_cc_mclk3_clk", .name = "cam_cc_mclk3_clk",
.parent_names = (const char *[]){ .parent_hws = (const struct clk_hw*[]){
"cam_cc_mclk3_clk_src", &cam_cc_mclk3_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
......
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