Commit 0d19e003 authored by Dave Jones's avatar Dave Jones Committed by Dave Jones

[CPUFREQ] powernow-k8 cpuid changes.

cpuid changes to support new processors that will be coming out in the
future. Also works around a processor that we have released to the field
that can have an erroneous cpuid value.

From paul.devriendt@amd.com
parent ad4c196a
...@@ -39,7 +39,7 @@ ...@@ -39,7 +39,7 @@
#define PFX "powernow-k8: " #define PFX "powernow-k8: "
#define BFX PFX "BIOS error: " #define BFX PFX "BIOS error: "
#define VERSION "version 1.00.08b" #define VERSION "version 1.00.09b"
#include "powernow-k8.h" #include "powernow-k8.h"
/* serialize freq changes */ /* serialize freq changes */
...@@ -450,13 +450,10 @@ static int check_supported_cpu(unsigned int cpu) ...@@ -450,13 +450,10 @@ static int check_supported_cpu(unsigned int cpu)
goto out; goto out;
eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE); eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
if ((eax & CPUID_XFAM_MOD) == ATHLON64_XFAM_MOD) { if (((eax & CPUID_USE_XFAM_XMOD) != CPUID_USE_XFAM_XMOD) ||
dprintk(KERN_DEBUG PFX "AMD Althon 64 Processor found\n"); ((eax & CPUID_XFAM) != CPUID_XFAM_K8) ||
} else if ((eax & CPUID_XFAM_MOD) == OPTERON_XFAM_MOD) { ((eax & CPUID_XMOD) > CPUID_XMOD_REV_E)) {
dprintk(KERN_DEBUG PFX "AMD Opteron Processor found\n"); printk(KERN_INFO PFX "Processor cpuid %x not supported\n", eax);
} else {
printk(KERN_INFO PFX
"AMD Athlon 64 or AMD Opteron processor required\n");
goto out; goto out;
} }
......
...@@ -38,13 +38,15 @@ struct powernow_k8_data { ...@@ -38,13 +38,15 @@ struct powernow_k8_data {
/* processor's cpuid instruction support */ /* processor's cpuid instruction support */
#define CPUID_PROCESSOR_SIGNATURE 1 /* function 1 */ #define CPUID_PROCESSOR_SIGNATURE 1 /* function 1 */
#define CPUID_XFAM_MOD 0x0ff00ff0 /* extended fam, fam + model */ #define CPUID_XFAM 0x0ff00000 /* extended family */
#define ATHLON64_XFAM_MOD 0x00000f40 /* extended fam, fam + model */ #define CPUID_XFAM_K8 0
#define OPTERON_XFAM_MOD 0x00000f50 /* extended fam, fam + model */ #define CPUID_XMOD 0x000f0000 /* extended model */
#define CPUID_GET_MAX_CAPABILITIES 0x80000000 #define CPUID_XMOD_REV_E 0x00020000
#define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007 #define CPUID_USE_XFAM_XMOD 0x00000f00
#define P_STATE_TRANSITION_CAPABLE 6 #define CPUID_GET_MAX_CAPABILITIES 0x80000000
#define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007
#define P_STATE_TRANSITION_CAPABLE 6
/* Model Specific Registers for p-state transitions. MSRs are 64-bit. For */ /* Model Specific Registers for p-state transitions. MSRs are 64-bit. For */
/* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */ /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */
......
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