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Commit 0de085bb authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'for_paulus' of master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc 

* 'for_paulus' of master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc: (25 commits)
  [POWERPC] 85xx: Added needed MPC85xx PCI device IDs
  [POWERPC] Add Freescale PCI VENDOR ID and 8641 device IDs
  [POWERPC] 85xxCDS: MPC8548 DTS cleanup.
  [POWERPC] 85xxCDS: Misc 8548 PCI Corrections.
  [POWERPC] 85xxCDS: Delay 8259 cascade hookup.
  [POWERPC] 85xxCDS: Make sure restart resets the PCI bus.
  [POWERPC] 85xxCDS: Allow 8259 cascade to share an MPIC interrupt line.
  [POWERPC] FSL: Add support for PCI-X controllers
  [POWERPC] Make sure virtual P2P bridge registers are setup on PCIe PHB
  [POWERPC] Provide ability to setup P2P bridge registers from struct resource
  [POWERPC] Add basic PCI/PCI Express support for 8544DS board
  [POWERPC] Make endianess of cfg_addr for indirect pci ops runtime
  [POWERPC] Removed setup_indirect_pci_nomap
  [POWERPC] 85xx: Add quirk to ignore bogus FPGA on CDS
  [POWERPC] 85xx: Added 8568 PCIe support
  [POWERPC] Fixup resources on pci_bus for PCIe PHB when no device is connected
  [POWERPC] Add basic PCI node for mpc8568mds board
  [POWERPC] Use Freescale pci/pcie common code for 85xx boards
  [POWERPC] Update PCI nodes in the 83xx/85xx boards device tree
  [POWERPC] Add 8548 CDS PCI express controller node and PCI-X device node
  ...
parents 3836df6b e5871211
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Showing with 1660 additions and 840 deletions
arch/powerpc/Kconfig
View file @ 0de085bb
...@@ -411,11 +411,6 @@ config PPC_INDIRECT_PCI ...@@ -411,11 +411,6 @@ config PPC_INDIRECT_PCI
default y if 40x || 44x default y if 40x || 44x
default n default n
config PPC_INDIRECT_PCI_BE
bool
depends PPC_INDIRECT_PCI
default n
config EISA config EISA
bool bool
...@@ -425,6 +420,10 @@ config SBUS ...@@ -425,6 +420,10 @@ config SBUS
config FSL_SOC config FSL_SOC
bool bool
config FSL_PCI
bool
select PPC_INDIRECT_PCI
# Yes MCA RS/6000s exist but Linux-PPC does not currently support any # Yes MCA RS/6000s exist but Linux-PPC does not currently support any
config MCA config MCA
bool bool
......
arch/powerpc/boot/dts/mpc8313erdb.dts
View file @ 0de085bb
...@@ -178,7 +178,7 @@ pci@8500 { ...@@ -178,7 +178,7 @@ pci@8500 {
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <8500 100>; reg = <8500 100>;
compatible = "83xx"; compatible = "fsl,mpc8349-pci";
device_type = "pci"; device_type = "pci";
}; };
......
arch/powerpc/boot/dts/mpc832x_mds.dts
View file @ 0de085bb
...@@ -154,7 +154,7 @@ c000 0 0 3 &ipic 17 8 ...@@ -154,7 +154,7 @@ c000 0 0 3 &ipic 17 8
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <8500 100>; reg = <8500 100>;
compatible = "83xx"; compatible = "fsl,mpc8349-pci";
device_type = "pci"; device_type = "pci";
}; };
......
arch/powerpc/boot/dts/mpc832x_rdb.dts
View file @ 0de085bb
...@@ -123,7 +123,7 @@ pci@8500 { ...@@ -123,7 +123,7 @@ pci@8500 {
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <8500 100>; reg = <8500 100>;
compatible = "83xx"; compatible = "fsl,mpc8349-pci";
device_type = "pci"; device_type = "pci";
}; };
......
arch/powerpc/boot/dts/mpc8349emitx.dts
View file @ 0de085bb
...@@ -197,7 +197,7 @@ pci@8500 { ...@@ -197,7 +197,7 @@ pci@8500 {
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <8500 100>; reg = <8500 100>;
compatible = "83xx"; compatible = "fsl,mpc8349-pci";
device_type = "pci"; device_type = "pci";
}; };
...@@ -222,7 +222,7 @@ pci@8600 { ...@@ -222,7 +222,7 @@ pci@8600 {
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <8600 100>; reg = <8600 100>;
compatible = "83xx"; compatible = "fsl,mpc8349-pci";
device_type = "pci"; device_type = "pci";
}; };
......
arch/powerpc/boot/dts/mpc8349emitxgp.dts
View file @ 0de085bb
...@@ -154,7 +154,7 @@ pci@8600 { ...@@ -154,7 +154,7 @@ pci@8600 {
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <8600 100>; reg = <8600 100>;
compatible = "83xx"; compatible = "fsl,mpc8349-pci";
device_type = "pci"; device_type = "pci";
}; };
......
arch/powerpc/boot/dts/mpc834x_mds.dts
View file @ 0de085bb
...@@ -241,7 +241,7 @@ c000 0 0 3 &ipic 17 8 ...@@ -241,7 +241,7 @@ c000 0 0 3 &ipic 17 8
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <8500 100>; reg = <8500 100>;
compatible = "83xx"; compatible = "fsl,mpc8349-pci";
device_type = "pci"; device_type = "pci";
}; };
...@@ -301,7 +301,7 @@ c000 0 0 3 &ipic 17 8 ...@@ -301,7 +301,7 @@ c000 0 0 3 &ipic 17 8
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <8600 100>; reg = <8600 100>;
compatible = "83xx"; compatible = "fsl,mpc8349-pci";
device_type = "pci"; device_type = "pci";
}; };
......
arch/powerpc/boot/dts/mpc836x_mds.dts
View file @ 0de085bb
...@@ -169,7 +169,7 @@ c000 0 0 3 &ipic 17 8 ...@@ -169,7 +169,7 @@ c000 0 0 3 &ipic 17 8
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <8500 100>; reg = <8500 100>;
compatible = "83xx"; compatible = "fsl,mpc8349-pci";
device_type = "pci"; device_type = "pci";
}; };
......
arch/powerpc/boot/dts/mpc8540ads.dts
View file @ 0de085bb
...@@ -258,7 +258,7 @@ a800 0 0 3 &mpic 4 1 ...@@ -258,7 +258,7 @@ a800 0 0 3 &mpic 4 1
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <8000 1000>; reg = <8000 1000>;
compatible = "85xx"; compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci"; device_type = "pci";
}; };
......
arch/powerpc/boot/dts/mpc8541cds.dts
View file @ 0de085bb
...@@ -193,7 +193,7 @@ pci1: pci@8000 { ...@@ -193,7 +193,7 @@ pci1: pci@8000 {
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <8000 1000>; reg = <8000 1000>;
compatible = "85xx"; compatible = "fsl,mpc8540-pci";
device_type = "pci"; device_type = "pci";
i8259@19000 { i8259@19000 {
...@@ -230,7 +230,7 @@ a800 0 0 3 &mpic b 1 ...@@ -230,7 +230,7 @@ a800 0 0 3 &mpic b 1
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <9000 1000>; reg = <9000 1000>;
compatible = "85xx"; compatible = "fsl,mpc8540-pci";
device_type = "pci"; device_type = "pci";
}; };
......
arch/powerpc/boot/dts/mpc8544ds.dts
View file @ 0de085bb
...@@ -137,6 +137,217 @@ serial@4600 { ...@@ -137,6 +137,217 @@ serial@4600 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
}; };
pci@8000 {
compatible = "fsl,mpc8540-pci";
device_type = "pci";
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x11 J17 Slot 1 */
8800 0 0 1 &mpic 2 1
8800 0 0 2 &mpic 3 1
8800 0 0 3 &mpic 4 1
8800 0 0 4 &mpic 1 1
/* IDSEL 0x12 J16 Slot 2 */
9000 0 0 1 &mpic 3 1
9000 0 0 2 &mpic 4 1
9000 0 0 3 &mpic 2 1
9000 0 0 4 &mpic 1 1>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
bus-range = <0 ff>;
ranges = <02000000 0 80000000 80000000 0 10000000
01000000 0 00000000 e2000000 0 00800000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8000 1000>;
};
pcie@9000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <9000 1000>;
bus-range = <0 ff>;
ranges = <02000000 0 90000000 90000000 0 10000000
01000000 0 00000000 e3000000 0 00800000>;
clock-frequency = <1fca055>;
interrupt-parent = <&mpic>;
interrupts = <1a 2>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 4 1
0000 0 0 2 &mpic 5 1
0000 0 0 3 &mpic 6 1
0000 0 0 4 &mpic 7 1
>;
};
pcie@a000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <a000 1000>;
bus-range = <0 ff>;
ranges = <02000000 0 a0000000 a0000000 0 10000000
01000000 0 00000000 e2800000 0 00800000>;
clock-frequency = <1fca055>;
interrupt-parent = <&mpic>;
interrupts = <19 2>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 */
0000 0 0 1 &mpic 0 1
0000 0 0 2 &mpic 1 1
0000 0 0 3 &mpic 2 1
0000 0 0 4 &mpic 3 1
>;
};
pcie@b000 {
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <b000 1000>;
bus-range = <0 ff>;
ranges = <02000000 0 b0000000 b0000000 0 10000000
01000000 0 00000000 e3800000 0 00800000>;
clock-frequency = <1fca055>;
interrupt-parent = <&mpic>;
interrupts = <1b 2>;
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
// IDSEL 0x1a
d000 0 0 1 &i8259 6 2
d000 0 0 2 &i8259 3 2
d000 0 0 3 &i8259 4 2
d000 0 0 4 &i8259 5 2
// IDSEL 0x1b
d800 0 0 1 &i8259 5 2
d800 0 0 2 &i8259 0 0
d800 0 0 3 &i8259 0 0
d800 0 0 4 &i8259 0 0
// IDSEL 0x1c USB
e000 0 0 1 &i8259 9 2
e000 0 0 2 &i8259 a 2
e000 0 0 3 &i8259 c 2
e000 0 0 4 &i8259 7 2
// IDSEL 0x1d Audio
e800 0 0 1 &i8259 9 2
e800 0 0 2 &i8259 a 2
e800 0 0 3 &i8259 b 2
e800 0 0 4 &i8259 0 0
// IDSEL 0x1e Legacy
f000 0 0 1 &i8259 c 2
f000 0 0 2 &i8259 0 0
f000 0 0 3 &i8259 0 0
f000 0 0 4 &i8259 0 0
// IDSEL 0x1f IDE/SATA
f800 0 0 1 &i8259 6 2
f800 0 0 2 &i8259 0 0
f800 0 0 3 &i8259 0 0
f800 0 0 4 &i8259 0 0
>;
uli1575@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
ranges = <02000000 0 b0000000
02000000 0 b0000000
0 10000000
01000000 0 00000000
01000000 0 00000000
0 00080000>;
pci_bridge@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
ranges = <02000000 0 b0000000
02000000 0 b0000000
0 20000000
01000000 0 00000000
01000000 0 00000000
0 00100000>;
isa@1e {
device_type = "isa";
#interrupt-cells = <2>;
#size-cells = <1>;
#address-cells = <2>;
reg = <f000 0 0 0 0>;
ranges = <1 0 01000000 0 0
00001000>;
interrupt-parent = <&i8259>;
i8259: interrupt-controller@20 {
reg = <1 20 2
1 a0 2
1 4d0 2>;
clock-frequency = <0>;
interrupt-controller;
device_type = "interrupt-controller";
#address-cells = <0>;
#interrupt-cells = <2>;
built-in;
compatible = "chrp,iic";
interrupts = <9 2>;
interrupt-parent =
<&mpic>;
};
i8042@60 {
#size-cells = <0>;
#address-cells = <1>;
reg = <1 60 1 1 64 1>;
interrupts = <1 3 c 3>;
interrupt-parent =
<&i8259>;
keyboard@0 {
reg = <0>;
compatible = "pnpPNP,303";
};
mouse@1 {
reg = <1>;
compatible = "pnpPNP,f03";
};
};
rtc@70 {
compatible =
"pnpPNP,b00";
reg = <1 70 2>;
};
gpio@400 {
reg = <1 400 80>;
};
};
};
};
};
mpic: pic@40000 { mpic: pic@40000 {
clock-frequency = <0>; clock-frequency = <0>;
interrupt-controller; interrupt-controller;
......
arch/powerpc/boot/dts/mpc8548cds.dts
View file @ 0de085bb
/* /*
* MPC8555 CDS Device Tree Source * MPC8548 CDS Device Tree Source
* *
* Copyright 2006 Freescale Semiconductor Inc. * Copyright 2006 Freescale Semiconductor Inc.
* *
...@@ -44,8 +44,14 @@ soc8548@e0000000 { ...@@ -44,8 +44,14 @@ soc8548@e0000000 {
#size-cells = <1>; #size-cells = <1>;
#interrupt-cells = <2>; #interrupt-cells = <2>;
device_type = "soc"; device_type = "soc";
ranges = <0 e0000000 00100000>; ranges = <00001000 e0001000 000ff000
reg = <e0000000 00100000>; // CCSRBAR 1M 80000000 80000000 10000000
e2000000 e2000000 00800000
90000000 90000000 10000000
e2800000 e2800000 00800000
a0000000 a0000000 20000000
e3000000 e3000000 01000000>;
reg = <e0000000 00001000>; // CCSRBAR
bus-frequency = <0>; bus-frequency = <0>;
memory-controller@2000 { memory-controller@2000 {
...@@ -162,8 +168,8 @@ ethernet@27000 { ...@@ -162,8 +168,8 @@ ethernet@27000 {
serial@4500 { serial@4500 {
device_type = "serial"; device_type = "serial";
compatible = "ns16550"; compatible = "ns16550";
reg = <4500 100>; // reg base, size reg = <4500 100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot? clock-frequency = <0>; // should we fill in in uboot?
interrupts = <2a 2>; interrupts = <2a 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
}; };
...@@ -172,7 +178,7 @@ serial@4600 { ...@@ -172,7 +178,7 @@ serial@4600 {
device_type = "serial"; device_type = "serial";
compatible = "ns16550"; compatible = "ns16550";
reg = <4600 100>; // reg base, size reg = <4600 100>; // reg base, size
clock-frequency = <0>; // should we fill in in uboot? clock-frequency = <0>; // should we fill in in uboot?
interrupts = <2a 2>; interrupts = <2a 2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
}; };
...@@ -183,77 +189,154 @@ global-utilities@e0000 { //global utilities reg ...@@ -183,77 +189,154 @@ global-utilities@e0000 { //global utilities reg
fsl,has-rstcr; fsl,has-rstcr;
}; };
pci1: pci@8000 { pci@8000 {
interrupt-map-mask = <1f800 0 0 7>; interrupt-map-mask = <f800 0 0 7>;
interrupt-map = < interrupt-map = <
/* IDSEL 0x4 (PCIX Slot 2) */
02000 0 0 1 &mpic 0 1
02000 0 0 2 &mpic 1 1
02000 0 0 3 &mpic 2 1
02000 0 0 4 &mpic 3 1
/* IDSEL 0x5 (PCIX Slot 3) */
02800 0 0 1 &mpic 1 1
02800 0 0 2 &mpic 2 1
02800 0 0 3 &mpic 3 1
02800 0 0 4 &mpic 0 1
/* IDSEL 0x6 (PCIX Slot 4) */
03000 0 0 1 &mpic 2 1
03000 0 0 2 &mpic 3 1
03000 0 0 3 &mpic 0 1
03000 0 0 4 &mpic 1 1
/* IDSEL 0x8 (PCIX Slot 5) */
04000 0 0 1 &mpic 0 1
04000 0 0 2 &mpic 1 1
04000 0 0 3 &mpic 2 1
04000 0 0 4 &mpic 3 1
/* IDSEL 0xC (Tsi310 bridge) */
06000 0 0 1 &mpic 0 1
06000 0 0 2 &mpic 1 1
06000 0 0 3 &mpic 2 1
06000 0 0 4 &mpic 3 1
/* IDSEL 0x14 (Slot 2) */
0a000 0 0 1 &mpic 0 1
0a000 0 0 2 &mpic 1 1
0a000 0 0 3 &mpic 2 1
0a000 0 0 4 &mpic 3 1
/* IDSEL 0x15 (Slot 3) */
0a800 0 0 1 &mpic 1 1
0a800 0 0 2 &mpic 2 1
0a800 0 0 3 &mpic 3 1
0a800 0 0 4 &mpic 0 1
/* IDSEL 0x16 (Slot 4) */
0b000 0 0 1 &mpic 2 1
0b000 0 0 2 &mpic 3 1
0b000 0 0 3 &mpic 0 1
0b000 0 0 4 &mpic 1 1
/* IDSEL 0x18 (Slot 5) */
0c000 0 0 1 &mpic 0 1
0c000 0 0 2 &mpic 1 1
0c000 0 0 3 &mpic 2 1
0c000 0 0 4 &mpic 3 1
/* IDSEL 0x1C (Tsi310 bridge PCI primary) */
0E000 0 0 1 &mpic 0 1
0E000 0 0 2 &mpic 1 1
0E000 0 0 3 &mpic 2 1
0E000 0 0 4 &mpic 3 1>;
/* IDSEL 0x10 */
08000 0 0 1 &mpic 0 1
08000 0 0 2 &mpic 1 1
08000 0 0 3 &mpic 2 1
08000 0 0 4 &mpic 3 1
/* IDSEL 0x11 */
08800 0 0 1 &mpic 0 1
08800 0 0 2 &mpic 1 1
08800 0 0 3 &mpic 2 1
08800 0 0 4 &mpic 3 1
/* IDSEL 0x12 (Slot 1) */
09000 0 0 1 &mpic 0 1
09000 0 0 2 &mpic 1 1
09000 0 0 3 &mpic 2 1
09000 0 0 4 &mpic 3 1
/* IDSEL 0x13 (Slot 2) */
09800 0 0 1 &mpic 1 1
09800 0 0 2 &mpic 2 1
09800 0 0 3 &mpic 3 1
09800 0 0 4 &mpic 0 1
/* IDSEL 0x14 (Slot 3) */
0a000 0 0 1 &mpic 2 1
0a000 0 0 2 &mpic 3 1
0a000 0 0 3 &mpic 0 1
0a000 0 0 4 &mpic 1 1
/* IDSEL 0x15 (Slot 4) */
0a800 0 0 1 &mpic 3 1
0a800 0 0 2 &mpic 0 1
0a800 0 0 3 &mpic 1 1
0a800 0 0 4 &mpic 2 1
/* Bus 1 (Tundra Bridge) */
/* IDSEL 0x12 (ISA bridge) */
19000 0 0 1 &mpic 0 1
19000 0 0 2 &mpic 1 1
19000 0 0 3 &mpic 2 1
19000 0 0 4 &mpic 3 1>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <18 2>; interrupts = <18 2>;
bus-range = <0 0>; bus-range = <0 0>;
ranges = <02000000 0 80000000 80000000 0 20000000 ranges = <02000000 0 80000000 80000000 0 10000000
01000000 0 00000000 e2000000 0 00100000>; 01000000 0 00000000 e2000000 0 00800000>;
clock-frequency = <3f940aa>; clock-frequency = <3f940aa>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <8000 1000>; reg = <8000 1000>;
compatible = "85xx"; compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci"; device_type = "pci";
i8259@19000 { pci_bridge@1c {
clock-frequency = <0>; interrupt-map-mask = <f800 0 0 7>;
interrupt-controller; interrupt-map = <
device_type = "interrupt-controller";
reg = <19000 0 0 0 1>; /* IDSEL 0x00 (PrPMC Site) */
#address-cells = <0>; 0000 0 0 1 &mpic 0 1
#interrupt-cells = <2>; 0000 0 0 2 &mpic 1 1
built-in; 0000 0 0 3 &mpic 2 1
compatible = "chrp,iic"; 0000 0 0 4 &mpic 3 1
big-endian;
interrupts = <1>; /* IDSEL 0x04 (VIA chip) */
interrupt-parent = <&pci1>; 2000 0 0 1 &mpic 0 1
2000 0 0 2 &mpic 1 1
2000 0 0 3 &mpic 2 1
2000 0 0 4 &mpic 3 1
/* IDSEL 0x05 (8139) */
2800 0 0 1 &mpic 1 1
/* IDSEL 0x06 (Slot 6) */
3000 0 0 1 &mpic 2 1
3000 0 0 2 &mpic 3 1
3000 0 0 3 &mpic 0 1
3000 0 0 4 &mpic 1 1
/* IDESL 0x07 (Slot 7) */
3800 0 0 1 &mpic 3 1
3800 0 0 2 &mpic 0 1
3800 0 0 3 &mpic 1 1
3800 0 0 4 &mpic 2 1>;
reg = <e000 0 0 0 0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
ranges = <02000000 0 80000000
02000000 0 80000000
0 20000000
01000000 0 00000000
01000000 0 00000000
0 00080000>;
clock-frequency = <1fca055>;
isa@4 {
device_type = "isa";
#interrupt-cells = <2>;
#size-cells = <1>;
#address-cells = <2>;
reg = <2000 0 0 0 0>;
ranges = <1 0 01000000 0 0 00001000>;
interrupt-parent = <&i8259>;
i8259: interrupt-controller@20 {
clock-frequency = <0>;
interrupt-controller;
device_type = "interrupt-controller";
reg = <1 20 2
1 a0 2
1 4d0 2>;
#address-cells = <0>;
#interrupt-cells = <2>;
built-in;
compatible = "chrp,iic";
interrupts = <0 1>;
interrupt-parent = <&mpic>;
};
rtc@70 {
compatible = "pnpPNP,b00";
reg = <1 70 2>;
};
};
}; };
}; };
...@@ -263,20 +346,45 @@ pci@9000 { ...@@ -263,20 +346,45 @@ pci@9000 {
/* IDSEL 0x15 */ /* IDSEL 0x15 */
a800 0 0 1 &mpic b 1 a800 0 0 1 &mpic b 1
a800 0 0 2 &mpic b 1 a800 0 0 2 &mpic 1 1
a800 0 0 3 &mpic b 1 a800 0 0 3 &mpic 2 1
a800 0 0 4 &mpic b 1>; a800 0 0 4 &mpic 3 1>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <19 2>; interrupts = <19 2>;
bus-range = <0 0>; bus-range = <0 0>;
ranges = <02000000 0 a0000000 a0000000 0 20000000 ranges = <02000000 0 90000000 90000000 0 10000000
01000000 0 00000000 e3000000 0 00100000>; 01000000 0 00000000 e2800000 0 00800000>;
clock-frequency = <3f940aa>; clock-frequency = <3f940aa>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <9000 1000>; reg = <9000 1000>;
compatible = "85xx"; compatible = "fsl,mpc8540-pci";
device_type = "pci";
};
/* PCI Express */
pcie@a000 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 (PEX) */
00000 0 0 1 &mpic 0 1
00000 0 0 2 &mpic 1 1
00000 0 0 3 &mpic 2 1
00000 0 0 4 &mpic 3 1>;
interrupt-parent = <&mpic>;
interrupts = <1a 2>;
bus-range = <0 ff>;
ranges = <02000000 0 a0000000 a0000000 0 20000000
01000000 0 00000000 e3000000 0 08000000>;
clock-frequency = <1fca055>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <a000 1000>;
compatible = "fsl,mpc8548-pcie";
device_type = "pci"; device_type = "pci";
}; };
......
arch/powerpc/boot/dts/mpc8555cds.dts
View file @ 0de085bb
...@@ -193,7 +193,7 @@ pci1: pci@8000 { ...@@ -193,7 +193,7 @@ pci1: pci@8000 {
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <8000 1000>; reg = <8000 1000>;
compatible = "85xx"; compatible = "fsl,mpc8540-pci";
device_type = "pci"; device_type = "pci";
i8259@19000 { i8259@19000 {
...@@ -230,7 +230,7 @@ a800 0 0 3 &mpic b 1 ...@@ -230,7 +230,7 @@ a800 0 0 3 &mpic b 1
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
reg = <9000 1000>; reg = <9000 1000>;
compatible = "85xx"; compatible = "fsl,mpc8540-pci";
device_type = "pci"; device_type = "pci";
}; };
......
arch/powerpc/boot/dts/mpc8560ads.dts
View file @ 0de085bb
...@@ -136,7 +136,7 @@ pci@8000 { ...@@ -136,7 +136,7 @@ pci@8000 {
#interrupt-cells = <1>; #interrupt-cells = <1>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
compatible = "85xx"; compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
device_type = "pci"; device_type = "pci";
reg = <8000 1000>; reg = <8000 1000>;
clock-frequency = <3f940aa>; clock-frequency = <3f940aa>;
......
arch/powerpc/boot/dts/mpc8568mds.dts
View file @ 0de085bb
...@@ -170,6 +170,60 @@ serial@4500 { ...@@ -170,6 +170,60 @@ serial@4500 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
}; };
pci@8000 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x12 AD18 */
9000 0 0 1 &mpic 5 1
9000 0 0 2 &mpic 6 1
9000 0 0 3 &mpic 7 1
9000 0 0 4 &mpic 4 1
/* IDSEL 0x13 AD19 */
9800 0 0 1 &mpic 6 1
9800 0 0 2 &mpic 7 1
9800 0 0 3 &mpic 4 1
9800 0 0 4 &mpic 5 1>;
interrupt-parent = <&mpic>;
interrupts = <18 2>;
bus-range = <0 ff>;
ranges = <02000000 0 80000000 80000000 0 20000000
01000000 0 00000000 e2000000 0 00800000>;
clock-frequency = <3f940aa>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <8000 1000>;
compatible = "fsl,mpc8540-pci";
device_type = "pci";
};
/* PCI Express */
pcie@a000 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
/* IDSEL 0x0 (PEX) */
00000 0 0 1 &mpic 0 1
00000 0 0 2 &mpic 1 1
00000 0 0 3 &mpic 2 1
00000 0 0 4 &mpic 3 1>;
interrupt-parent = <&mpic>;
interrupts = <1a 2>;
bus-range = <0 ff>;
ranges = <02000000 0 a0000000 a0000000 0 20000000
01000000 0 00000000 e3000000 0 08000000>;
clock-frequency = <1fca055>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <a000 1000>;
compatible = "fsl,mpc8548-pcie";
device_type = "pci";
};
serial@4600 { serial@4600 {
device_type = "serial"; device_type = "serial";
compatible = "ns16550"; compatible = "ns16550";
......
arch/powerpc/boot/dts/mpc8641_hpcn.dts
View file @ 0de085bb
...@@ -211,8 +211,8 @@ serial@4600 { ...@@ -211,8 +211,8 @@ serial@4600 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
}; };
pci@8000 { pcie@8000 {
compatible = "86xx"; compatible = "fsl,mpc8641-pcie";
device_type = "pci"; device_type = "pci";
#interrupt-cells = <1>; #interrupt-cells = <1>;
#size-cells = <2>; #size-cells = <2>;
...@@ -399,8 +399,8 @@ gpio@400 { ...@@ -399,8 +399,8 @@ gpio@400 {
}; };
pci@9000 { pcie@9000 {
compatible = "86xx"; compatible = "fsl,mpc8641-pcie";
device_type = "pci"; device_type = "pci";
#interrupt-cells = <1>; #interrupt-cells = <1>;
#size-cells = <2>; #size-cells = <2>;
......
arch/powerpc/configs/mpc8544_ds_defconfig
View file @ 0de085bb
This diff is collapsed.
arch/powerpc/configs/mpc8568mds_defconfig
View file @ 0de085bb
This diff is collapsed.
arch/powerpc/kernel/pci_32.c
View file @ 0de085bb
...@@ -415,15 +415,13 @@ probe_resource(struct pci_bus *parent, struct resource *pr, ...@@ -415,15 +415,13 @@ probe_resource(struct pci_bus *parent, struct resource *pr,
return 0; return 0;
} }
static void __init void __init
update_bridge_base(struct pci_bus *bus, int i) update_bridge_resource(struct pci_dev *dev, struct resource *res)
{ {
struct resource *res = bus->resource[i];
u8 io_base_lo, io_limit_lo; u8 io_base_lo, io_limit_lo;
u16 mem_base, mem_limit; u16 mem_base, mem_limit;
u16 cmd; u16 cmd;
unsigned long start, end, off; unsigned long start, end, off;
struct pci_dev *dev = bus->self;
struct pci_controller *hose = dev->sysdata; struct pci_controller *hose = dev->sysdata;
if (!hose) { if (!hose) {
...@@ -467,12 +465,20 @@ update_bridge_base(struct pci_bus *bus, int i) ...@@ -467,12 +465,20 @@ update_bridge_base(struct pci_bus *bus, int i)
pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit); pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, mem_limit);
} else { } else {
DBG(KERN_ERR "PCI: ugh, bridge %s res %d has flags=%lx\n", DBG(KERN_ERR "PCI: ugh, bridge %s res has flags=%lx\n",
pci_name(dev), i, res->flags); pci_name(dev), res->flags);
} }
pci_write_config_word(dev, PCI_COMMAND, cmd); pci_write_config_word(dev, PCI_COMMAND, cmd);
} }
static void __init
update_bridge_base(struct pci_bus *bus, int i)
{
struct resource *res = bus->resource[i];
struct pci_dev *dev = bus->self;
update_bridge_resource(dev, res);
}
static inline void alloc_resource(struct pci_dev *dev, int idx) static inline void alloc_resource(struct pci_dev *dev, int idx)
{ {
struct resource *pr, *r = &dev->resource[idx]; struct resource *pr, *r = &dev->resource[idx];
...@@ -1468,3 +1474,10 @@ EARLY_PCI_OP(read, dword, u32 *) ...@@ -1468,3 +1474,10 @@ EARLY_PCI_OP(read, dword, u32 *)
EARLY_PCI_OP(write, byte, u8) EARLY_PCI_OP(write, byte, u8)
EARLY_PCI_OP(write, word, u16) EARLY_PCI_OP(write, word, u16)
EARLY_PCI_OP(write, dword, u32) EARLY_PCI_OP(write, dword, u32)
extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap);
int early_find_capability(struct pci_controller *hose, int bus, int devfn,
int cap)
{
return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
}
arch/powerpc/platforms/82xx/mpc82xx_ads.c
View file @ 0de085bb
...@@ -553,7 +553,8 @@ static void __init mpc82xx_add_bridge(struct device_node *np) ...@@ -553,7 +553,8 @@ static void __init mpc82xx_add_bridge(struct device_node *np)
setup_indirect_pci(hose, setup_indirect_pci(hose,
r.start + offsetof(pci_cpm2_t, pci_cfg_addr), r.start + offsetof(pci_cpm2_t, pci_cfg_addr),
r.start + offsetof(pci_cpm2_t, pci_cfg_data)); r.start + offsetof(pci_cpm2_t, pci_cfg_data),
0);
pci_process_bridge_OF_ranges(hose, np, 1); pci_process_bridge_OF_ranges(hose, np, 1);
} }
......
arch/powerpc/platforms/83xx/pci.c
View file @ 0de085bb
...@@ -74,11 +74,11 @@ int __init mpc83xx_add_bridge(struct device_node *dev) ...@@ -74,11 +74,11 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
*/ */
/* PCI 1 */ /* PCI 1 */
if ((rsrc.start & 0xfffff) == 0x8500) { if ((rsrc.start & 0xfffff) == 0x8500) {
setup_indirect_pci(hose, immr + 0x8300, immr + 0x8304); setup_indirect_pci(hose, immr + 0x8300, immr + 0x8304, 0);
} }
/* PCI 2 */ /* PCI 2 */
if ((rsrc.start & 0xfffff) == 0x8600) { if ((rsrc.start & 0xfffff) == 0x8600) {
setup_indirect_pci(hose, immr + 0x8380, immr + 0x8384); setup_indirect_pci(hose, immr + 0x8380, immr + 0x8384, 0);
primary = 0; primary = 0;
} }
......
arch/powerpc/platforms/85xx/Kconfig
View file @ 0de085bb
...@@ -18,6 +18,7 @@ config MPC8560_ADS ...@@ -18,6 +18,7 @@ config MPC8560_ADS
config MPC85xx_CDS config MPC85xx_CDS
bool "Freescale MPC85xx CDS" bool "Freescale MPC85xx CDS"
select DEFAULT_UIMAGE select DEFAULT_UIMAGE
select PPC_I8259
help help
This option enables support for the MPC85xx CDS board This option enables support for the MPC85xx CDS board
...@@ -30,6 +31,7 @@ config MPC85xx_MDS ...@@ -30,6 +31,7 @@ config MPC85xx_MDS
config MPC8544_DS config MPC8544_DS
bool "Freescale MPC8544 DS" bool "Freescale MPC8544 DS"
select PPC_I8259
select DEFAULT_UIMAGE select DEFAULT_UIMAGE
help help
This option enables support for the MPC8544 DS board This option enables support for the MPC8544 DS board
...@@ -50,9 +52,9 @@ config MPC8560 ...@@ -50,9 +52,9 @@ config MPC8560
config MPC85xx config MPC85xx
bool bool
select PPC_UDBG_16550 select PPC_UDBG_16550
select PPC_INDIRECT_PCI select PPC_INDIRECT_PCI if PCI
select PPC_INDIRECT_PCI_BE
select MPIC select MPIC
select FSL_PCI if PCI
select SERIAL_8250_SHARE_IRQ if SERIAL_8250 select SERIAL_8250_SHARE_IRQ if SERIAL_8250
default y if MPC8540_ADS || MPC85xx_CDS || MPC8560_ADS \ default y if MPC8540_ADS || MPC85xx_CDS || MPC8560_ADS \
|| MPC85xx_MDS || MPC8544_DS || MPC85xx_MDS || MPC8544_DS
arch/powerpc/platforms/85xx/Makefile
View file @ 0de085bb
# #
# Makefile for the PowerPC 85xx linux kernel. # Makefile for the PowerPC 85xx linux kernel.
# #
obj-$(CONFIG_PPC_85xx) += misc.o pci.o obj-$(CONFIG_PPC_85xx) += misc.o
obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o
obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
......
arch/powerpc/platforms/85xx/mpc8544_ds.c
View file @ 0de085bb
...@@ -2,6 +2,8 @@ ...@@ -2,6 +2,8 @@
* MPC8544 DS Board Setup * MPC8544 DS Board Setup
* *
* Author Xianghua Xiao (x.xiao@freescale.com) * Author Xianghua Xiao (x.xiao@freescale.com)
* Roy Zang <tie-fei.zang@freescale.com>
* - Add PCI/PCI Exprees support
* Copyright 2007 Freescale Semiconductor Inc. * Copyright 2007 Freescale Semiconductor Inc.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
...@@ -12,13 +14,16 @@ ...@@ -12,13 +14,16 @@
#include <linux/stddef.h> #include <linux/stddef.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/kdev_t.h> #include <linux/kdev_t.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/seq_file.h> #include <linux/seq_file.h>
#include <linux/interrupt.h>
#include <asm/system.h> #include <asm/system.h>
#include <asm/time.h> #include <asm/time.h>
#include <asm/machdep.h> #include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <asm/mpc85xx.h> #include <asm/mpc85xx.h>
#include <mm/mmu_decl.h> #include <mm/mmu_decl.h>
#include <asm/prom.h> #include <asm/prom.h>
...@@ -27,6 +32,7 @@ ...@@ -27,6 +32,7 @@
#include <asm/i8259.h> #include <asm/i8259.h>
#include <sysdev/fsl_soc.h> #include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#include "mpc85xx.h" #include "mpc85xx.h"
#undef DEBUG #undef DEBUG
...@@ -37,6 +43,17 @@ ...@@ -37,6 +43,17 @@
#define DBG(fmt, args...) #define DBG(fmt, args...)
#endif #endif
#ifdef CONFIG_PPC_I8259
static void mpc8544_8259_cascade(unsigned int irq, struct irq_desc *desc)
{
unsigned int cascade_irq = i8259_irq();
if (cascade_irq != NO_IRQ) {
generic_handle_irq(cascade_irq);
}
desc->chip->eoi(irq);
}
#endif /* CONFIG_PPC_I8259 */
void __init mpc8544_ds_pic_init(void) void __init mpc8544_ds_pic_init(void)
{ {
...@@ -96,19 +113,240 @@ void __init mpc8544_ds_pic_init(void) ...@@ -96,19 +113,240 @@ void __init mpc8544_ds_pic_init(void)
#endif /* CONFIG_PPC_I8259 */ #endif /* CONFIG_PPC_I8259 */
} }
#ifdef CONFIG_PCI
enum pirq { PIRQA = 8, PIRQB, PIRQC, PIRQD, PIRQE, PIRQF, PIRQG, PIRQH };
/*
* Value in table -- IRQ number
*/
const unsigned char uli1575_irq_route_table[16] = {
0, /* 0: Reserved */
0x8,
0, /* 2: Reserved */
0x2,
0x4,
0x5,
0x7,
0x6,
0, /* 8: Reserved */
0x1,
0x3,
0x9,
0xb,
0, /* 13: Reserved */
0xd,
0xf,
};
static int __devinit
get_pci_irq_from_of(struct pci_controller *hose, int slot, int pin)
{
struct of_irq oirq;
u32 laddr[3];
struct device_node *hosenode = hose ? hose->arch_data : NULL;
if (!hosenode)
return -EINVAL;
laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(slot, 0) << 8);
laddr[1] = laddr[2] = 0;
of_irq_map_raw(hosenode, &pin, 1, laddr, &oirq);
DBG("mpc8544_ds: pci irq addr %x, slot %d, pin %d, irq %d\n",
laddr[0], slot, pin, oirq.specifier[0]);
return oirq.specifier[0];
}
/*8259*/
static void __devinit quirk_uli1575(struct pci_dev *dev)
{
unsigned short temp;
struct pci_controller *hose = pci_bus_to_host(dev->bus);
unsigned char irq2pin[16];
unsigned long pirq_map_word = 0;
u32 irq;
int i;
/*
* ULI1575 interrupts route setup
*/
memset(irq2pin, 0, 16); /* Initialize default value 0 */
irq2pin[6]=PIRQA+3; /* enabled mapping for IRQ6 to PIRQD, used by SATA */
/*
* PIRQE -> PIRQF mapping set manually
*
* IRQ pin IRQ#
* PIRQE ---- 9
* PIRQF ---- 10
* PIRQG ---- 11
* PIRQH ---- 12
*/
for (i = 0; i < 4; i++)
irq2pin[i + 9] = PIRQE + i;
/* Set IRQ-PIRQ Mapping to ULI1575 */
for (i = 0; i < 16; i++)
if (irq2pin[i])
pirq_map_word |= (uli1575_irq_route_table[i] & 0xf)
<< ((irq2pin[i] - PIRQA) * 4);
pirq_map_word |= 1<<26; /* disable INTx in EP mode*/
/* ULI1575 IRQ mapping conf register default value is 0xb9317542 */
DBG("Setup ULI1575 IRQ mapping configuration register value = 0x%x\n",
(int)pirq_map_word);
pci_write_config_dword(dev, 0x48, pirq_map_word);
#define ULI1575_SET_DEV_IRQ(slot, pin, reg) \
do { \
int irq; \
irq = get_pci_irq_from_of(hose, slot, pin); \
if (irq > 0 && irq < 16) \
pci_write_config_byte(dev, reg, irq2pin[irq]); \
else \
printk(KERN_WARNING "ULI1575 device" \
"(slot %d, pin %d) irq %d is invalid.\n", \
slot, pin, irq); \
} while(0)
/* USB 1.1 OHCI controller 1, slot 28, pin 1 */
ULI1575_SET_DEV_IRQ(28, 1, 0x86);
/* USB 1.1 OHCI controller 2, slot 28, pin 2 */
ULI1575_SET_DEV_IRQ(28, 2, 0x87);
/* USB 1.1 OHCI controller 3, slot 28, pin 3 */
ULI1575_SET_DEV_IRQ(28, 3, 0x88);
/* USB 2.0 controller, slot 28, pin 4 */
irq = get_pci_irq_from_of(hose, 28, 4);
if (irq >= 0 && irq <= 15)
pci_write_config_dword(dev, 0x74, uli1575_irq_route_table[irq]);
/* Audio controller, slot 29, pin 1 */
ULI1575_SET_DEV_IRQ(29, 1, 0x8a);
/* Modem controller, slot 29, pin 2 */
ULI1575_SET_DEV_IRQ(29, 2, 0x8b);
/* HD audio controller, slot 29, pin 3 */
ULI1575_SET_DEV_IRQ(29, 3, 0x8c);
/* SMB interrupt: slot 30, pin 1 */
ULI1575_SET_DEV_IRQ(30, 1, 0x8e);
/* PMU ACPI SCI interrupt: slot 30, pin 2 */
ULI1575_SET_DEV_IRQ(30, 2, 0x8f);
/* Serial ATA interrupt: slot 31, pin 1 */
ULI1575_SET_DEV_IRQ(31, 1, 0x8d);
/* Primary PATA IDE IRQ: 14
* Secondary PATA IDE IRQ: 15
*/
pci_write_config_byte(dev, 0x44, 0x30 | uli1575_irq_route_table[14]);
pci_write_config_byte(dev, 0x75, uli1575_irq_route_table[15]);
/* Set IRQ14 and IRQ15 to legacy IRQs */
pci_read_config_word(dev, 0x46, &temp);
temp |= 0xc000;
pci_write_config_word(dev, 0x46, temp);
/* Set i8259 interrupt trigger
* IRQ 3: Level
* IRQ 4: Level
* IRQ 5: Level
* IRQ 6: Level
* IRQ 7: Level
* IRQ 9: Level
* IRQ 10: Level
* IRQ 11: Level
* IRQ 12: Level
* IRQ 14: Edge
* IRQ 15: Edge
*/
outb(0xfa, 0x4d0);
outb(0x1e, 0x4d1);
#undef ULI1575_SET_DEV_IRQ
}
/* SATA */
static void __devinit quirk_uli5288(struct pci_dev *dev)
{
unsigned char c;
pci_read_config_byte(dev, 0x83, &c);
c |= 0x80; /* read/write lock */
pci_write_config_byte(dev, 0x83, c);
pci_write_config_byte(dev, 0x09, 0x01); /* Base class code: storage */
pci_write_config_byte(dev, 0x0a, 0x06); /* IDE disk */
pci_read_config_byte(dev, 0x83, &c);
c &= 0x7f;
pci_write_config_byte(dev, 0x83, c);
pci_read_config_byte(dev, 0x84, &c);
c |= 0x01; /* emulated PATA mode enabled */
pci_write_config_byte(dev, 0x84, c);
}
/* PATA */
static void __devinit quirk_uli5229(struct pci_dev *dev)
{
unsigned short temp;
pci_write_config_word(dev, 0x04, 0x0405); /* MEM IO MSI */
pci_read_config_word(dev, 0x4a, &temp);
temp |= 0x1000; /* Enable Native IRQ 14/15 */
pci_write_config_word(dev, 0x4a, temp);
}
/*Bridge*/
static void __devinit early_uli5249(struct pci_dev *dev)
{
unsigned char temp;
pci_write_config_word(dev, 0x04, 0x0007); /* mem access */
pci_read_config_byte(dev, 0x7c, &temp);
pci_write_config_byte(dev, 0x7c, 0x80); /* R/W lock control */
pci_write_config_byte(dev, 0x09, 0x01); /* set as pci-pci bridge */
pci_write_config_byte(dev, 0x7c, temp); /* restore pci bus debug control */
dev->class |= 0x1;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);
#endif /* CONFIG_PCI */
/* /*
* Setup the architecture * Setup the architecture
*/ */
static void __init mpc8544_ds_setup_arch(void) static void __init mpc8544_ds_setup_arch(void)
{ {
#ifdef CONFIG_PCI
struct device_node *np;
#endif
if (ppc_md.progress) if (ppc_md.progress)
ppc_md.progress("mpc8544_ds_setup_arch()", 0); ppc_md.progress("mpc8544_ds_setup_arch()", 0);
#ifdef CONFIG_PCI
for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) {
struct resource rsrc;
of_address_to_resource(np, 0, &rsrc);
if ((rsrc.start & 0xfffff) == 0xb000)
fsl_add_bridge(np, 1);
else
fsl_add_bridge(np, 0);
}
#endif
printk("MPC8544 DS board from Freescale Semiconductor\n"); printk("MPC8544 DS board from Freescale Semiconductor\n");
} }
/* /*
* Called very early, device-tree isn't unflattened * Called very early, device-tree isn't unflattened
*/ */
...@@ -124,6 +362,7 @@ define_machine(mpc8544_ds) { ...@@ -124,6 +362,7 @@ define_machine(mpc8544_ds) {
.probe = mpc8544_ds_probe, .probe = mpc8544_ds_probe,
.setup_arch = mpc8544_ds_setup_arch, .setup_arch = mpc8544_ds_setup_arch,
.init_IRQ = mpc8544_ds_pic_init, .init_IRQ = mpc8544_ds_pic_init,
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
.get_irq = mpic_get_irq, .get_irq = mpic_get_irq,
.restart = mpc85xx_restart, .restart = mpc85xx_restart,
.calibrate_decr = generic_calibrate_decr, .calibrate_decr = generic_calibrate_decr,
......
arch/powerpc/platforms/85xx/mpc85xx.h
View file @ 0de085bb
...@@ -15,4 +15,3 @@ ...@@ -15,4 +15,3 @@
*/ */
extern void mpc85xx_restart(char *); extern void mpc85xx_restart(char *);
extern int mpc85xx_add_bridge(struct device_node *dev);
arch/powerpc/platforms/85xx/mpc85xx_ads.c
View file @ 0de085bb
...@@ -29,6 +29,7 @@ ...@@ -29,6 +29,7 @@
#include <asm/udbg.h> #include <asm/udbg.h>
#include <sysdev/fsl_soc.h> #include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#include "mpc85xx.h" #include "mpc85xx.h"
#ifdef CONFIG_CPM2 #ifdef CONFIG_CPM2
...@@ -217,7 +218,7 @@ static void __init mpc85xx_ads_setup_arch(void) ...@@ -217,7 +218,7 @@ static void __init mpc85xx_ads_setup_arch(void)
#ifdef CONFIG_PCI #ifdef CONFIG_PCI
for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
mpc85xx_add_bridge(np); fsl_add_bridge(np, 1);
ppc_md.pci_exclude_device = mpc85xx_exclude_device; ppc_md.pci_exclude_device = mpc85xx_exclude_device;
#endif #endif
} }
......
arch/powerpc/platforms/85xx/mpc85xx_cds.c
View file @ 0de085bb
...@@ -24,6 +24,7 @@ ...@@ -24,6 +24,7 @@
#include <linux/seq_file.h> #include <linux/seq_file.h>
#include <linux/initrd.h> #include <linux/initrd.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/fsl_devices.h> #include <linux/fsl_devices.h>
#include <asm/system.h> #include <asm/system.h>
...@@ -45,6 +46,7 @@ ...@@ -45,6 +46,7 @@
#include <asm/i8259.h> #include <asm/i8259.h>
#include <sysdev/fsl_soc.h> #include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#include "mpc85xx.h" #include "mpc85xx.h"
static int cds_pci_slot = 2; static int cds_pci_slot = 2;
...@@ -58,8 +60,6 @@ static volatile u8 *cadmus; ...@@ -58,8 +60,6 @@ static volatile u8 *cadmus;
static int mpc85xx_exclude_device(struct pci_controller *hose, static int mpc85xx_exclude_device(struct pci_controller *hose,
u_char bus, u_char devfn) u_char bus, u_char devfn)
{ {
if ((bus == hose->first_busno) && PCI_SLOT(devfn) == 0)
return PCIBIOS_DEVICE_NOT_FOUND;
/* We explicitly do not go past the Tundra 320 Bridge */ /* We explicitly do not go past the Tundra 320 Bridge */
if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL)) if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
return PCIBIOS_DEVICE_NOT_FOUND; return PCIBIOS_DEVICE_NOT_FOUND;
...@@ -69,6 +69,37 @@ static int mpc85xx_exclude_device(struct pci_controller *hose, ...@@ -69,6 +69,37 @@ static int mpc85xx_exclude_device(struct pci_controller *hose,
return PCIBIOS_SUCCESSFUL; return PCIBIOS_SUCCESSFUL;
} }
static void mpc85xx_cds_restart(char *cmd)
{
struct pci_dev *dev;
u_char tmp;
if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686,
NULL))) {
/* Use the VIA Super Southbridge to force a PCI reset */
pci_read_config_byte(dev, 0x47, &tmp);
pci_write_config_byte(dev, 0x47, tmp | 1);
/* Flush the outbound PCI write queues */
pci_read_config_byte(dev, 0x47, &tmp);
/*
* At this point, the harware reset should have triggered.
* However, if it doesn't work for some mysterious reason,
* just fall through to the default reset below.
*/
pci_dev_put(dev);
}
/*
* If we can't find the VIA chip (maybe the P2P bridge is disabled)
* or the VIA chip reset didn't work, just use the default reset.
*/
mpc85xx_restart(NULL);
}
static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev) static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
{ {
u_char c; u_char c;
...@@ -98,7 +129,7 @@ static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev) ...@@ -98,7 +129,7 @@ static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
/* There are two USB controllers. /* There are two USB controllers.
* Identify them by functon number * Identify them by functon number
*/ */
if (PCI_FUNC(dev->devfn)) if (PCI_FUNC(dev->devfn) == 3)
dev->irq = 11; dev->irq = 11;
else else
dev->irq = 10; dev->irq = 10;
...@@ -109,17 +140,41 @@ static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev) ...@@ -109,17 +140,41 @@ static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
} }
} }
static void __devinit skip_fake_bridge(struct pci_dev *dev)
{
/* Make it an error to skip the fake bridge
* in pci_setup_device() in probe.c */
dev->hdr_type = 0x7f;
}
DECLARE_PCI_FIXUP_EARLY(0x1957, 0x3fff, skip_fake_bridge);
DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge);
DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge);
#ifdef CONFIG_PPC_I8259 #ifdef CONFIG_PPC_I8259
#warning The i8259 PIC support is currently broken static void mpc85xx_8259_cascade_handler(unsigned int irq,
static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc) struct irq_desc *desc)
{ {
unsigned int cascade_irq = i8259_irq(); unsigned int cascade_irq = i8259_irq();
if (cascade_irq != NO_IRQ) if (cascade_irq != NO_IRQ)
/* handle an interrupt from the 8259 */
generic_handle_irq(cascade_irq); generic_handle_irq(cascade_irq);
desc->chip->eoi(irq); /* check for any interrupts from the shared IRQ line */
handle_fasteoi_irq(irq, desc);
}
static irqreturn_t mpc85xx_8259_cascade_action(int irq, void *dev_id)
{
return IRQ_HANDLED;
} }
static struct irqaction mpc85xxcds_8259_irqaction = {
.handler = mpc85xx_8259_cascade_action,
.flags = IRQF_SHARED,
.mask = CPU_MASK_NONE,
.name = "8259 cascade",
};
#endif /* PPC_I8259 */ #endif /* PPC_I8259 */
#endif /* CONFIG_PCI */ #endif /* CONFIG_PCI */
...@@ -128,10 +183,6 @@ static void __init mpc85xx_cds_pic_init(void) ...@@ -128,10 +183,6 @@ static void __init mpc85xx_cds_pic_init(void)
struct mpic *mpic; struct mpic *mpic;
struct resource r; struct resource r;
struct device_node *np = NULL; struct device_node *np = NULL;
#ifdef CONFIG_PPC_I8259
struct device_node *cascade_node = NULL;
int cascade_irq;
#endif
np = of_find_node_by_type(np, "open-pic"); np = of_find_node_by_type(np, "open-pic");
...@@ -155,8 +206,19 @@ static void __init mpc85xx_cds_pic_init(void) ...@@ -155,8 +206,19 @@ static void __init mpc85xx_cds_pic_init(void)
of_node_put(np); of_node_put(np);
mpic_init(mpic); mpic_init(mpic);
}
#if defined(CONFIG_PPC_I8259) && defined(CONFIG_PCI)
static int mpc85xx_cds_8259_attach(void)
{
int ret;
struct device_node *np = NULL;
struct device_node *cascade_node = NULL;
int cascade_irq;
if (!machine_is(mpc85xx_cds))
return 0;
#ifdef CONFIG_PPC_I8259
/* Initialize the i8259 controller */ /* Initialize the i8259 controller */
for_each_node_by_type(np, "interrupt-controller") for_each_node_by_type(np, "interrupt-controller")
if (of_device_is_compatible(np, "chrp,iic")) { if (of_device_is_compatible(np, "chrp,iic")) {
...@@ -166,22 +228,39 @@ static void __init mpc85xx_cds_pic_init(void) ...@@ -166,22 +228,39 @@ static void __init mpc85xx_cds_pic_init(void)
if (cascade_node == NULL) { if (cascade_node == NULL) {
printk(KERN_DEBUG "Could not find i8259 PIC\n"); printk(KERN_DEBUG "Could not find i8259 PIC\n");
return; return -ENODEV;
} }
cascade_irq = irq_of_parse_and_map(cascade_node, 0); cascade_irq = irq_of_parse_and_map(cascade_node, 0);
if (cascade_irq == NO_IRQ) { if (cascade_irq == NO_IRQ) {
printk(KERN_ERR "Failed to map cascade interrupt\n"); printk(KERN_ERR "Failed to map cascade interrupt\n");
return; return -ENXIO;
} }
i8259_init(cascade_node, 0); i8259_init(cascade_node, 0);
of_node_put(cascade_node); of_node_put(cascade_node);
set_irq_chained_handler(cascade_irq, mpc85xx_8259_cascade); /*
#endif /* CONFIG_PPC_I8259 */ * Hook the interrupt to make sure desc->action is never NULL.
* This is required to ensure that the interrupt does not get
* disabled when the last user of the shared IRQ line frees their
* interrupt.
*/
if ((ret = setup_irq(cascade_irq, &mpc85xxcds_8259_irqaction))) {
printk(KERN_ERR "Failed to setup cascade interrupt\n");
return ret;
}
/* Success. Connect our low-level cascade handler. */
set_irq_handler(cascade_irq, mpc85xx_8259_cascade_handler);
return 0;
} }
device_initcall(mpc85xx_cds_8259_attach);
#endif /* CONFIG_PPC_I8259 */
/* /*
* Setup the architecture * Setup the architecture
*/ */
...@@ -218,9 +297,14 @@ static void __init mpc85xx_cds_setup_arch(void) ...@@ -218,9 +297,14 @@ static void __init mpc85xx_cds_setup_arch(void)
} }
#ifdef CONFIG_PCI #ifdef CONFIG_PCI
for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) {
mpc85xx_add_bridge(np); struct resource rsrc;
of_address_to_resource(np, 0, &rsrc);
if ((rsrc.start & 0xfffff) == 0x8000)
fsl_add_bridge(np, 1);
else
fsl_add_bridge(np, 0);
}
ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup; ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup;
ppc_md.pci_exclude_device = mpc85xx_exclude_device; ppc_md.pci_exclude_device = mpc85xx_exclude_device;
#endif #endif
...@@ -265,7 +349,12 @@ define_machine(mpc85xx_cds) { ...@@ -265,7 +349,12 @@ define_machine(mpc85xx_cds) {
.init_IRQ = mpc85xx_cds_pic_init, .init_IRQ = mpc85xx_cds_pic_init,
.show_cpuinfo = mpc85xx_cds_show_cpuinfo, .show_cpuinfo = mpc85xx_cds_show_cpuinfo,
.get_irq = mpic_get_irq, .get_irq = mpic_get_irq,
#ifdef CONFIG_PCI
.restart = mpc85xx_cds_restart,
#else
.restart = mpc85xx_restart, .restart = mpc85xx_restart,
#endif
.calibrate_decr = generic_calibrate_decr, .calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress, .progress = udbg_progress,
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
}; };
arch/powerpc/platforms/85xx/mpc85xx_mds.c
View file @ 0de085bb
...@@ -46,6 +46,7 @@ ...@@ -46,6 +46,7 @@
#include <asm/prom.h> #include <asm/prom.h>
#include <asm/udbg.h> #include <asm/udbg.h>
#include <sysdev/fsl_soc.h> #include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#include <asm/qe.h> #include <asm/qe.h>
#include <asm/qe_ic.h> #include <asm/qe_ic.h>
#include <asm/mpic.h> #include <asm/mpic.h>
...@@ -94,9 +95,8 @@ static void __init mpc85xx_mds_setup_arch(void) ...@@ -94,9 +95,8 @@ static void __init mpc85xx_mds_setup_arch(void)
} }
#ifdef CONFIG_PCI #ifdef CONFIG_PCI
for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) { for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
mpc85xx_add_bridge(np); fsl_add_bridge(np, 1);
}
of_node_put(np); of_node_put(np);
#endif #endif
...@@ -208,4 +208,5 @@ define_machine(mpc85xx_mds) { ...@@ -208,4 +208,5 @@ define_machine(mpc85xx_mds) {
.restart = mpc85xx_restart, .restart = mpc85xx_restart,
.calibrate_decr = generic_calibrate_decr, .calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress, .progress = udbg_progress,
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
}; };
arch/powerpc/platforms/85xx/pci.c deleted 100644 → 0
View file @ 3836df6b
/*
* FSL SoC setup code
*
* Maintained by Kumar Gala (see MAINTAINERS for contact information)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <asm/system.h>
#include <asm/atomic.h>
#include <asm/io.h>
#include <asm/pci-bridge.h>
#include <asm/prom.h>
#include <sysdev/fsl_soc.h>
#undef DEBUG
#ifdef DEBUG
#define DBG(x...) printk(x)
#else
#define DBG(x...)
#endif
#ifdef CONFIG_PCI
int __init mpc85xx_add_bridge(struct device_node *dev)
{
int len;
struct pci_controller *hose;
struct resource rsrc;
const int *bus_range;
int primary = 1, has_address = 0;
phys_addr_t immr = get_immrbase();
DBG("Adding PCI host bridge %s\n", dev->full_name);
/* Fetch host bridge registers address */
has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
/* Get bus range if any */
bus_range = of_get_property(dev, "bus-range", &len);
if (bus_range == NULL || len < 2 * sizeof(int)) {
printk(KERN_WARNING "Can't get bus-range for %s, assume"
" bus 0\n", dev->full_name);
}
pci_assign_all_buses = 1;
hose = pcibios_alloc_controller(dev);
if (!hose)
return -ENOMEM;
hose->first_busno = bus_range ? bus_range[0] : 0;
hose->last_busno = bus_range ? bus_range[1] : 0xff;
/* PCI 1 */
if ((rsrc.start & 0xfffff) == 0x8000) {
setup_indirect_pci(hose, immr + 0x8000, immr + 0x8004);
}
/* PCI 2 */
if ((rsrc.start & 0xfffff) == 0x9000) {
setup_indirect_pci(hose, immr + 0x9000, immr + 0x9004);
primary = 0;
}
printk(KERN_INFO "Found MPC85xx PCI host bridge at 0x%016llx. "
"Firmware bus number: %d->%d\n",
(unsigned long long)rsrc.start, hose->first_busno,
hose->last_busno);
DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
hose, hose->cfg_addr, hose->cfg_data);
/* Interpret the "ranges" property */
/* This also maps the I/O region and sets isa_io/mem_base */
pci_process_bridge_OF_ranges(hose, dev, primary);
return 0;
}
#endif
arch/powerpc/platforms/86xx/Kconfig
View file @ 0de085bb
...@@ -14,8 +14,7 @@ endchoice ...@@ -14,8 +14,7 @@ endchoice
config MPC8641 config MPC8641
bool bool
select PPC_INDIRECT_PCI select FSL_PCI if PCI
select PPC_INDIRECT_PCI_BE
select PPC_UDBG_16550 select PPC_UDBG_16550
select MPIC select MPIC
default y if MPC8641_HPCN default y if MPC8641_HPCN
arch/powerpc/platforms/86xx/Makefile
View file @ 0de085bb
...@@ -4,4 +4,3 @@ ...@@ -4,4 +4,3 @@
obj-$(CONFIG_SMP) += mpc86xx_smp.o obj-$(CONFIG_SMP) += mpc86xx_smp.o
obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o
obj-$(CONFIG_PCI) += pci.o
arch/powerpc/platforms/86xx/mpc86xx.h
View file @ 0de085bb
...@@ -15,11 +15,6 @@ ...@@ -15,11 +15,6 @@
* mpc86xx_* files. Mostly for use by mpc86xx_setup(). * mpc86xx_* files. Mostly for use by mpc86xx_setup().
*/ */
extern int mpc86xx_add_bridge(struct device_node *dev);
extern int mpc86xx_exclude_device(struct pci_controller *hose,
u_char bus, u_char devfn);
extern void __init mpc86xx_smp_init(void); extern void __init mpc86xx_smp_init(void);
#endif /* __MPC86XX_H__ */ #endif /* __MPC86XX_H__ */
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
View file @ 0de085bb
...@@ -31,6 +31,7 @@ ...@@ -31,6 +31,7 @@
#include <asm/mpic.h> #include <asm/mpic.h>
#include <sysdev/fsl_pci.h>
#include <sysdev/fsl_soc.h> #include <sysdev/fsl_soc.h>
#include "mpc86xx.h" #include "mpc86xx.h"
...@@ -344,8 +345,14 @@ mpc86xx_hpcn_setup_arch(void) ...@@ -344,8 +345,14 @@ mpc86xx_hpcn_setup_arch(void)
} }
#ifdef CONFIG_PCI #ifdef CONFIG_PCI
for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) {
mpc86xx_add_bridge(np); struct resource rsrc;
of_address_to_resource(np, 0, &rsrc);
if ((rsrc.start & 0xfffff) == 0x8000)
fsl_add_bridge(np, 1);
else
fsl_add_bridge(np, 0);
}
#endif #endif
printk("MPC86xx HPCN board from Freescale Semiconductor\n"); printk("MPC86xx HPCN board from Freescale Semiconductor\n");
...@@ -424,7 +431,6 @@ mpc86xx_time_init(void) ...@@ -424,7 +431,6 @@ mpc86xx_time_init(void)
return 0; return 0;
} }
define_machine(mpc86xx_hpcn) { define_machine(mpc86xx_hpcn) {
.name = "MPC86xx HPCN", .name = "MPC86xx HPCN",
.probe = mpc86xx_hpcn_probe, .probe = mpc86xx_hpcn_probe,
...@@ -436,4 +442,5 @@ define_machine(mpc86xx_hpcn) { ...@@ -436,4 +442,5 @@ define_machine(mpc86xx_hpcn) {
.time_init = mpc86xx_time_init, .time_init = mpc86xx_time_init,
.calibrate_decr = generic_calibrate_decr, .calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress, .progress = udbg_progress,
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
}; };
arch/powerpc/platforms/86xx/pci.c deleted 100644 → 0
View file @ 3836df6b
/*
* MPC86XX pci setup code
*
* Recode: ZHANG WEI <wei.zhang@freescale.com>
* Initial author: Xianghua Xiao <x.xiao@freescale.com>
*
* Copyright 2006 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/types.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/serial.h>
#include <asm/system.h>
#include <asm/atomic.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pcie.h>
#include "mpc86xx.h"
#undef DEBUG
#ifdef DEBUG
#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
#else
#define DBG(fmt, args...)
#endif
struct pcie_outbound_window_regs {
uint pexotar; /* 0x.0 - PCI Express outbound translation address register */
uint pexotear; /* 0x.4 - PCI Express outbound translation extended address register */
uint pexowbar; /* 0x.8 - PCI Express outbound window base address register */
char res1[4];
uint pexowar; /* 0x.10 - PCI Express outbound window attributes register */
char res2[12];
};
struct pcie_inbound_window_regs {
uint pexitar; /* 0x.0 - PCI Express inbound translation address register */
char res1[4];
uint pexiwbar; /* 0x.8 - PCI Express inbound window base address register */
uint pexiwbear; /* 0x.c - PCI Express inbound window base extended address register */
uint pexiwar; /* 0x.10 - PCI Express inbound window attributes register */
char res2[12];
};
static void __init setup_pcie_atmu(struct pci_controller *hose, struct resource *rsrc)
{
volatile struct ccsr_pex *pcie;
volatile struct pcie_outbound_window_regs *pcieow;
volatile struct pcie_inbound_window_regs *pcieiw;
int i = 0;
DBG("PCIE memory map start 0x%x, size 0x%x\n", rsrc->start,
rsrc->end - rsrc->start + 1);
pcie = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
/* Disable all windows (except pexowar0 since its ignored) */
pcie->pexowar1 = 0;
pcie->pexowar2 = 0;
pcie->pexowar3 = 0;
pcie->pexowar4 = 0;
pcie->pexiwar1 = 0;
pcie->pexiwar2 = 0;
pcie->pexiwar3 = 0;
pcieow = (struct pcie_outbound_window_regs *)&pcie->pexotar1;
pcieiw = (struct pcie_inbound_window_regs *)&pcie->pexitar1;
/* Setup outbound MEM window */
for(i = 0; i < 3; i++)
if (hose->mem_resources[i].flags & IORESOURCE_MEM){
DBG("PCIE MEM resource start 0x%08x, size 0x%08x.\n",
hose->mem_resources[i].start,
hose->mem_resources[i].end
- hose->mem_resources[i].start + 1);
pcieow->pexotar = (hose->mem_resources[i].start) >> 12
& 0x000fffff;
pcieow->pexotear = 0;
pcieow->pexowbar = (hose->mem_resources[i].start) >> 12
& 0x000fffff;
/* Enable, Mem R/W */
pcieow->pexowar = 0x80044000 |
(__ilog2(hose->mem_resources[i].end
- hose->mem_resources[i].start + 1)
- 1);
pcieow++;
}
/* Setup outbound IO window */
if (hose->io_resource.flags & IORESOURCE_IO){
DBG("PCIE IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n",
hose->io_resource.start,
hose->io_resource.end - hose->io_resource.start + 1,
hose->io_base_phys);
pcieow->pexotar = (hose->io_resource.start) >> 12 & 0x000fffff;
pcieow->pexotear = 0;
pcieow->pexowbar = (hose->io_base_phys) >> 12 & 0x000fffff;
/* Enable, IO R/W */
pcieow->pexowar = 0x80088000 | (__ilog2(hose->io_resource.end
- hose->io_resource.start + 1) - 1);
}
/* Setup 2G inbound Memory Window @ 0 */
pcieiw->pexitar = 0x00000000;
pcieiw->pexiwbar = 0x00000000;
/* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
pcieiw->pexiwar = 0xa0f5501e;
}
static void __init
mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)
{
u16 cmd;
DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n",
pcie_offset, pcie_size);
early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
| PCI_COMMAND_IO;
early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
}
static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev)
{
struct resource *res;
int i, res_idx = PCI_BRIDGE_RESOURCES;
struct pci_controller *hose;
/*
* Make the bridge be transparent.
*/
dev->transparent = 1;
hose = pci_bus_to_host(dev->bus);
if (!hose) {
printk(KERN_ERR "Can't find hose for bus %d\n",
dev->bus->number);
return;
}
if (hose->io_resource.flags) {
res = &dev->resource[res_idx++];
res->start = hose->io_resource.start;
res->end = hose->io_resource.end;
res->flags = hose->io_resource.flags;
}
for (i = 0; i < 3; i++) {
res = &dev->resource[res_idx + i];
res->start = hose->mem_resources[i].start;
res->end = hose->mem_resources[i].end;
res->flags = hose->mem_resources[i].flags;
}
}
DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent);
DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent);
#define PCIE_LTSSM 0x404 /* PCIe Link Training and Status */
#define PCIE_LTSSM_L0 0x16 /* L0 state */
int __init mpc86xx_add_bridge(struct device_node *dev)
{
int len;
struct pci_controller *hose;
struct resource rsrc;
const int *bus_range;
int has_address = 0;
int primary = 0;
u16 val;
DBG("Adding PCIE host bridge %s\n", dev->full_name);
/* Fetch host bridge registers address */
has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
/* Get bus range if any */
bus_range = of_get_property(dev, "bus-range", &len);
if (bus_range == NULL || len < 2 * sizeof(int))
printk(KERN_WARNING "Can't get bus-range for %s, assume"
" bus 0\n", dev->full_name);
pci_assign_all_buses = 1;
hose = pcibios_alloc_controller(dev);
if (!hose)
return -ENOMEM;
hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG |
PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
hose->first_busno = bus_range ? bus_range[0] : 0x0;
hose->last_busno = bus_range ? bus_range[1] : 0xff;
setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4);
/* Probe the hose link training status */
early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val);
if (val < PCIE_LTSSM_L0)
return -ENXIO;
/* Setup the PCIE host controller. */
mpc86xx_setup_pcie(hose, rsrc.start, rsrc.end - rsrc.start + 1);
if ((rsrc.start & 0xfffff) == 0x8000)
primary = 1;
printk(KERN_INFO "Found MPC86xx PCIE host bridge at 0x%08lx. "
"Firmware bus number: %d->%d\n",
(unsigned long) rsrc.start,
hose->first_busno, hose->last_busno);
DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
hose, hose->cfg_addr, hose->cfg_data);
/* Interpret the "ranges" property */
/* This also maps the I/O region and sets isa_io/mem_base */
pci_process_bridge_OF_ranges(hose, dev, primary);
/* Setup PEX window registers */
setup_pcie_atmu(hose, &rsrc);
return 0;
}
arch/powerpc/platforms/chrp/pci.c
View file @ 0de085bb
...@@ -181,7 +181,7 @@ setup_python(struct pci_controller *hose, struct device_node *dev) ...@@ -181,7 +181,7 @@ setup_python(struct pci_controller *hose, struct device_node *dev)
} }
iounmap(reg); iounmap(reg);
setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010); setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010, 0);
} }
/* Marvell Discovery II based Pegasos 2 */ /* Marvell Discovery II based Pegasos 2 */
...@@ -277,13 +277,14 @@ chrp_find_bridges(void) ...@@ -277,13 +277,14 @@ chrp_find_bridges(void)
hose->cfg_data = p; hose->cfg_data = p;
gg2_pci_config_base = p; gg2_pci_config_base = p;
} else if (is_pegasos == 1) { } else if (is_pegasos == 1) {
setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc); setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc, 0);
} else if (is_pegasos == 2) { } else if (is_pegasos == 2) {
setup_peg2(hose, dev); setup_peg2(hose, dev);
} else if (!strncmp(model, "IBM,CPC710", 10)) { } else if (!strncmp(model, "IBM,CPC710", 10)) {
setup_indirect_pci(hose, setup_indirect_pci(hose,
r.start + 0x000f8000, r.start + 0x000f8000,
r.start + 0x000f8010); r.start + 0x000f8010,
0);
if (index == 0) { if (index == 0) {
dma = of_get_property(dev, "system-dma-base", dma = of_get_property(dev, "system-dma-base",
&len); &len);
......
arch/powerpc/platforms/embedded6xx/linkstation.c
View file @ 0de085bb
...@@ -73,7 +73,7 @@ static int __init linkstation_add_bridge(struct device_node *dev) ...@@ -73,7 +73,7 @@ static int __init linkstation_add_bridge(struct device_node *dev)
return -ENOMEM; return -ENOMEM;
hose->first_busno = bus_range ? bus_range[0] : 0; hose->first_busno = bus_range ? bus_range[0] : 0;
hose->last_busno = bus_range ? bus_range[1] : 0xff; hose->last_busno = bus_range ? bus_range[1] : 0xff;
setup_indirect_pci(hose, 0xfec00000, 0xfee00000); setup_indirect_pci(hose, 0xfec00000, 0xfee00000, 0);
/* Interpret the "ranges" property */ /* Interpret the "ranges" property */
/* This also maps the I/O region and sets isa_io/mem_base */ /* This also maps the I/O region and sets isa_io/mem_base */
......
arch/powerpc/sysdev/Makefile
View file @ 0de085bb
...@@ -12,6 +12,7 @@ obj-$(CONFIG_PPC_PMI) += pmi.o ...@@ -12,6 +12,7 @@ obj-$(CONFIG_PPC_PMI) += pmi.o
obj-$(CONFIG_U3_DART) += dart_iommu.o obj-$(CONFIG_U3_DART) += dart_iommu.o
obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
obj-$(CONFIG_FSL_SOC) += fsl_soc.o obj-$(CONFIG_FSL_SOC) += fsl_soc.o
obj-$(CONFIG_FSL_PCI) += fsl_pci.o
obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
obj-$(CONFIG_QUICC_ENGINE) += qe_lib/ obj-$(CONFIG_QUICC_ENGINE) += qe_lib/
mv64x60-$(CONFIG_PCI) += mv64x60_pci.o mv64x60-$(CONFIG_PCI) += mv64x60_pci.o
......
arch/powerpc/sysdev/fsl_pci.c 0 → 100644
View file @ 0de085bb
/*
* MPC85xx/86xx PCI/PCIE support routing.
*
* Copyright 2007 Freescale Semiconductor, Inc
*
* Initial author: Xianghua Xiao <x.xiao@freescale.com>
* Recode: ZHANG WEI <wei.zhang@freescale.com>
* Rewrite the routing for Frescale PCI and PCI Express
* Roy Zang <tie-fei.zang@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/bootmem.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#include <asm/machdep.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
/* atmu setup for fsl pci/pcie controller */
void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc)
{
struct ccsr_pci __iomem *pci;
int i;
pr_debug("PCI memory map start 0x%x, size 0x%x\n", rsrc->start,
rsrc->end - rsrc->start + 1);
pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
/* Disable all windows (except powar0 since its ignored) */
for(i = 1; i < 5; i++)
out_be32(&pci->pow[i].powar, 0);
for(i = 0; i < 3; i++)
out_be32(&pci->piw[i].piwar, 0);
/* Setup outbound MEM window */
for(i = 0; i < 3; i++)
if (hose->mem_resources[i].flags & IORESOURCE_MEM){
pr_debug("PCI MEM resource start 0x%08x, size 0x%08x.\n",
hose->mem_resources[i].start,
hose->mem_resources[i].end
- hose->mem_resources[i].start + 1);
out_be32(&pci->pow[i+1].potar,
(hose->mem_resources[i].start >> 12)
& 0x000fffff);
out_be32(&pci->pow[i+1].potear, 0);
out_be32(&pci->pow[i+1].powbar,
(hose->mem_resources[i].start >> 12)
& 0x000fffff);
/* Enable, Mem R/W */
out_be32(&pci->pow[i+1].powar, 0x80044000
| (__ilog2(hose->mem_resources[i].end
- hose->mem_resources[i].start + 1) - 1));
}
/* Setup outbound IO window */
if (hose->io_resource.flags & IORESOURCE_IO){
pr_debug("PCI IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n",
hose->io_resource.start,
hose->io_resource.end - hose->io_resource.start + 1,
hose->io_base_phys);
out_be32(&pci->pow[i+1].potar, (hose->io_resource.start >> 12)
& 0x000fffff);
out_be32(&pci->pow[i+1].potear, 0);
out_be32(&pci->pow[i+1].powbar, (hose->io_base_phys >> 12)
& 0x000fffff);
/* Enable, IO R/W */
out_be32(&pci->pow[i+1].powar, 0x80088000
| (__ilog2(hose->io_resource.end
- hose->io_resource.start + 1) - 1));
}
/* Setup 2G inbound Memory Window @ 1 */
out_be32(&pci->piw[2].pitar, 0x00000000);
out_be32(&pci->piw[2].piwbar,0x00000000);
out_be32(&pci->piw[2].piwar, PIWAR_2G);
}
void __init setup_pci_cmd(struct pci_controller *hose)
{
u16 cmd;
int cap_x;
early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
| PCI_COMMAND_IO;
early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
if (cap_x) {
int pci_x_cmd = cap_x + PCI_X_CMD;
cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
} else {
early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
}
}
static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev)
{
struct resource *res;
int i, res_idx = PCI_BRIDGE_RESOURCES;
struct pci_controller *hose;
/* if we aren't a PCIe don't bother */
if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
return ;
/*
* Make the bridge be transparent.
*/
dev->transparent = 1;
hose = pci_bus_to_host(dev->bus);
if (!hose) {
printk(KERN_ERR "Can't find hose for bus %d\n",
dev->bus->number);
return;
}
/* Clear out any of the virtual P2P bridge registers */
pci_write_config_word(dev, PCI_IO_BASE_UPPER16, 0);
pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16, 0);
pci_write_config_byte(dev, PCI_IO_BASE, 0x10);
pci_write_config_byte(dev, PCI_IO_LIMIT, 0);
pci_write_config_word(dev, PCI_MEMORY_BASE, 0x10);
pci_write_config_word(dev, PCI_MEMORY_LIMIT, 0);
pci_write_config_word(dev, PCI_PREF_BASE_UPPER32, 0x0);
pci_write_config_word(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10);
pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
if (hose->io_resource.flags) {
res = &dev->resource[res_idx++];
res->start = hose->io_resource.start;
res->end = hose->io_resource.end;
res->flags = hose->io_resource.flags;
update_bridge_resource(dev, res);
}
for (i = 0; i < 3; i++) {
res = &dev->resource[res_idx + i];
res->start = hose->mem_resources[i].start;
res->end = hose->mem_resources[i].end;
res->flags = hose->mem_resources[i].flags;
update_bridge_resource(dev, res);
}
}
int __init fsl_pcie_check_link(struct pci_controller *hose)
{
u16 val;
early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val);
if (val < PCIE_LTSSM_L0)
return 1;
return 0;
}
void fsl_pcibios_fixup_bus(struct pci_bus *bus)
{
struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
int i;
/* deal with bogus pci_bus when we don't have anything connected on PCIe */
if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {
if (bus->parent) {
for (i = 0; i < 4; ++i)
bus->resource[i] = bus->parent->resource[i];
}
}
}
int __init fsl_add_bridge(struct device_node *dev, int is_primary)
{
int len;
struct pci_controller *hose;
struct resource rsrc;
const int *bus_range;
pr_debug("Adding PCI host bridge %s\n", dev->full_name);
/* Fetch host bridge registers address */
if (of_address_to_resource(dev, 0, &rsrc)) {
printk(KERN_WARNING "Can't get pci register base!");
return -ENOMEM;
}
/* Get bus range if any */
bus_range = of_get_property(dev, "bus-range", &len);
if (bus_range == NULL || len < 2 * sizeof(int))
printk(KERN_WARNING "Can't get bus-range for %s, assume"
" bus 0\n", dev->full_name);
pci_assign_all_buses = 1;
hose = pcibios_alloc_controller(dev);
if (!hose)
return -ENOMEM;
hose->first_busno = bus_range ? bus_range[0] : 0x0;
hose->last_busno = bus_range ? bus_range[1] : 0xff;
setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
PPC_INDIRECT_TYPE_BIG_ENDIAN);
setup_pci_cmd(hose);
/* check PCI express link status */
if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG |
PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
if (fsl_pcie_check_link(hose))
hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
}
printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx."
"Firmware bus number: %d->%d\n",
(unsigned long long)rsrc.start, hose->first_busno,
hose->last_busno);
pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
hose, hose->cfg_addr, hose->cfg_data);
/* Interpret the "ranges" property */
/* This also maps the I/O region and sets isa_io/mem_base */
pci_process_bridge_OF_ranges(hose, dev, is_primary);
/* Setup PEX window registers */
setup_pci_atmu(hose, &rsrc);
return 0;
}
DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_transparent);
DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_transparent);
DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_transparent);
DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_transparent);
DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_transparent);
DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_transparent);
DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_transparent);
DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_transparent);
DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_transparent);
DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_transparent);
DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_transparent);
DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_transparent);
DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_transparent);
DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_transparent);
DECLARE_PCI_FIXUP_EARLY(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_transparent);
arch/powerpc/sysdev/fsl_pci.h 0 → 100644
View file @ 0de085bb
/*
* MPC85xx/86xx PCI Express structure define
*
* Copyright 2007 Freescale Semiconductor, Inc
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifdef __KERNEL__
#ifndef __POWERPC_FSL_PCI_H
#define __POWERPC_FSL_PCI_H
#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
#define PCIE_LTSSM_L0 0x16 /* L0 state */
#define PIWAR_2G 0xa0f5501e /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
/* PCI/PCI Express outbound window reg */
struct pci_outbound_window_regs {
__be32 potar; /* 0x.0 - Outbound translation address register */
__be32 potear; /* 0x.4 - Outbound translation extended address register */
__be32 powbar; /* 0x.8 - Outbound window base address register */
u8 res1[4];
__be32 powar; /* 0x.10 - Outbound window attributes register */
u8 res2[12];
};
/* PCI/PCI Express inbound window reg */
struct pci_inbound_window_regs {
__be32 pitar; /* 0x.0 - Inbound translation address register */
u8 res1[4];
__be32 piwbar; /* 0x.8 - Inbound window base address register */
__be32 piwbear; /* 0x.c - Inbound window base extended address register */
__be32 piwar; /* 0x.10 - Inbound window attributes register */
u8 res2[12];
};
/* PCI/PCI Express IO block registers for 85xx/86xx */
struct ccsr_pci {
__be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */
__be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */
__be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
__be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */
__be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */
u8 res2[12];
__be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */
__be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */
__be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */
__be32 pex_pmcr; /* 0x.02c - PCIE power management command register */
u8 res3[3024];
/* PCI/PCI Express outbound window 0-4
* Window 0 is the default window and is the only window enabled upon reset.
* The default outbound register set is used when a transaction misses
* in all of the other outbound windows.
*/
struct pci_outbound_window_regs pow[5];
u8 res14[256];
/* PCI/PCI Express inbound window 3-1
* inbound window 1 supports only a 32-bit base address and does not
* define an inbound window base extended address register.
*/
struct pci_inbound_window_regs piw[3];
__be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */
u8 res21[4];
__be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */
u8 res22[4];
__be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */
u8 res23[12];
__be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */
u8 res24[4];
__be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */
__be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */
__be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */
__be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */
};
extern int fsl_add_bridge(struct device_node *dev, int is_primary);
extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
#endif /* __POWERPC_FSL_PCI_H */
#endif /* __KERNEL__ */
arch/powerpc/sysdev/fsl_pcie.h deleted 100644 → 0
View file @ 3836df6b
/*
* MPC85xx/86xx PCI Express structure define
*
* Copyright 2007 Freescale Semiconductor, Inc
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifdef __KERNEL__
#ifndef __POWERPC_FSL_PCIE_H
#define __POWERPC_FSL_PCIE_H
/* PCIE Express IO block registers in 85xx/86xx */
struct ccsr_pex {
__be32 __iomem pex_config_addr; /* 0x.000 - PCI Express Configuration Address Register */
__be32 __iomem pex_config_data; /* 0x.004 - PCI Express Configuration Data Register */
u8 __iomem res1[4];
__be32 __iomem pex_otb_cpl_tor; /* 0x.00c - PCI Express Outbound completion timeout register */
__be32 __iomem pex_conf_tor; /* 0x.010 - PCI Express configuration timeout register */
u8 __iomem res2[12];
__be32 __iomem pex_pme_mes_dr; /* 0x.020 - PCI Express PME and message detect register */
__be32 __iomem pex_pme_mes_disr; /* 0x.024 - PCI Express PME and message disable register */
__be32 __iomem pex_pme_mes_ier; /* 0x.028 - PCI Express PME and message interrupt enable register */
__be32 __iomem pex_pmcr; /* 0x.02c - PCI Express power management command register */
u8 __iomem res3[3024];
__be32 __iomem pexotar0; /* 0x.c00 - PCI Express outbound translation address register 0 */
__be32 __iomem pexotear0; /* 0x.c04 - PCI Express outbound translation extended address register 0*/
u8 __iomem res4[8];
__be32 __iomem pexowar0; /* 0x.c10 - PCI Express outbound window attributes register 0*/
u8 __iomem res5[12];
__be32 __iomem pexotar1; /* 0x.c20 - PCI Express outbound translation address register 1 */
__be32 __iomem pexotear1; /* 0x.c24 - PCI Express outbound translation extended address register 1*/
__be32 __iomem pexowbar1; /* 0x.c28 - PCI Express outbound window base address register 1*/
u8 __iomem res6[4];
__be32 __iomem pexowar1; /* 0x.c30 - PCI Express outbound window attributes register 1*/
u8 __iomem res7[12];
__be32 __iomem pexotar2; /* 0x.c40 - PCI Express outbound translation address register 2 */
__be32 __iomem pexotear2; /* 0x.c44 - PCI Express outbound translation extended address register 2*/
__be32 __iomem pexowbar2; /* 0x.c48 - PCI Express outbound window base address register 2*/
u8 __iomem res8[4];
__be32 __iomem pexowar2; /* 0x.c50 - PCI Express outbound window attributes register 2*/
u8 __iomem res9[12];
__be32 __iomem pexotar3; /* 0x.c60 - PCI Express outbound translation address register 3 */
__be32 __iomem pexotear3; /* 0x.c64 - PCI Express outbound translation extended address register 3*/
__be32 __iomem pexowbar3; /* 0x.c68 - PCI Express outbound window base address register 3*/
u8 __iomem res10[4];
__be32 __iomem pexowar3; /* 0x.c70 - PCI Express outbound window attributes register 3*/
u8 __iomem res11[12];
__be32 __iomem pexotar4; /* 0x.c80 - PCI Express outbound translation address register 4 */
__be32 __iomem pexotear4; /* 0x.c84 - PCI Express outbound translation extended address register 4*/
__be32 __iomem pexowbar4; /* 0x.c88 - PCI Express outbound window base address register 4*/
u8 __iomem res12[4];
__be32 __iomem pexowar4; /* 0x.c90 - PCI Express outbound window attributes register 4*/
u8 __iomem res13[12];
u8 __iomem res14[256];
__be32 __iomem pexitar3; /* 0x.da0 - PCI Express inbound translation address register 3 */
u8 __iomem res15[4];
__be32 __iomem pexiwbar3; /* 0x.da8 - PCI Express inbound window base address register 3 */
__be32 __iomem pexiwbear3; /* 0x.dac - PCI Express inbound window base extended address register 3 */
__be32 __iomem pexiwar3; /* 0x.db0 - PCI Express inbound window attributes register 3 */
u8 __iomem res16[12];
__be32 __iomem pexitar2; /* 0x.dc0 - PCI Express inbound translation address register 2 */
u8 __iomem res17[4];
__be32 __iomem pexiwbar2; /* 0x.dc8 - PCI Express inbound window base address register 2 */
__be32 __iomem pexiwbear2; /* 0x.dcc - PCI Express inbound window base extended address register 2 */
__be32 __iomem pexiwar2; /* 0x.dd0 - PCI Express inbound window attributes register 2 */
u8 __iomem res18[12];
__be32 __iomem pexitar1; /* 0x.de0 - PCI Express inbound translation address register 2 */
u8 __iomem res19[4];
__be32 __iomem pexiwbar1; /* 0x.de8 - PCI Express inbound window base address register 2 */
__be32 __iomem pexiwbear1; /* 0x.dec - PCI Express inbound window base extended address register 2 */
__be32 __iomem pexiwar1; /* 0x.df0 - PCI Express inbound window attributes register 2 */
u8 __iomem res20[12];
__be32 __iomem pex_err_dr; /* 0x.e00 - PCI Express error detect register */
u8 __iomem res21[4];
__be32 __iomem pex_err_en; /* 0x.e08 - PCI Express error interrupt enable register */
u8 __iomem res22[4];
__be32 __iomem pex_err_disr; /* 0x.e10 - PCI Express error disable register */
u8 __iomem res23[12];
__be32 __iomem pex_err_cap_stat; /* 0x.e20 - PCI Express error capture status register */
u8 __iomem res24[4];
__be32 __iomem pex_err_cap_r0; /* 0x.e28 - PCI Express error capture register 0 */
__be32 __iomem pex_err_cap_r1; /* 0x.e2c - PCI Express error capture register 0 */
__be32 __iomem pex_err_cap_r2; /* 0x.e30 - PCI Express error capture register 0 */
__be32 __iomem pex_err_cap_r3; /* 0x.e34 - PCI Express error capture register 0 */
};
#endif /* __POWERPC_FSL_PCIE_H */
#endif /* __KERNEL__ */
arch/powerpc/sysdev/grackle.c
View file @ 0de085bb
...@@ -55,7 +55,7 @@ static inline void grackle_set_loop_snoop(struct pci_controller *bp, int enable) ...@@ -55,7 +55,7 @@ static inline void grackle_set_loop_snoop(struct pci_controller *bp, int enable)
void __init setup_grackle(struct pci_controller *hose) void __init setup_grackle(struct pci_controller *hose)
{ {
setup_indirect_pci(hose, 0xfec00000, 0xfee00000); setup_indirect_pci(hose, 0xfec00000, 0xfee00000, 0);
if (machine_is_compatible("PowerMac1,1")) if (machine_is_compatible("PowerMac1,1"))
pci_assign_all_buses = 1; pci_assign_all_buses = 1;
if (machine_is_compatible("AAPL,PowerBook1998")) if (machine_is_compatible("AAPL,PowerBook1998"))
......
arch/powerpc/sysdev/indirect_pci.c
View file @ 0de085bb
...@@ -20,12 +20,6 @@ ...@@ -20,12 +20,6 @@
#include <asm/pci-bridge.h> #include <asm/pci-bridge.h>
#include <asm/machdep.h> #include <asm/machdep.h>
#ifdef CONFIG_PPC_INDIRECT_PCI_BE
#define PCI_CFG_OUT out_be32
#else
#define PCI_CFG_OUT out_le32
#endif
static int static int
indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
int len, u32 *val) int len, u32 *val)
...@@ -35,10 +29,17 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, ...@@ -35,10 +29,17 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
u8 cfg_type = 0; u8 cfg_type = 0;
u32 bus_no, reg; u32 bus_no, reg;
if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {
if (bus->number != hose->first_busno)
return PCIBIOS_DEVICE_NOT_FOUND;
if (devfn != 0)
return PCIBIOS_DEVICE_NOT_FOUND;
}
if (ppc_md.pci_exclude_device) if (ppc_md.pci_exclude_device)
if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
return PCIBIOS_DEVICE_NOT_FOUND; return PCIBIOS_DEVICE_NOT_FOUND;
if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE) if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE)
if (bus->number != hose->first_busno) if (bus->number != hose->first_busno)
cfg_type = 1; cfg_type = 1;
...@@ -51,9 +52,12 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, ...@@ -51,9 +52,12 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
else else
reg = offset & 0xfc; reg = offset & 0xfc;
PCI_CFG_OUT(hose->cfg_addr, if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN)
(0x80000000 | (bus_no << 16) out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
| (devfn << 8) | reg | cfg_type)); (devfn << 8) | reg | cfg_type));
else
out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
(devfn << 8) | reg | cfg_type));
/* /*
* Note: the caller has already checked that offset is * Note: the caller has already checked that offset is
...@@ -83,6 +87,13 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset, ...@@ -83,6 +87,13 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
u8 cfg_type = 0; u8 cfg_type = 0;
u32 bus_no, reg; u32 bus_no, reg;
if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {
if (bus->number != hose->first_busno)
return PCIBIOS_DEVICE_NOT_FOUND;
if (devfn != 0)
return PCIBIOS_DEVICE_NOT_FOUND;
}
if (ppc_md.pci_exclude_device) if (ppc_md.pci_exclude_device)
if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
return PCIBIOS_DEVICE_NOT_FOUND; return PCIBIOS_DEVICE_NOT_FOUND;
...@@ -99,9 +110,12 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset, ...@@ -99,9 +110,12 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
else else
reg = offset & 0xfc; reg = offset & 0xfc;
PCI_CFG_OUT(hose->cfg_addr, if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN)
(0x80000000 | (bus_no << 16) out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
| (devfn << 8) | reg | cfg_type)); (devfn << 8) | reg | cfg_type));
else
out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
(devfn << 8) | reg | cfg_type));
/* surpress setting of PCI_PRIMARY_BUS */ /* surpress setting of PCI_PRIMARY_BUS */
if (hose->indirect_type & PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS) if (hose->indirect_type & PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS)
...@@ -135,24 +149,15 @@ static struct pci_ops indirect_pci_ops = ...@@ -135,24 +149,15 @@ static struct pci_ops indirect_pci_ops =
}; };
void __init void __init
setup_indirect_pci_nomap(struct pci_controller* hose, void __iomem * cfg_addr, setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data, u32 flags)
void __iomem * cfg_data)
{
hose->cfg_addr = cfg_addr;
hose->cfg_data = cfg_data;
hose->ops = &indirect_pci_ops;
}
void __init
setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
{ {
unsigned long base = cfg_addr & PAGE_MASK; unsigned long base = cfg_addr & PAGE_MASK;
void __iomem *mbase, *addr, *data; void __iomem *mbase;
mbase = ioremap(base, PAGE_SIZE); mbase = ioremap(base, PAGE_SIZE);
addr = mbase + (cfg_addr & ~PAGE_MASK); hose->cfg_addr = mbase + (cfg_addr & ~PAGE_MASK);
if ((cfg_data & PAGE_MASK) != base) if ((cfg_data & PAGE_MASK) != base)
mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE); mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);
data = mbase + (cfg_data & ~PAGE_MASK); hose->cfg_data = mbase + (cfg_data & ~PAGE_MASK);
setup_indirect_pci_nomap(hose, addr, data); hose->ops = &indirect_pci_ops;
} }
arch/powerpc/sysdev/mv64x60_pci.c
View file @ 0de085bb
...@@ -144,7 +144,7 @@ static int __init mv64x60_add_bridge(struct device_node *dev) ...@@ -144,7 +144,7 @@ static int __init mv64x60_add_bridge(struct device_node *dev)
hose->first_busno = bus_range ? bus_range[0] : 0; hose->first_busno = bus_range ? bus_range[0] : 0;
hose->last_busno = bus_range ? bus_range[1] : 0xff; hose->last_busno = bus_range ? bus_range[1] : 0xff;
setup_indirect_pci(hose, rsrc.start, rsrc.start + 4); setup_indirect_pci(hose, rsrc.start, rsrc.start + 4, 0);
hose->self_busno = hose->first_busno; hose->self_busno = hose->first_busno;
printk(KERN_INFO "Found MV64x60 PCI host bridge at 0x%016llx. " printk(KERN_INFO "Found MV64x60 PCI host bridge at 0x%016llx. "
......
include/asm-powerpc/pci-bridge.h
View file @ 0de085bb
...@@ -45,10 +45,17 @@ struct pci_controller { ...@@ -45,10 +45,17 @@ struct pci_controller {
* on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
* to determine which bus number to match on when generating type0 * to determine which bus number to match on when generating type0
* config cycles * config cycles
* NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
* hanging if we don't have link and try to do config cycles to
* anything but the PHB. Only allow talking to the PHB if this is
* set.
* BIG_ENDIAN - cfg_addr is a big endian register
*/ */
#define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001) #define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001)
#define PPC_INDIRECT_TYPE_EXT_REG (0x00000002) #define PPC_INDIRECT_TYPE_EXT_REG (0x00000002)
#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004) #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004)
#define PPC_INDIRECT_TYPE_NO_PCIE_LINK (0x00000008)
#define PPC_INDIRECT_TYPE_BIG_ENDIAN (0x00000010)
u32 indirect_type; u32 indirect_type;
/* Currently, we limit ourselves to 1 IO range and 3 mem /* Currently, we limit ourselves to 1 IO range and 3 mem
...@@ -79,11 +86,14 @@ int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn, ...@@ -79,11 +86,14 @@ int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn,
int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn, int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
int where, u32 val); int where, u32 val);
extern void setup_indirect_pci_nomap(struct pci_controller* hose, extern int early_find_capability(struct pci_controller *hose, int bus,
void __iomem *cfg_addr, void __iomem *cfg_data); int dev_fn, int cap);
extern void setup_indirect_pci(struct pci_controller* hose, extern void setup_indirect_pci(struct pci_controller* hose,
u32 cfg_addr, u32 cfg_data); u32 cfg_addr, u32 cfg_data, u32 flags);
extern void setup_grackle(struct pci_controller *hose); extern void setup_grackle(struct pci_controller *hose);
extern void __init update_bridge_resource(struct pci_dev *dev,
struct resource *res);
#else #else
......
include/linux/pci_ids.h
View file @ 0de085bb
...@@ -2079,6 +2079,23 @@ ...@@ -2079,6 +2079,23 @@
#define PCI_VENDOR_ID_TDI 0x192E #define PCI_VENDOR_ID_TDI 0x192E
#define PCI_DEVICE_ID_TDI_EHCI 0x0101 #define PCI_DEVICE_ID_TDI_EHCI 0x0101
#define PCI_VENDOR_ID_FREESCALE 0x1957
#define PCI_DEVICE_ID_MPC8548E 0x0012
#define PCI_DEVICE_ID_MPC8548 0x0013
#define PCI_DEVICE_ID_MPC8543E 0x0014
#define PCI_DEVICE_ID_MPC8543 0x0015
#define PCI_DEVICE_ID_MPC8547E 0x0018
#define PCI_DEVICE_ID_MPC8545E 0x0019
#define PCI_DEVICE_ID_MPC8545 0x001a
#define PCI_DEVICE_ID_MPC8568E 0x0020
#define PCI_DEVICE_ID_MPC8568 0x0021
#define PCI_DEVICE_ID_MPC8567E 0x0022
#define PCI_DEVICE_ID_MPC8567 0x0023
#define PCI_DEVICE_ID_MPC8544E 0x0030
#define PCI_DEVICE_ID_MPC8544 0x0031
#define PCI_DEVICE_ID_MPC8641 0x7010
#define PCI_DEVICE_ID_MPC8641D 0x7011
#define PCI_VENDOR_ID_PASEMI 0x1959 #define PCI_VENDOR_ID_PASEMI 0x1959
#define PCI_VENDOR_ID_ATTANSIC 0x1969 #define PCI_VENDOR_ID_ATTANSIC 0x1969
......
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