Commit 0e0c4db2 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven

soc: renesas: r8a7795-sysc: Fix power request conflicts

Describe the location and contents of the SYSCEXTMASK register on R-Car
H3, to prevent conflicts between internal and external power requests.

This register does not exist on R-Car H3 ES1.x and ES2.x.

Based on a patch in the BSP by Dien Pham <dien.pham.ry@renesas.com>.
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: default avatarSimon Horman <horms+renesas@verge.net.au>
Link: https://lore.kernel.org/r/20190828113618.6672-3-geert+renesas@glider.be
parent 44b5100f
...@@ -5,6 +5,7 @@ ...@@ -5,6 +5,7 @@
* Copyright (C) 2016-2017 Glider bvba * Copyright (C) 2016-2017 Glider bvba
*/ */
#include <linux/bits.h>
#include <linux/bug.h> #include <linux/bug.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/sys_soc.h> #include <linux/sys_soc.h>
...@@ -51,25 +52,46 @@ static struct rcar_sysc_area r8a7795_areas[] __initdata = { ...@@ -51,25 +52,46 @@ static struct rcar_sysc_area r8a7795_areas[] __initdata = {
/* /*
* Fixups for R-Car H3 revisions after ES1.x * Fixups for R-Car H3 revisions
*/ */
static const struct soc_device_attribute r8a7795es1[] __initconst = { #define HAS_A2VC0 BIT(0) /* Power domain A2VC0 is present */
{ .soc_id = "r8a7795", .revision = "ES1.*" }, #define NO_EXTMASK BIT(1) /* Missing SYSCEXTMASK register */
static const struct soc_device_attribute r8a7795_quirks_match[] __initconst = {
{
.soc_id = "r8a7795", .revision = "ES1.*",
.data = (void *)(HAS_A2VC0 | NO_EXTMASK),
}, {
.soc_id = "r8a7795", .revision = "ES2.*",
.data = (void *)(NO_EXTMASK),
},
{ /* sentinel */ } { /* sentinel */ }
}; };
static int __init r8a7795_sysc_init(void) static int __init r8a7795_sysc_init(void)
{ {
if (!soc_device_match(r8a7795es1)) const struct soc_device_attribute *attr;
u32 quirks = 0;
attr = soc_device_match(r8a7795_quirks_match);
if (attr)
quirks = (uintptr_t)attr->data;
if (!(quirks & HAS_A2VC0))
rcar_sysc_nullify(r8a7795_areas, ARRAY_SIZE(r8a7795_areas), rcar_sysc_nullify(r8a7795_areas, ARRAY_SIZE(r8a7795_areas),
R8A7795_PD_A2VC0); R8A7795_PD_A2VC0);
if (quirks & NO_EXTMASK)
r8a7795_sysc_info.extmask_val = 0;
return 0; return 0;
} }
const struct rcar_sysc_info r8a7795_sysc_info __initconst = { struct rcar_sysc_info r8a7795_sysc_info __initdata = {
.init = r8a7795_sysc_init, .init = r8a7795_sysc_init,
.areas = r8a7795_areas, .areas = r8a7795_areas,
.num_areas = ARRAY_SIZE(r8a7795_areas), .num_areas = ARRAY_SIZE(r8a7795_areas),
.extmask_offs = 0x2f8,
.extmask_val = BIT(0),
}; };
...@@ -59,7 +59,7 @@ extern const struct rcar_sysc_info r8a7790_sysc_info; ...@@ -59,7 +59,7 @@ extern const struct rcar_sysc_info r8a7790_sysc_info;
extern const struct rcar_sysc_info r8a7791_sysc_info; extern const struct rcar_sysc_info r8a7791_sysc_info;
extern const struct rcar_sysc_info r8a7792_sysc_info; extern const struct rcar_sysc_info r8a7792_sysc_info;
extern const struct rcar_sysc_info r8a7794_sysc_info; extern const struct rcar_sysc_info r8a7794_sysc_info;
extern const struct rcar_sysc_info r8a7795_sysc_info; extern struct rcar_sysc_info r8a7795_sysc_info;
extern const struct rcar_sysc_info r8a7796_sysc_info; extern const struct rcar_sysc_info r8a7796_sysc_info;
extern const struct rcar_sysc_info r8a77965_sysc_info; extern const struct rcar_sysc_info r8a77965_sysc_info;
extern const struct rcar_sysc_info r8a77970_sysc_info; extern const struct rcar_sysc_info r8a77970_sysc_info;
......
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