Commit 0e9c026f authored by Gayatri Kammela's avatar Gayatri Kammela Committed by Andy Shevchenko

platform/x86: intel_pmc_core: Add slp_s0_offset attribute back to tgl_reg_map

If platforms such as Tiger Lake has sub-states of S0ix, then attributes
such as slps0_dbg_offset become invalid. But slp_s0_offset is still
valid as it is used to get the pmcdev_base_addr.

Hence, add back slp_s0_offset and remove slps0_dbg_offset attributes.

Cc: Chen Zhou <chenzhou10@huawei.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: David E. Box <david.e.box@intel.com>
Signed-off-by: default avatarGayatri Kammela <gayatri.kammela@intel.com>
Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
parent 08ec5020
...@@ -556,9 +556,9 @@ static const struct pmc_bit_map *tgl_lpm_maps[] = { ...@@ -556,9 +556,9 @@ static const struct pmc_bit_map *tgl_lpm_maps[] = {
static const struct pmc_reg_map tgl_reg_map = { static const struct pmc_reg_map tgl_reg_map = {
.pfear_sts = ext_tgl_pfear_map, .pfear_sts = ext_tgl_pfear_map,
.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
.ltr_show_sts = cnp_ltr_show_map, .ltr_show_sts = cnp_ltr_show_map,
.msr_sts = msr_map, .msr_sts = msr_map,
.slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
.regmap_length = CNP_PMC_MMIO_REG_LEN, .regmap_length = CNP_PMC_MMIO_REG_LEN,
.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A, .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
......
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