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Commit 0ebf7dc4 authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'samsung-dt-s3c64xx' of... 

Merge tag 'samsung-dt-s3c64xx' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt

From Kukjin Kim:

Add device tree support for S3C64XX
- add device tree infrastructure for s3c64xx
- add DT SoC file for s3c64xx
- add DT board file for FriendlyARM Mini6410 board
- add DT board file for SAMSUNG SMDK6410

Based on Common Clk Framework for S3C64XX

* tag 'samsung-dt-s3c64xx' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: dts: Add dts file for S3C6410-based SMDK6410 board
  ARM: dts: Add dts file for S3C6410-based Mini6410 board
  ARM: dts: Add basic dts include files for Samsung S3C64xx SoCs
  ARM: S3C64XX: Add board file for boot using Device Tree
  gpio: samsung: Skip initialization if device tree is present
  ARM: S3C64XX: Bypass legacy initialization when booting with DT
  irqchip: vic: Parse interrupt and resume masks from device tree
  ARM: S3C64XX: Remove old clock management code
  ARM: S3C64XX: Migrate clock handling to Common Clock Framework
  usb: ohci-s3c2410.c: Use clk_prepare_enable/clk_disable_unprepare
  ARM: S3C64XX: Use clk_prepare_enable/clk_disable_unprepare in dma.c
  ARM: SAMSUNG: Add soc_is_s3c6400/s3c6410 macros
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 4a10c2ac 2ec35a42
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Documentation/devicetree/bindings/arm/vic.txt
View file @ 0ebf7dc4
......@@ -18,6 +18,15 @@ Required properties:
Optional properties:
- interrupts : Interrupt source for parent controllers if the VIC is nested.
- valid-mask : A one cell big bit mask of valid interrupt sources. Each bit
represents single interrupt source, starting from source 0 at LSb and ending
at source 31 at MSb. A bit that is set means that the source is wired and
clear means otherwise. If unspecified, defaults to all valid.
- valid-wakeup-mask : A one cell big bit mask of interrupt sources that can be
configured as wake up source for the system. Order of bits is the same as for
valid-mask property. A set bit means that this interrupt source can be
configured as a wake up source for the system. If unspecied, defaults to all
interrupt sources configurable as wake up sources.
Example:
......@@ -26,4 +35,7 @@ Example:
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x60000 0x1000>;
valid-mask = <0xffffff7f>;
valid-wakeup-mask = <0x0000ff7f>;
};
arch/arm/Kconfig
View file @ 0ebf7dc4
......@@ -727,6 +727,7 @@ config ARCH_S3C64XX
select ARM_VIC
select CLKDEV_LOOKUP
select CLKSRC_SAMSUNG_PWM
select COMMON_CLK
select CPU_V6
select GENERIC_CLOCKEVENTS
select GPIO_SAMSUNG
......@@ -740,7 +741,6 @@ config ARCH_S3C64XX
select S3C_DEV_NAND
select S3C_GPIO_TRACK
select SAMSUNG_ATAGS
select SAMSUNG_CLKSRC
select SAMSUNG_GPIOLIB_4BIT
select SAMSUNG_WDT_RESET
select USB_ARCH_HAS_OHCI
......
arch/arm/boot/dts/Makefile
View file @ 0ebf7dc4
......@@ -195,6 +195,8 @@ dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
ste-ccu8540.dtb \
ste-ccu9540.dtb
dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \
s3c6410-smdk6410.dtb
dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
emev2-kzm9d-reference.dtb \
r8a7740-armadillo800eva.dtb \
......
arch/arm/boot/dts/s3c6400.dtsi 0 → 100644
View file @ 0ebf7dc4
/*
* Samsung's S3C6400 SoC device tree source
*
* Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
*
* Samsung's S3C6400 SoC device nodes are listed in this file. S3C6400
* based board files can include this file and provide values for board specfic
* bindings.
*
* Note: This file does not include device nodes for all the controllers in
* S3C6400 SoC. As device tree coverage for S3C6400 increases, additional
* nodes can be added to this file.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "s3c64xx.dtsi"
/ {
compatible = "samsung,s3c6400";
};
&vic0 {
valid-mask = <0xfffffe1f>;
valid-wakeup-mask = <0x00200004>;
};
&vic1 {
valid-mask = <0xffffffff>;
valid-wakeup-mask = <0x53020000>;
};
&soc {
clocks: clock-controller@7e00f000 {
compatible = "samsung,s3c6400-clock";
reg = <0x7e00f000 0x1000>;
#clock-cells = <1>;
};
};
arch/arm/boot/dts/s3c6410-mini6410.dts 0 → 100644
View file @ 0ebf7dc4
/*
* Samsung's S3C6410 based Mini6410 board device tree source
*
* Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
*
* Device tree source file for FriendlyARM Mini6410 board which is based on
* Samsung's S3C6410 SoC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "s3c6410.dtsi"
/ {
model = "FriendlyARM Mini6410 board based on S3C6410";
compatible = "friendlyarm,mini6410", "samsung,s3c6410";
memory {
reg = <0x50000000 0x10000000>;
};
chosen {
bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1";
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
fin_pll: oscillator@0 {
compatible = "fixed-clock";
reg = <0>;
clock-frequency = <12000000>;
clock-output-names = "fin_pll";
#clock-cells = <0>;
};
xusbxti: oscillator@1 {
compatible = "fixed-clock";
reg = <1>;
clock-output-names = "xusbxti";
clock-frequency = <48000000>;
#clock-cells = <0>;
};
};
srom-cs1@18000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x18000000 0x8000000>;
ranges;
ethernet@18000000 {
compatible = "davicom,dm9000";
reg = <0x18000000 0x2 0x18000004 0x2>;
interrupt-parent = <&gpn>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
davicom,no-eeprom;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys>;
autorepeat;
button-k1 {
label = "K1";
gpios = <&gpn 0 GPIO_ACTIVE_LOW>;
linux,code = <2>;
debounce-interval = <20>;
};
button-k2 {
label = "K2";
gpios = <&gpn 1 GPIO_ACTIVE_LOW>;
linux,code = <3>;
debounce-interval = <20>;
};
button-k3 {
label = "K3";
gpios = <&gpn 2 GPIO_ACTIVE_LOW>;
linux,code = <4>;
debounce-interval = <20>;
};
button-k4 {
label = "K4";
gpios = <&gpn 3 GPIO_ACTIVE_LOW>;
linux,code = <5>;
debounce-interval = <20>;
};
button-k5 {
label = "K5";
gpios = <&gpn 4 GPIO_ACTIVE_LOW>;
linux,code = <6>;
debounce-interval = <20>;
};
button-k6 {
label = "K6";
gpios = <&gpn 5 GPIO_ACTIVE_LOW>;
linux,code = <7>;
debounce-interval = <20>;
};
button-k7 {
label = "K7";
gpios = <&gpl 11 GPIO_ACTIVE_LOW>;
linux,code = <8>;
debounce-interval = <20>;
};
button-k8 {
label = "K8";
gpios = <&gpl 12 GPIO_ACTIVE_LOW>;
linux,code = <9>;
debounce-interval = <20>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&gpio_leds>;
led-1 {
label = "LED1";
gpios = <&gpk 4 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
led-2 {
label = "LED2";
gpios = <&gpk 5 GPIO_ACTIVE_LOW>;
linux,default-trigger = "mmc0";
};
led-3 {
label = "LED3";
gpios = <&gpk 6 GPIO_ACTIVE_LOW>;
};
led-4 {
label = "LED4";
gpios = <&gpk 7 GPIO_ACTIVE_LOW>;
};
};
buzzer {
compatible = "pwm-beeper";
pwms = <&pwm 0 1000000 0>;
pinctrl-names = "default";
pinctrl-0 = <&pwm0_out>;
};
};
&sdhci0 {
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
bus-width = <4>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_data>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_data>, <&uart1_fctl>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_data>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_data>;
status = "okay";
};
&pwm {
status = "okay";
};
&pinctrl0 {
gpio_leds: gpio-leds {
samsung,pins = "gpk-4", "gpk-5", "gpk-6", "gpk-7";
samsung,pin-pud = <PIN_PULL_NONE>;
};
gpio_keys: gpio-keys {
samsung,pins = "gpn-0", "gpn-1", "gpn-2", "gpn-3",
"gpn-4", "gpn-5", "gpl-11", "gpl-12";
samsung,pin-pud = <PIN_PULL_NONE>;
};
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_bus>;
status = "okay";
eeprom@50 {
compatible = "atmel,24c08";
reg = <0x50>;
pagesize = <16>;
};
};
arch/arm/boot/dts/s3c6410-smdk6410.dts 0 → 100644
View file @ 0ebf7dc4
/*
* Samsung S3C6410 based SMDK6410 board device tree source.
*
* Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
*
* Device tree source file for SAMSUNG SMDK6410 board which is based on
* Samsung's S3C6410 SoC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "s3c6410.dtsi"
/ {
model = "SAMSUNG SMDK6410 board based on S3C6410";
compatible = "samsung,mini6410", "samsung,s3c6410";
memory {
reg = <0x50000000 0x8000000>;
};
chosen {
bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1";
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
fin_pll: oscillator@0 {
compatible = "fixed-clock";
reg = <0>;
clock-frequency = <12000000>;
clock-output-names = "fin_pll";
#clock-cells = <0>;
};
xusbxti: oscillator@1 {
compatible = "fixed-clock";
reg = <1>;
clock-output-names = "xusbxti";
clock-frequency = <48000000>;
#clock-cells = <0>;
};
};
srom-cs1@18000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x18000000 0x8000000>;
ranges;
ethernet@18000000 {
compatible = "smsc,lan9115";
reg = <0x18000000 0x10000>;
interrupt-parent = <&gpn>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
phy-mode = "mii";
reg-io-width = <4>;
smsc,force-internal-phy;
};
};
};
&sdhci0 {
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;
bus-width = <4>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_data>, <&uart0_fctl>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_data>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_data>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_data>;
status = "okay";
};
arch/arm/boot/dts/s3c6410.dtsi 0 → 100644
View file @ 0ebf7dc4
/*
* Samsung's S3C6410 SoC device tree source
*
* Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
*
* Samsung's S3C6410 SoC device nodes are listed in this file. S3C6410
* based board files can include this file and provide values for board specfic
* bindings.
*
* Note: This file does not include device nodes for all the controllers in
* S3C6410 SoC. As device tree coverage for S3C6410 increases, additional
* nodes can be added to this file.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "s3c64xx.dtsi"
/ {
compatible = "samsung,s3c6410";
aliases {
i2c1 = &i2c1;
};
};
&vic0 {
valid-mask = <0xffffff7f>;
valid-wakeup-mask = <0x00200004>;
};
&vic1 {
valid-mask = <0xffffffff>;
valid-wakeup-mask = <0x53020000>;
};
&soc {
clocks: clock-controller@7e00f000 {
compatible = "samsung,s3c6410-clock";
reg = <0x7e00f000 0x1000>;
#clock-cells = <1>;
};
i2c1: i2c@7f00f000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x7f00f000 0x1000>;
interrupt-parent = <&vic0>;
interrupts = <5>;
clock-names = "i2c";
clocks = <&clocks PCLK_IIC1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
};
arch/arm/boot/dts/s3c64xx-pinctrl.dtsi 0 → 100644
View file @ 0ebf7dc4
/*
* Samsung's S3C64xx SoC series common device tree source
* - pin control-related definitions
*
* Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
*
* Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are
* listed as device tree nodes in this file.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define PIN_PULL_NONE 0
#define PIN_PULL_DOWN 1
#define PIN_PULL_UP 2
&pinctrl0 {
/*
* Pin banks
*/
gpa: gpa {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpb: gpb {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc: gpc {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpd: gpd {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpe: gpe {
gpio-controller;
#gpio-cells = <2>;
};
gpf: gpf {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpg: gpg {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gph: gph {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpi: gpi {
gpio-controller;
#gpio-cells = <2>;
};
gpj: gpj {
gpio-controller;
#gpio-cells = <2>;
};
gpk: gpk {
gpio-controller;
#gpio-cells = <2>;
};
gpl: gpl {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpm: gpm {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpn: gpn {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpo: gpo {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpp: gpp {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpq: gpq {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
/*
* Pin groups
*/
uart0_data: uart0-data {
samsung,pins = "gpa-0", "gpa-1";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
uart0_fctl: uart0-fctl {
samsung,pins = "gpa-2", "gpa-3";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
uart1_data: uart1-data {
samsung,pins = "gpa-4", "gpa-5";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
uart1_fctl: uart1-fctl {
samsung,pins = "gpa-6", "gpa-7";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
uart2_data: uart2-data {
samsung,pins = "gpb-0", "gpb-1";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
uart3_data: uart3-data {
samsung,pins = "gpb-2", "gpb-3";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
ext_dma_0: ext-dma-0 {
samsung,pins = "gpb-0", "gpb-1";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
ext_dma_1: ext-dma-1 {
samsung,pins = "gpb-2", "gpb-3";
samsung,pin-function = <4>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
irda_data_0: irda-data-0 {
samsung,pins = "gpb-0", "gpb-1";
samsung,pin-function = <4>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
irda_data_1: irda-data-1 {
samsung,pins = "gpb-2", "gpb-3";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
irda_sdbw: irda-sdbw {
samsung,pins = "gpb-4";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
i2c0_bus: i2c0-bus {
samsung,pins = "gpb-5", "gpb-6";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
};
i2c1_bus: i2c1-bus {
/* S3C6410-only */
samsung,pins = "gpb-2", "gpb-3";
samsung,pin-function = <6>;
samsung,pin-pud = <PIN_PULL_UP>;
};
spi0_bus: spi0-bus {
samsung,pins = "gpc-0", "gpc-1", "gpc-2";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
};
spi0_cs: spi0-cs {
samsung,pins = "gpc-3";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
spi1_bus: spi1-bus {
samsung,pins = "gpc-4", "gpc-5", "gpc-6";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
};
spi1_cs: spi1-cs {
samsung,pins = "gpc-7";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
sd0_cmd: sd0-cmd {
samsung,pins = "gpg-1";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
sd0_clk: sd0-clk {
samsung,pins = "gpg-0";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
sd0_bus1: sd0-bus1 {
samsung,pins = "gpg-2";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
sd0_bus4: sd0-bus4 {
samsung,pins = "gpg-2", "gpg-3", "gpg-4", "gpg-5";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
sd0_cd: sd0-cd {
samsung,pins = "gpg-6";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_UP>;
};
sd1_cmd: sd1-cmd {
samsung,pins = "gph-1";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
sd1_clk: sd1-clk {
samsung,pins = "gph-0";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
sd1_bus1: sd1-bus1 {
samsung,pins = "gph-2";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
sd1_bus4: sd1-bus4 {
samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
sd1_bus8: sd1-bus8 {
samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5",
"gph-6", "gph-7", "gph-8", "gph-9";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
sd1_cd: sd1-cd {
samsung,pins = "gpg-6";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_UP>;
};
sd2_cmd: sd2-cmd {
samsung,pins = "gpc-4";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
sd2_clk: sd2-clk {
samsung,pins = "gpc-5";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
sd2_bus1: sd2-bus1 {
samsung,pins = "gph-6";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
sd2_bus4: sd2-bus4 {
samsung,pins = "gph-6", "gph-7", "gph-8", "gph-9";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
i2s0_bus: i2s0-bus {
samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
i2s0_cdclk: i2s0-cdclk {
samsung,pins = "gpd-1";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
i2s1_bus: i2s1-bus {
samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
i2s1_cdclk: i2s1-cdclk {
samsung,pins = "gpe-1";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
i2s2_bus: i2s2-bus {
/* S3C6410-only */
samsung,pins = "gpc-4", "gpc-5", "gpc-6", "gph-6",
"gph-8", "gph-9";
samsung,pin-function = <5>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
i2s2_cdclk: i2s2-cdclk {
/* S3C6410-only */
samsung,pins = "gph-7";
samsung,pin-function = <5>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
pcm0_bus: pcm0-bus {
samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
pcm0_extclk: pcm0-extclk {
samsung,pins = "gpd-1";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
pcm1_bus: pcm1-bus {
samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
pcm1_extclk: pcm1-extclk {
samsung,pins = "gpe-1";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
ac97_bus_0: ac97-bus-0 {
samsung,pins = "gpd-0", "gpd-1", "gpd-2", "gpd-3", "gpd-4";
samsung,pin-function = <4>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
ac97_bus_1: ac97-bus-1 {
samsung,pins = "gpe-0", "gpe-1", "gpe-2", "gpe-3", "gpe-4";
samsung,pin-function = <4>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
cam_port: cam-port {
samsung,pins = "gpf-0", "gpf-1", "gpf-2", "gpf-4",
"gpf-5", "gpf-6", "gpf-7", "gpf-8",
"gpf-9", "gpf-10", "gpf-11", "gpf-12";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
cam_rst: cam-rst {
samsung,pins = "gpf-3";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
cam_field: cam-field {
/* S3C6410-only */
samsung,pins = "gpb-4";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
pwm_extclk: pwm-extclk {
samsung,pins = "gpf-13";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
pwm0_out: pwm0-out {
samsung,pins = "gpf-14";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
pwm1_out: pwm1-out {
samsung,pins = "gpf-15";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
clkout0: clkout-0 {
samsung,pins = "gpf-14";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_col0_0: keypad-col0-0 {
samsung,pins = "gph-0";
samsung,pin-function = <4>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_col1_0: keypad-col1-0 {
samsung,pins = "gph-1";
samsung,pin-function = <4>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_col2_0: keypad-col2-0 {
samsung,pins = "gph-2";
samsung,pin-function = <4>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_col3_0: keypad-col3-0 {
samsung,pins = "gph-3";
samsung,pin-function = <4>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_col4_0: keypad-col4-0 {
samsung,pins = "gph-4";
samsung,pin-function = <4>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_col5_0: keypad-col5-0 {
samsung,pins = "gph-5";
samsung,pin-function = <4>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_col6_0: keypad-col6-0 {
samsung,pins = "gph-6";
samsung,pin-function = <4>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_col7_0: keypad-col7-0 {
samsung,pins = "gph-7";
samsung,pin-function = <4>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_col0_1: keypad-col0-1 {
samsung,pins = "gpl-0";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_col1_1: keypad-col1-1 {
samsung,pins = "gpl-1";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_col2_1: keypad-col2-1 {
samsung,pins = "gpl-2";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_col3_1: keypad-col3-1 {
samsung,pins = "gpl-3";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_col4_1: keypad-col4-1 {
samsung,pins = "gpl-4";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_col5_1: keypad-col5-1 {
samsung,pins = "gpl-5";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_col6_1: keypad-col6-1 {
samsung,pins = "gpl-6";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_col7_1: keypad-col7-1 {
samsung,pins = "gpl-7";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_row0_0: keypad-row0-0 {
samsung,pins = "gpk-8";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_row1_0: keypad-row1-0 {
samsung,pins = "gpk-9";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_row2_0: keypad-row2-0 {
samsung,pins = "gpk-10";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_row3_0: keypad-row3-0 {
samsung,pins = "gpk-11";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_row4_0: keypad-row4-0 {
samsung,pins = "gpk-12";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_row5_0: keypad-row5-0 {
samsung,pins = "gpk-13";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_row6_0: keypad-row6-0 {
samsung,pins = "gpk-14";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_row7_0: keypad-row7-0 {
samsung,pins = "gpk-15";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_row0_1: keypad-row0-1 {
samsung,pins = "gpn-0";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_row1_1: keypad-row1-1 {
samsung,pins = "gpn-1";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_row2_1: keypad-row2-1 {
samsung,pins = "gpn-2";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_row3_1: keypad-row3-1 {
samsung,pins = "gpn-3";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_row4_1: keypad-row4-1 {
samsung,pins = "gpn-4";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_row5_1: keypad-row5-1 {
samsung,pins = "gpn-5";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_row6_1: keypad-row6-1 {
samsung,pins = "gpn-6";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
keypad_row7_1: keypad-row7-1 {
samsung,pins = "gpn-7";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
lcd_ctrl: lcd-ctrl {
samsung,pins = "gpj-8", "gpj-9", "gpj-10", "gpj-11";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
lcd_data16: lcd-data-width16 {
samsung,pins = "gpi-3", "gpi-4", "gpi-5", "gpi-6",
"gpi-7", "gpi-10", "gpi-11", "gpi-12",
"gpi-13", "gpi-14", "gpi-15", "gpj-3",
"gpj-4", "gpj-5", "gpj-6", "gpj-7";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
lcd_data18: lcd-data-width18 {
samsung,pins = "gpi-2", "gpi-3", "gpi-4", "gpi-5",
"gpi-6", "gpi-7", "gpi-10", "gpi-11",
"gpi-12", "gpi-13", "gpi-14", "gpi-15",
"gpj-2", "gpj-3", "gpj-4", "gpj-5",
"gpj-6", "gpj-7";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
lcd_data24: lcd-data-width24 {
samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3",
"gpi-4", "gpi-5", "gpi-6", "gpi-7",
"gpi-8", "gpi-9", "gpi-10", "gpi-11",
"gpi-12", "gpi-13", "gpi-14", "gpi-15",
"gpj-0", "gpj-1", "gpj-2", "gpj-3",
"gpj-4", "gpj-5", "gpj-6", "gpj-7";
samsung,pin-function = <2>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
hsi_bus: hsi-bus {
samsung,pins = "gpk-0", "gpk-1", "gpk-2", "gpk-3",
"gpk-4", "gpk-5", "gpk-6", "gpk-7";
samsung,pin-function = <3>;
samsung,pin-pud = <PIN_PULL_NONE>;
};
};
arch/arm/boot/dts/s3c64xx.dtsi 0 → 100644
View file @ 0ebf7dc4
/*
* Samsung's S3C64xx SoC series common device tree source
*
* Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
*
* Samsung's S3C64xx SoC series device nodes are listed in this file.
* Particular SoCs from S3C64xx series can include this file and provide
* values for SoCs specfic bindings.
*
* Note: This file does not include device nodes for all the controllers in
* S3C64xx SoCs. As device tree coverage for S3C64xx increases, additional
* nodes can be added to this file.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "skeleton.dtsi"
#include <dt-bindings/clock/samsung,s3c64xx-clock.h>
/ {
aliases {
i2c0 = &i2c0;
pinctrl0 = &pinctrl0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,arm1176jzf-s", "arm,arm1176";
reg = <0x0>;
};
};
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
vic0: interrupt-controller@71200000 {
compatible = "arm,pl192-vic";
interrupt-controller;
reg = <0x71200000 0x1000>;
#interrupt-cells = <1>;
};
vic1: interrupt-controller@71300000 {
compatible = "arm,pl192-vic";
interrupt-controller;
reg = <0x71300000 0x1000>;
#interrupt-cells = <1>;
};
sdhci0: sdhci@7c200000 {
compatible = "samsung,s3c6410-sdhci";
reg = <0x7c200000 0x100>;
interrupt-parent = <&vic1>;
interrupts = <24>;
clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
<&clocks SCLK_MMC0>;
status = "disabled";
};
sdhci1: sdhci@7c300000 {
compatible = "samsung,s3c6410-sdhci";
reg = <0x7c300000 0x100>;
interrupt-parent = <&vic1>;
interrupts = <25>;
clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
<&clocks SCLK_MMC1>;
status = "disabled";
};
sdhci2: sdhci@7c400000 {
compatible = "samsung,s3c6410-sdhci";
reg = <0x7c400000 0x100>;
interrupt-parent = <&vic1>;
interrupts = <17>;
clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
clocks = <&clocks HCLK_HSMMC2>, <&clocks HCLK_HSMMC2>,
<&clocks SCLK_MMC2>;
status = "disabled";
};
watchdog: watchdog@7e004000 {
compatible = "samsung,s3c2410-wdt";
reg = <0x7e004000 0x1000>;
interrupt-parent = <&vic0>;
interrupts = <26>;
clock-names = "watchdog";
clocks = <&clocks PCLK_WDT>;
status = "disabled";
};
i2c0: i2c@7f004000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x7f004000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <18>;
clock-names = "i2c";
clocks = <&clocks PCLK_IIC0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
uart0: serial@7f005000 {
compatible = "samsung,s3c6400-uart";
reg = <0x7f005000 0x100>;
interrupt-parent = <&vic1>;
interrupts = <5>;
clock-names = "uart", "clk_uart_baud2",
"clk_uart_baud3";
clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
<&clocks SCLK_UART>;
status = "disabled";
};
uart1: serial@7f005400 {
compatible = "samsung,s3c6400-uart";
reg = <0x7f005400 0x100>;
interrupt-parent = <&vic1>;
interrupts = <6>;
clock-names = "uart", "clk_uart_baud2",
"clk_uart_baud3";
clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
<&clocks SCLK_UART>;
status = "disabled";
};
uart2: serial@7f005800 {
compatible = "samsung,s3c6400-uart";
reg = <0x7f005800 0x100>;
interrupt-parent = <&vic1>;
interrupts = <7>;
clock-names = "uart", "clk_uart_baud2",
"clk_uart_baud3";
clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
<&clocks SCLK_UART>;
status = "disabled";
};
uart3: serial@7f005c00 {
compatible = "samsung,s3c6400-uart";
reg = <0x7f005c00 0x100>;
interrupt-parent = <&vic1>;
interrupts = <8>;
clock-names = "uart", "clk_uart_baud2",
"clk_uart_baud3";
clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
<&clocks SCLK_UART>;
status = "disabled";
};
pwm: pwm@7f006000 {
compatible = "samsung,s3c6400-pwm";
reg = <0x7f006000 0x1000>;
interrupt-parent = <&vic0>;
interrupts = <23>, <24>, <25>, <27>, <28>;
clock-names = "timers";
clocks = <&clocks PCLK_PWM>;
samsung,pwm-outputs = <0>, <1>;
#pwm-cells = <3>;
status = "disabled";
};
pinctrl0: pinctrl@7f008000 {
compatible = "samsung,s3c64xx-pinctrl";
reg = <0x7f008000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <21>;
pctrl_int_map: pinctrl-interrupt-map {
interrupt-map = <0 &vic0 0>,
<1 &vic0 1>,
<2 &vic1 0>,
<3 &vic1 1>;
#address-cells = <0>;
#size-cells = <0>;
#interrupt-cells = <1>;
};
wakeup-interrupt-controller {
compatible = "samsung,s3c64xx-wakeup-eint";
interrupts = <0>, <1>, <2>, <3>;
interrupt-parent = <&pctrl_int_map>;
};
};
};
};
#include "s3c64xx-pinctrl.dtsi"
arch/arm/mach-s3c64xx/Kconfig
View file @ 0ebf7dc4
......@@ -306,3 +306,19 @@ config MACH_WLF_CRAGG_6410
select SAMSUNG_GPIO_EXTRA128
help
Machine support for the Wolfson Cragganmore S3C6410 variant.
config MACH_S3C64XX_DT
bool "Samsung S3C6400/S3C6410 machine using Device Tree"
select CLKSRC_OF
select CPU_S3C6400
select CPU_S3C6410
select PINCTRL
select PINCTRL_S3C64XX
select USE_OF
help
Machine support for Samsung S3C6400/S3C6410 machines with Device Tree
enabled.
Select this if a fdt blob is available for your S3C64XX SoC based
board.
Note: This is under development and not all peripherals can be
supported with this machine file.
arch/arm/mach-s3c64xx/Makefile
View file @ 0ebf7dc4
......@@ -12,7 +12,7 @@ obj- :=
# Core
obj-y += common.o clock.o
obj-y += common.o
# Core support
......@@ -57,3 +57,4 @@ obj-$(CONFIG_MACH_SMARTQ7) += mach-smartq7.o
obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o
obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o
obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o mach-crag6410-module.o
obj-$(CONFIG_MACH_S3C64XX_DT) += mach-s3c64xx-dt.o
arch/arm/mach-s3c64xx/clock.c deleted 100644 → 0
View file @ 4a10c2ac
/* linux/arch/arm/plat-s3c64xx/clock.c
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C64XX Base clock support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/cpu-freq.h>
#include <plat/clock.h>
#include <plat/clock-clksrc.h>
#include <plat/pll.h>
#include "regs-sys.h"
/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
* ext_xtal_mux for want of an actual name from the manual.
*/
static struct clk clk_ext_xtal_mux = {
.name = "ext_xtal",
};
#define clk_fin_apll clk_ext_xtal_mux
#define clk_fin_mpll clk_ext_xtal_mux
#define clk_fin_epll clk_ext_xtal_mux
#define clk_fout_mpll clk_mpll
#define clk_fout_epll clk_epll
struct clk clk_h2 = {
.name = "hclk2",
.rate = 0,
};
struct clk clk_27m = {
.name = "clk_27m",
.rate = 27000000,
};
static int clk_48m_ctrl(struct clk *clk, int enable)
{
unsigned long flags;
u32 val;
/* can't rely on clock lock, this register has other usages */
local_irq_save(flags);
val = __raw_readl(S3C64XX_OTHERS);
if (enable)
val |= S3C64XX_OTHERS_USBMASK;
else
val &= ~S3C64XX_OTHERS_USBMASK;
__raw_writel(val, S3C64XX_OTHERS);
local_irq_restore(flags);
return 0;
}
struct clk clk_48m = {
.name = "clk_48m",
.rate = 48000000,
.enable = clk_48m_ctrl,
};
struct clk clk_xusbxti = {
.name = "xusbxti",
.rate = 48000000,
};
static int inline s3c64xx_gate(void __iomem *reg,
struct clk *clk,
int enable)
{
unsigned int ctrlbit = clk->ctrlbit;
u32 con;
con = __raw_readl(reg);
if (enable)
con |= ctrlbit;
else
con &= ~ctrlbit;
__raw_writel(con, reg);
return 0;
}
static int s3c64xx_pclk_ctrl(struct clk *clk, int enable)
{
return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
}
static int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
{
return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
}
int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
{
return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
}
static struct clk init_clocks_off[] = {
{
.name = "nand",
.parent = &clk_h,
}, {
.name = "rtc",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_RTC,
}, {
.name = "adc",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_TSADC,
}, {
.name = "i2c",
.devname = "s3c2440-i2c.0",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIC,
}, {
.name = "i2c",
.devname = "s3c2440-i2c.1",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C6410_CLKCON_PCLK_I2C1,
}, {
.name = "keypad",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_KEYPAD,
}, {
.name = "spi",
.devname = "s3c6410-spi.0",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_SPI0,
}, {
.name = "spi",
.devname = "s3c6410-spi.1",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_SPI1,
}, {
.name = "48m",
.devname = "s3c-sdhci.0",
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
}, {
.name = "48m",
.devname = "s3c-sdhci.1",
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
}, {
.name = "48m",
.devname = "s3c-sdhci.2",
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
}, {
.name = "ac97",
.parent = &clk_p,
.ctrlbit = S3C_CLKCON_PCLK_AC97,
}, {
.name = "cfcon",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_IHOST,
}, {
.name = "dma0",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_DMA0,
}, {
.name = "dma1",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_DMA1,
}, {
.name = "3dse",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_3DSE,
}, {
.name = "hclk_secur",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_SECUR,
}, {
.name = "sdma1",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_SDMA1,
}, {
.name = "sdma0",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_SDMA0,
}, {
.name = "hclk_jpeg",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_JPEG,
}, {
.name = "camif",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_CAMIF,
}, {
.name = "hclk_scaler",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_SCALER,
}, {
.name = "2d",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_2D,
}, {
.name = "tv",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_TV,
}, {
.name = "post0",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_POST0,
}, {
.name = "rot",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_ROT,
}, {
.name = "hclk_mfc",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_MFC,
}, {
.name = "pclk_mfc",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_MFC,
}, {
.name = "dac27",
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_DAC27,
}, {
.name = "tv27",
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_TV27,
}, {
.name = "scaler27",
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_SCALER27,
}, {
.name = "sclk_scaler",
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_SCALER,
}, {
.name = "post0_27",
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_POST0_27,
}, {
.name = "secur",
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_SECUR,
}, {
.name = "sclk_mfc",
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MFC,
}, {
.name = "sclk_jpeg",
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_JPEG,
},
};
static struct clk clk_48m_spi0 = {
.name = "spi_48m",
.devname = "s3c6410-spi.0",
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
};
static struct clk clk_48m_spi1 = {
.name = "spi_48m",
.devname = "s3c6410-spi.1",
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
};
static struct clk clk_i2s0 = {
.name = "iis",
.devname = "samsung-i2s.0",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIS0,
};
static struct clk clk_i2s1 = {
.name = "iis",
.devname = "samsung-i2s.1",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIS1,
};
#ifdef CONFIG_CPU_S3C6410
static struct clk clk_i2s2 = {
.name = "iis",
.devname = "samsung-i2s.2",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C6410_CLKCON_PCLK_IIS2,
};
#endif
static struct clk init_clocks[] = {
{
.name = "lcd",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_LCD,
}, {
.name = "gpio",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_GPIO,
}, {
.name = "usb-host",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_UHOST,
}, {
.name = "otg",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_USB,
}, {
.name = "timers",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_PWM,
}, {
.name = "uart",
.devname = "s3c6400-uart.0",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART0,
}, {
.name = "uart",
.devname = "s3c6400-uart.1",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART1,
}, {
.name = "uart",
.devname = "s3c6400-uart.2",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART2,
}, {
.name = "uart",
.devname = "s3c6400-uart.3",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART3,
}, {
.name = "watchdog",
.parent = &clk_p,
.ctrlbit = S3C_CLKCON_PCLK_WDT,
},
};
static struct clk clk_hsmmc0 = {
.name = "hsmmc",
.devname = "s3c-sdhci.0",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
};
static struct clk clk_hsmmc1 = {
.name = "hsmmc",
.devname = "s3c-sdhci.1",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
};
static struct clk clk_hsmmc2 = {
.name = "hsmmc",
.devname = "s3c-sdhci.2",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
};
static struct clk clk_fout_apll = {
.name = "fout_apll",
};
static struct clk *clk_src_apll_list[] = {
[0] = &clk_fin_apll,
[1] = &clk_fout_apll,
};
static struct clksrc_sources clk_src_apll = {
.sources = clk_src_apll_list,
.nr_sources = ARRAY_SIZE(clk_src_apll_list),
};
static struct clksrc_clk clk_mout_apll = {
.clk = {
.name = "mout_apll",
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 },
.sources = &clk_src_apll,
};
static struct clk *clk_src_epll_list[] = {
[0] = &clk_fin_epll,
[1] = &clk_fout_epll,
};
static struct clksrc_sources clk_src_epll = {
.sources = clk_src_epll_list,
.nr_sources = ARRAY_SIZE(clk_src_epll_list),
};
static struct clksrc_clk clk_mout_epll = {
.clk = {
.name = "mout_epll",
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 },
.sources = &clk_src_epll,
};
static struct clk *clk_src_mpll_list[] = {
[0] = &clk_fin_mpll,
[1] = &clk_fout_mpll,
};
static struct clksrc_sources clk_src_mpll = {
.sources = clk_src_mpll_list,
.nr_sources = ARRAY_SIZE(clk_src_mpll_list),
};
static struct clksrc_clk clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 },
.sources = &clk_src_mpll,
};
static unsigned int armclk_mask;
static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk)
{
unsigned long rate = clk_get_rate(clk->parent);
u32 clkdiv;
/* divisor mask starts at bit0, so no need to shift */
clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask;
return rate / (clkdiv + 1);
}
static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk,
unsigned long rate)
{
unsigned long parent = clk_get_rate(clk->parent);
u32 div;
if (parent < rate)
return parent;
div = (parent / rate) - 1;
if (div > armclk_mask)
div = armclk_mask;
return parent / (div + 1);
}
static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
{
unsigned long parent = clk_get_rate(clk->parent);
u32 div;
u32 val;
if (rate < parent / (armclk_mask + 1))
return -EINVAL;
rate = clk_round_rate(clk, rate);
div = clk_get_rate(clk->parent) / rate;
val = __raw_readl(S3C_CLK_DIV0);
val &= ~armclk_mask;
val |= (div - 1);
__raw_writel(val, S3C_CLK_DIV0);
return 0;
}
static struct clk clk_arm = {
.name = "armclk",
.parent = &clk_mout_apll.clk,
.ops = &(struct clk_ops) {
.get_rate = s3c64xx_clk_arm_get_rate,
.set_rate = s3c64xx_clk_arm_set_rate,
.round_rate = s3c64xx_clk_arm_round_rate,
},
};
static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
{
unsigned long rate = clk_get_rate(clk->parent);
printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
rate /= 2;
return rate;
}
static struct clk_ops clk_dout_ops = {
.get_rate = s3c64xx_clk_doutmpll_get_rate,
};
static struct clk clk_dout_mpll = {
.name = "dout_mpll",
.parent = &clk_mout_mpll.clk,
.ops = &clk_dout_ops,
};
static struct clk *clkset_spi_mmc_list[] = {
&clk_mout_epll.clk,
&clk_dout_mpll,
&clk_fin_epll,
&clk_27m,
};
static struct clksrc_sources clkset_spi_mmc = {
.sources = clkset_spi_mmc_list,
.nr_sources = ARRAY_SIZE(clkset_spi_mmc_list),
};
static struct clk *clkset_irda_list[] = {
&clk_mout_epll.clk,
&clk_dout_mpll,
NULL,
&clk_27m,
};
static struct clksrc_sources clkset_irda = {
.sources = clkset_irda_list,
.nr_sources = ARRAY_SIZE(clkset_irda_list),
};
static struct clk *clkset_uart_list[] = {
&clk_mout_epll.clk,
&clk_dout_mpll,
NULL,
NULL
};
static struct clksrc_sources clkset_uart = {
.sources = clkset_uart_list,
.nr_sources = ARRAY_SIZE(clkset_uart_list),
};
static struct clk *clkset_uhost_list[] = {
&clk_48m,
&clk_mout_epll.clk,
&clk_dout_mpll,
&clk_fin_epll,
};
static struct clksrc_sources clkset_uhost = {
.sources = clkset_uhost_list,
.nr_sources = ARRAY_SIZE(clkset_uhost_list),
};
/* The peripheral clocks are all controlled via clocksource followed
* by an optional divider and gate stage. We currently roll this into
* one clock which hides the intermediate clock from the mux.
*
* Note, the JPEG clock can only be an even divider...
*
* The scaler and LCD clocks depend on the S3C64XX version, and also
* have a common parent divisor so are not included here.
*/
/* clocks that feed other parts of the clock source tree */
static struct clk clk_iis_cd0 = {
.name = "iis_cdclk0",
};
static struct clk clk_iis_cd1 = {
.name = "iis_cdclk1",
};
static struct clk clk_iisv4_cd = {
.name = "iis_cdclk_v4",
};
static struct clk clk_pcm_cd = {
.name = "pcm_cdclk",
};
static struct clk *clkset_audio0_list[] = {
[0] = &clk_mout_epll.clk,
[1] = &clk_dout_mpll,
[2] = &clk_fin_epll,
[3] = &clk_iis_cd0,
[4] = &clk_pcm_cd,
};
static struct clksrc_sources clkset_audio0 = {
.sources = clkset_audio0_list,
.nr_sources = ARRAY_SIZE(clkset_audio0_list),
};
static struct clk *clkset_audio1_list[] = {
[0] = &clk_mout_epll.clk,
[1] = &clk_dout_mpll,
[2] = &clk_fin_epll,
[3] = &clk_iis_cd1,
[4] = &clk_pcm_cd,
};
static struct clksrc_sources clkset_audio1 = {
.sources = clkset_audio1_list,
.nr_sources = ARRAY_SIZE(clkset_audio1_list),
};
#ifdef CONFIG_CPU_S3C6410
static struct clk *clkset_audio2_list[] = {
[0] = &clk_mout_epll.clk,
[1] = &clk_dout_mpll,
[2] = &clk_fin_epll,
[3] = &clk_iisv4_cd,
[4] = &clk_pcm_cd,
};
static struct clksrc_sources clkset_audio2 = {
.sources = clkset_audio2_list,
.nr_sources = ARRAY_SIZE(clkset_audio2_list),
};
#endif
static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "usb-bus-host",
.ctrlbit = S3C_CLKCON_SCLK_UHOST,
.enable = s3c64xx_sclk_ctrl,
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 5, .size = 2 },
.reg_div = { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4 },
.sources = &clkset_uhost,
}, {
.clk = {
.name = "irda-bus",
.ctrlbit = S3C_CLKCON_SCLK_IRDA,
.enable = s3c64xx_sclk_ctrl,
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 24, .size = 2 },
.reg_div = { .reg = S3C_CLK_DIV2, .shift = 20, .size = 4 },
.sources = &clkset_irda,
}, {
.clk = {
.name = "camera",
.ctrlbit = S3C_CLKCON_SCLK_CAM,
.enable = s3c64xx_sclk_ctrl,
.parent = &clk_h2,
},
.reg_div = { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4 },
},
};
/* Where does UCLK0 come from? */
static struct clksrc_clk clk_sclk_uclk = {
.clk = {
.name = "uclk1",
.ctrlbit = S3C_CLKCON_SCLK_UART,
.enable = s3c64xx_sclk_ctrl,
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1 },
.reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 },
.sources = &clkset_uart,
};
static struct clksrc_clk clk_sclk_mmc0 = {
.clk = {
.name = "mmc_bus",
.devname = "s3c-sdhci.0",
.ctrlbit = S3C_CLKCON_SCLK_MMC0,
.enable = s3c64xx_sclk_ctrl,
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 },
.reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 },
.sources = &clkset_spi_mmc,
};
static struct clksrc_clk clk_sclk_mmc1 = {
.clk = {
.name = "mmc_bus",
.devname = "s3c-sdhci.1",
.ctrlbit = S3C_CLKCON_SCLK_MMC1,
.enable = s3c64xx_sclk_ctrl,
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 },
.reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 },
.sources = &clkset_spi_mmc,
};
static struct clksrc_clk clk_sclk_mmc2 = {
.clk = {
.name = "mmc_bus",
.devname = "s3c-sdhci.2",
.ctrlbit = S3C_CLKCON_SCLK_MMC2,
.enable = s3c64xx_sclk_ctrl,
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 },
.reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 },
.sources = &clkset_spi_mmc,
};
static struct clksrc_clk clk_sclk_spi0 = {
.clk = {
.name = "spi-bus",
.devname = "s3c6410-spi.0",
.ctrlbit = S3C_CLKCON_SCLK_SPI0,
.enable = s3c64xx_sclk_ctrl,
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
.reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
.sources = &clkset_spi_mmc,
};
static struct clksrc_clk clk_sclk_spi1 = {
.clk = {
.name = "spi-bus",
.devname = "s3c6410-spi.1",
.ctrlbit = S3C_CLKCON_SCLK_SPI1,
.enable = s3c64xx_sclk_ctrl,
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
.reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
.sources = &clkset_spi_mmc,
};
static struct clksrc_clk clk_audio_bus0 = {
.clk = {
.name = "audio-bus",
.devname = "samsung-i2s.0",
.ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
.enable = s3c64xx_sclk_ctrl,
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 7, .size = 3 },
.reg_div = { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4 },
.sources = &clkset_audio0,
};
static struct clksrc_clk clk_audio_bus1 = {
.clk = {
.name = "audio-bus",
.devname = "samsung-i2s.1",
.ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
.enable = s3c64xx_sclk_ctrl,
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3 },
.reg_div = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4 },
.sources = &clkset_audio1,
};
#ifdef CONFIG_CPU_S3C6410
static struct clksrc_clk clk_audio_bus2 = {
.clk = {
.name = "audio-bus",
.devname = "samsung-i2s.2",
.ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2,
.enable = s3c64xx_sclk_ctrl,
},
.reg_src = { .reg = S3C6410_CLK_SRC2, .shift = 0, .size = 3 },
.reg_div = { .reg = S3C_CLK_DIV2, .shift = 24, .size = 4 },
.sources = &clkset_audio2,
};
#endif
/* Clock initialisation code */
static struct clksrc_clk *init_parents[] = {
&clk_mout_apll,
&clk_mout_epll,
&clk_mout_mpll,
};
static struct clksrc_clk *clksrc_cdev[] = {
&clk_sclk_uclk,
&clk_sclk_mmc0,
&clk_sclk_mmc1,
&clk_sclk_mmc2,
&clk_sclk_spi0,
&clk_sclk_spi1,
&clk_audio_bus0,
&clk_audio_bus1,
};
static struct clk *clk_cdev[] = {
&clk_hsmmc0,
&clk_hsmmc1,
&clk_hsmmc2,
&clk_48m_spi0,
&clk_48m_spi1,
&clk_i2s0,
&clk_i2s1,
};
static struct clk_lookup s3c64xx_clk_lookup[] = {
CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
CLKDEV_INIT("s3c6410-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
CLKDEV_INIT("s3c6410-spi.0", "spi_busclk2", &clk_48m_spi0),
CLKDEV_INIT("s3c6410-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
CLKDEV_INIT("s3c6410-spi.1", "spi_busclk2", &clk_48m_spi1),
CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &clk_i2s0),
CLKDEV_INIT("samsung-i2s.0", "i2s_opclk1", &clk_audio_bus0.clk),
CLKDEV_INIT("samsung-i2s.1", "i2s_opclk0", &clk_i2s1),
CLKDEV_INIT("samsung-i2s.1", "i2s_opclk1", &clk_audio_bus1.clk),
#ifdef CONFIG_CPU_S3C6410
CLKDEV_INIT("samsung-i2s.2", "i2s_opclk0", &clk_i2s2),
CLKDEV_INIT("samsung-i2s.2", "i2s_opclk1", &clk_audio_bus2.clk),
#endif
};
#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
void __init_or_cpufreq s3c64xx_setup_clocks(void)
{
struct clk *xtal_clk;
unsigned long xtal;
unsigned long fclk;
unsigned long hclk;
unsigned long hclk2;
unsigned long pclk;
unsigned long epll;
unsigned long apll;
unsigned long mpll;
unsigned int ptr;
u32 clkdiv0;
printk(KERN_DEBUG "%s: registering clocks\n", __func__);
clkdiv0 = __raw_readl(S3C_CLK_DIV0);
printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
xtal_clk = clk_get(NULL, "xtal");
BUG_ON(IS_ERR(xtal_clk));
xtal = clk_get_rate(xtal_clk);
clk_put(xtal_clk);
printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
/* For now assume the mux always selects the crystal */
clk_ext_xtal_mux.parent = xtal_clk;
epll = s3c_get_pll6553x(xtal, __raw_readl(S3C_EPLL_CON0),
__raw_readl(S3C_EPLL_CON1));
mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
fclk = mpll;
printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
apll, mpll, epll);
if(__raw_readl(S3C64XX_OTHERS) & S3C64XX_OTHERS_SYNCMUXSEL)
/* Synchronous mode */
hclk2 = apll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
else
/* Asynchronous mode */
hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
hclk2, hclk, pclk);
clk_fout_mpll.rate = mpll;
clk_fout_epll.rate = epll;
clk_fout_apll.rate = apll;
clk_h2.rate = hclk2;
clk_h.rate = hclk;
clk_p.rate = pclk;
clk_f.rate = fclk;
for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
s3c_set_clksrc(init_parents[ptr], true);
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
s3c_set_clksrc(&clksrcs[ptr], true);
}
static struct clk *clks1[] __initdata = {
&clk_ext_xtal_mux,
&clk_iis_cd0,
&clk_iis_cd1,
&clk_iisv4_cd,
&clk_pcm_cd,
&clk_mout_epll.clk,
&clk_mout_mpll.clk,
&clk_dout_mpll,
&clk_arm,
};
static struct clk *clks[] __initdata = {
&clk_ext,
&clk_epll,
&clk_27m,
&clk_48m,
&clk_h2,
&clk_xusbxti,
};
/**
* s3c64xx_register_clocks - register clocks for s3c6400 and s3c6410
* @xtal: The rate for the clock crystal feeding the PLLs.
* @armclk_divlimit: Divisor mask for ARMCLK.
*
* Register the clocks for the S3C6400 and S3C6410 SoC range, such
* as ARMCLK as well as the necessary parent clocks.
*
* This call does not setup the clocks, which is left to the
* s3c64xx_setup_clocks() call which may be needed by the cpufreq
* or resume code to re-set the clocks if the bootloader has changed
* them.
*/
void __init s3c64xx_register_clocks(unsigned long xtal,
unsigned armclk_divlimit)
{
unsigned int cnt;
armclk_mask = armclk_divlimit;
s3c24xx_register_baseclocks(xtal);
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
s3c_disable_clocks(clk_cdev[cnt], 1);
s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++)
s3c_register_clksrc(clksrc_cdev[cnt], 1);
clkdev_add_table(s3c64xx_clk_lookup, ARRAY_SIZE(s3c64xx_clk_lookup));
}
arch/arm/mach-s3c64xx/common.c
View file @ 0ebf7dc4
......@@ -14,9 +14,14 @@
* published by the Free Software Foundation.
*/
/*
* NOTE: Code in this file is not used when booting with Device Tree support.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/clk-provider.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/serial_core.h>
......@@ -38,7 +43,6 @@
#include <mach/regs-gpio.h>
#include <plat/cpu.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/pm.h>
#include <plat/gpio-cfg.h>
......@@ -50,6 +54,19 @@
#include "common.h"
/* External clock frequency */
static unsigned long xtal_f = 12000000, xusbxti_f = 48000000;
void __init s3c64xx_set_xtal_freq(unsigned long freq)
{
xtal_f = freq;
}
void __init s3c64xx_set_xusbxti_freq(unsigned long freq)
{
xusbxti_f = freq;
}
/* uart registration process */
static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
......@@ -67,7 +84,6 @@ static struct cpu_table cpu_ids[] __initdata = {
.idcode = S3C6400_CPU_ID,
.idmask = S3C64XX_CPU_MASK,
.map_io = s3c6400_map_io,
.init_clocks = s3c6400_init_clocks,
.init_uarts = s3c64xx_init_uarts,
.init = s3c6400_init,
.name = name_s3c6400,
......@@ -75,7 +91,6 @@ static struct cpu_table cpu_ids[] __initdata = {
.idcode = S3C6410_CPU_ID,
.idmask = S3C64XX_CPU_MASK,
.map_io = s3c6410_map_io,
.init_clocks = s3c6410_init_clocks,
.init_uarts = s3c64xx_init_uarts,
.init = s3c6410_init,
.name = name_s3c6410,
......@@ -192,6 +207,10 @@ void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
static __init int s3c64xx_dev_init(void)
{
/* Not applicable when using DT. */
if (of_have_populated_dt())
return 0;
subsys_system_register(&s3c64xx_subsys, NULL);
return device_register(&s3c64xx_dev);
}
......@@ -213,8 +232,10 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
{
/*
* FIXME: there is no better place to put this at the moment
* (samsung_wdt_reset_init needs clocks)
* (s3c64xx_clk_init needs ioremap and must happen before init_time
* samsung_wdt_reset_init needs clocks)
*/
s3c64xx_clk_init(NULL, xtal_f, xusbxti_f, soc_is_s3c6400(), S3C_VA_SYS);
samsung_wdt_reset_init(S3C_VA_WATCHDOG);
printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
......@@ -391,6 +412,10 @@ static int __init s3c64xx_init_irq_eint(void)
{
int irq;
/* On DT-enabled systems EINTs are handled by pinctrl-s3c64xx driver. */
if (of_have_populated_dt())
return -ENODEV;
for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
......
arch/arm/mach-s3c64xx/common.h
View file @ 0ebf7dc4
......@@ -22,21 +22,21 @@
void s3c64xx_init_irq(u32 vic0, u32 vic1);
void s3c64xx_init_io(struct map_desc *mach_desc, int size);
void s3c64xx_register_clocks(unsigned long xtal, unsigned armclk_limit);
void s3c64xx_setup_clocks(void);
void s3c64xx_restart(enum reboot_mode mode, const char *cmd);
void s3c64xx_init_late(void);
void s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
unsigned long xusbxti_f, bool is_s3c6400, void __iomem *reg_base);
void s3c64xx_set_xtal_freq(unsigned long freq);
void s3c64xx_set_xusbxti_freq(unsigned long freq);
#ifdef CONFIG_CPU_S3C6400
extern int s3c6400_init(void);
extern void s3c6400_init_irq(void);
extern void s3c6400_map_io(void);
extern void s3c6400_init_clocks(int xtal);
#else
#define s3c6400_init_clocks NULL
#define s3c6400_map_io NULL
#define s3c6400_init NULL
#endif
......@@ -46,10 +46,8 @@ extern void s3c6400_init_clocks(int xtal);
extern int s3c6410_init(void);
extern void s3c6410_init_irq(void);
extern void s3c6410_map_io(void);
extern void s3c6410_init_clocks(int xtal);
#else
#define s3c6410_init_clocks NULL
#define s3c6410_map_io NULL
#define s3c6410_init NULL
#endif
......
arch/arm/mach-s3c64xx/dma.c
View file @ 0ebf7dc4
......@@ -12,6 +12,10 @@
* published by the Free Software Foundation.
*/
/*
* NOTE: Code in this file is not used when booting with Device Tree support.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/interrupt.h>
......@@ -24,6 +28,7 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/amba/pl080.h>
#include <linux/of.h>
#include <mach/dma.h>
#include <mach/map.h>
......@@ -677,7 +682,7 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
goto err_map;
}
clk_enable(dmac->clk);
clk_prepare_enable(dmac->clk);
dmac->regs = regs;
dmac->chanbase = chbase;
......@@ -711,7 +716,7 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
return 0;
err_clk:
clk_disable(dmac->clk);
clk_disable_unprepare(dmac->clk);
clk_put(dmac->clk);
err_map:
iounmap(regs);
......@@ -726,6 +731,10 @@ static int __init s3c64xx_dma_init(void)
{
int ret;
/* This driver is not supported when booting with device tree. */
if (of_have_populated_dt())
return -ENODEV;
printk(KERN_INFO "%s: Registering DMA channels\n", __func__);
dma_pool = dma_pool_create("DMA-LLI", NULL, sizeof(struct pl080s_lli), 16, 0);
......
arch/arm/mach-s3c64xx/include/mach/regs-clock.h
View file @ 0ebf7dc4
......@@ -15,145 +15,21 @@
#ifndef __PLAT_REGS_CLOCK_H
#define __PLAT_REGS_CLOCK_H __FILE__
/*
* FIXME: Remove remaining definitions
*/
#define S3C_CLKREG(x) (S3C_VA_SYS + (x))
#define S3C_APLL_LOCK S3C_CLKREG(0x00)
#define S3C_MPLL_LOCK S3C_CLKREG(0x04)
#define S3C_EPLL_LOCK S3C_CLKREG(0x08)
#define S3C_APLL_CON S3C_CLKREG(0x0C)
#define S3C_MPLL_CON S3C_CLKREG(0x10)
#define S3C_EPLL_CON0 S3C_CLKREG(0x14)
#define S3C_EPLL_CON1 S3C_CLKREG(0x18)
#define S3C_CLK_SRC S3C_CLKREG(0x1C)
#define S3C_CLK_DIV0 S3C_CLKREG(0x20)
#define S3C_CLK_DIV1 S3C_CLKREG(0x24)
#define S3C_CLK_DIV2 S3C_CLKREG(0x28)
#define S3C_CLK_OUT S3C_CLKREG(0x2C)
#define S3C_HCLK_GATE S3C_CLKREG(0x30)
#define S3C_PCLK_GATE S3C_CLKREG(0x34)
#define S3C_SCLK_GATE S3C_CLKREG(0x38)
#define S3C_MEM0_GATE S3C_CLKREG(0x3C)
#define S3C6410_CLK_SRC2 S3C_CLKREG(0x10C)
#define S3C_MEM_SYS_CFG S3C_CLKREG(0x120)
/* CLKDIV0 */
#define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12)
#define S3C6400_CLKDIV0_PCLK_SHIFT (12)
#define S3C6400_CLKDIV0_HCLK2_MASK (0x7 << 9)
#define S3C6400_CLKDIV0_HCLK2_SHIFT (9)
#define S3C6400_CLKDIV0_HCLK_MASK (0x1 << 8)
#define S3C6400_CLKDIV0_HCLK_SHIFT (8)
#define S3C6400_CLKDIV0_MPLL_MASK (0x1 << 4)
#define S3C6400_CLKDIV0_MPLL_SHIFT (4)
#define S3C6400_CLKDIV0_ARM_MASK (0x7 << 0)
#define S3C6410_CLKDIV0_ARM_MASK (0xf << 0)
#define S3C6400_CLKDIV0_ARM_SHIFT (0)
/* HCLK GATE Registers */
#define S3C_CLKCON_HCLK_3DSE (1<<31)
#define S3C_CLKCON_HCLK_UHOST (1<<29)
#define S3C_CLKCON_HCLK_SECUR (1<<28)
#define S3C_CLKCON_HCLK_SDMA1 (1<<27)
#define S3C_CLKCON_HCLK_SDMA0 (1<<26)
#define S3C_CLKCON_HCLK_IROM (1<<25)
#define S3C_CLKCON_HCLK_DDR1 (1<<24)
#define S3C_CLKCON_HCLK_DDR0 (1<<23)
#define S3C_CLKCON_HCLK_MEM1 (1<<22)
#define S3C_CLKCON_HCLK_MEM0 (1<<21)
#define S3C_CLKCON_HCLK_USB (1<<20)
#define S3C_CLKCON_HCLK_HSMMC2 (1<<19)
#define S3C_CLKCON_HCLK_HSMMC1 (1<<18)
#define S3C_CLKCON_HCLK_HSMMC0 (1<<17)
#define S3C_CLKCON_HCLK_MDP (1<<16)
#define S3C_CLKCON_HCLK_DHOST (1<<15)
#define S3C_CLKCON_HCLK_IHOST (1<<14)
#define S3C_CLKCON_HCLK_DMA1 (1<<13)
#define S3C_CLKCON_HCLK_DMA0 (1<<12)
#define S3C_CLKCON_HCLK_JPEG (1<<11)
#define S3C_CLKCON_HCLK_CAMIF (1<<10)
#define S3C_CLKCON_HCLK_SCALER (1<<9)
#define S3C_CLKCON_HCLK_2D (1<<8)
#define S3C_CLKCON_HCLK_TV (1<<7)
#define S3C_CLKCON_HCLK_POST0 (1<<5)
#define S3C_CLKCON_HCLK_ROT (1<<4)
#define S3C_CLKCON_HCLK_LCD (1<<3)
#define S3C_CLKCON_HCLK_TZIC (1<<2)
#define S3C_CLKCON_HCLK_INTC (1<<1)
#define S3C_CLKCON_HCLK_MFC (1<<0)
/* PCLK GATE Registers */
#define S3C6410_CLKCON_PCLK_I2C1 (1<<27)
#define S3C6410_CLKCON_PCLK_IIS2 (1<<26)
#define S3C_CLKCON_PCLK_SKEY (1<<24)
#define S3C_CLKCON_PCLK_CHIPID (1<<23)
#define S3C_CLKCON_PCLK_SPI1 (1<<22)
#define S3C_CLKCON_PCLK_SPI0 (1<<21)
#define S3C_CLKCON_PCLK_HSIRX (1<<20)
#define S3C_CLKCON_PCLK_HSITX (1<<19)
#define S3C_CLKCON_PCLK_GPIO (1<<18)
#define S3C_CLKCON_PCLK_IIC (1<<17)
#define S3C_CLKCON_PCLK_IIS1 (1<<16)
#define S3C_CLKCON_PCLK_IIS0 (1<<15)
#define S3C_CLKCON_PCLK_AC97 (1<<14)
#define S3C_CLKCON_PCLK_TZPC (1<<13)
#define S3C_CLKCON_PCLK_TSADC (1<<12)
#define S3C_CLKCON_PCLK_KEYPAD (1<<11)
#define S3C_CLKCON_PCLK_IRDA (1<<10)
#define S3C_CLKCON_PCLK_PCM1 (1<<9)
#define S3C_CLKCON_PCLK_PCM0 (1<<8)
#define S3C_CLKCON_PCLK_PWM (1<<7)
#define S3C_CLKCON_PCLK_RTC (1<<6)
#define S3C_CLKCON_PCLK_WDT (1<<5)
#define S3C_CLKCON_PCLK_UART3 (1<<4)
#define S3C_CLKCON_PCLK_UART2 (1<<3)
#define S3C_CLKCON_PCLK_UART1 (1<<2)
#define S3C_CLKCON_PCLK_UART0 (1<<1)
#define S3C_CLKCON_PCLK_MFC (1<<0)
/* SCLK GATE Registers */
#define S3C_CLKCON_SCLK_UHOST (1<<30)
#define S3C_CLKCON_SCLK_MMC2_48 (1<<29)
#define S3C_CLKCON_SCLK_MMC1_48 (1<<28)
#define S3C_CLKCON_SCLK_MMC0_48 (1<<27)
#define S3C_CLKCON_SCLK_MMC2 (1<<26)
#define S3C_CLKCON_SCLK_MMC1 (1<<25)
#define S3C_CLKCON_SCLK_MMC0 (1<<24)
#define S3C_CLKCON_SCLK_SPI1_48 (1<<23)
#define S3C_CLKCON_SCLK_SPI0_48 (1<<22)
#define S3C_CLKCON_SCLK_SPI1 (1<<21)
#define S3C_CLKCON_SCLK_SPI0 (1<<20)
#define S3C_CLKCON_SCLK_DAC27 (1<<19)
#define S3C_CLKCON_SCLK_TV27 (1<<18)
#define S3C_CLKCON_SCLK_SCALER27 (1<<17)
#define S3C_CLKCON_SCLK_SCALER (1<<16)
#define S3C_CLKCON_SCLK_LCD27 (1<<15)
#define S3C_CLKCON_SCLK_LCD (1<<14)
#define S3C6400_CLKCON_SCLK_POST1_27 (1<<13)
#define S3C6410_CLKCON_FIMC (1<<13)
#define S3C_CLKCON_SCLK_POST0_27 (1<<12)
#define S3C6400_CLKCON_SCLK_POST1 (1<<11)
#define S3C6410_CLKCON_SCLK_AUDIO2 (1<<11)
#define S3C_CLKCON_SCLK_POST0 (1<<10)
#define S3C_CLKCON_SCLK_AUDIO1 (1<<9)
#define S3C_CLKCON_SCLK_AUDIO0 (1<<8)
#define S3C_CLKCON_SCLK_SECUR (1<<7)
#define S3C_CLKCON_SCLK_IRDA (1<<6)
#define S3C_CLKCON_SCLK_UART (1<<5)
#define S3C_CLKCON_SCLK_ONENAND (1<<4)
#define S3C_CLKCON_SCLK_MFC (1<<3)
#define S3C_CLKCON_SCLK_CAM (1<<2)
#define S3C_CLKCON_SCLK_JPEG (1<<1)
/* CLKSRC */
#define S3C6400_CLKSRC_APLL_MOUT (1 << 0)
#define S3C6400_CLKSRC_MPLL_MOUT (1 << 1)
#define S3C6400_CLKSRC_EPLL_MOUT (1 << 2)
#define S3C6400_CLKSRC_APLL_MOUT_SHIFT (0)
#define S3C6400_CLKSRC_MPLL_MOUT_SHIFT (1)
#define S3C6400_CLKSRC_EPLL_MOUT_SHIFT (2)
#define S3C6400_CLKSRC_MFC (1 << 4)
/* MEM_SYS_CFG */
#define MEM_SYS_CFG_INDEP_CF 0x4000
......
arch/arm/mach-s3c64xx/irq-pm.c
View file @ 0ebf7dc4
......@@ -12,12 +12,17 @@
* published by the Free Software Foundation.
*/
/*
* NOTE: Code in this file is not used when booting with Device Tree support.
*/
#include <linux/kernel.h>
#include <linux/syscore_ops.h>
#include <linux/interrupt.h>
#include <linux/serial_core.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/of.h>
#include <mach/map.h>
......@@ -101,6 +106,10 @@ static struct syscore_ops s3c64xx_irq_syscore_ops = {
static __init int s3c64xx_syscore_init(void)
{
/* Appropriate drivers (pinctrl, uart) handle this when using DT. */
if (of_have_populated_dt())
return 0;
register_syscore_ops(&s3c64xx_irq_syscore_ops);
return 0;
......
arch/arm/mach-s3c64xx/mach-anw6410.c
View file @ 0ebf7dc4
......@@ -207,7 +207,7 @@ static struct platform_device *anw6410_devices[] __initdata = {
static void __init anw6410_map_io(void)
{
s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc));
s3c24xx_init_clocks(12000000);
s3c64xx_set_xtal_freq(12000000);
s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs));
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
......
arch/arm/mach-s3c64xx/mach-crag6410.c
View file @ 0ebf7dc4
......@@ -743,7 +743,7 @@ static struct s3c2410_platform_i2c i2c1_pdata = {
static void __init crag6410_map_io(void)
{
s3c64xx_init_io(NULL, 0);
s3c24xx_init_clocks(12000000);
s3c64xx_set_xtal_freq(12000000);
s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs));
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
......
arch/arm/mach-s3c64xx/mach-hmt.c
View file @ 0ebf7dc4
......@@ -247,7 +247,7 @@ static struct platform_device *hmt_devices[] __initdata = {
static void __init hmt_map_io(void)
{
s3c64xx_init_io(hmt_iodesc, ARRAY_SIZE(hmt_iodesc));
s3c24xx_init_clocks(12000000);
s3c64xx_set_xtal_freq(12000000);
s3c24xx_init_uarts(hmt_uartcfgs, ARRAY_SIZE(hmt_uartcfgs));
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
}
......
arch/arm/mach-s3c64xx/mach-mini6410.c
View file @ 0ebf7dc4
......@@ -231,7 +231,7 @@ static void __init mini6410_map_io(void)
u32 tmp;
s3c64xx_init_io(NULL, 0);
s3c24xx_init_clocks(12000000);
s3c64xx_set_xtal_freq(12000000);
s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs));
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
......
arch/arm/mach-s3c64xx/mach-ncp.c
View file @ 0ebf7dc4
......@@ -86,7 +86,7 @@ static struct map_desc ncp_iodesc[] __initdata = {};
static void __init ncp_map_io(void)
{
s3c64xx_init_io(ncp_iodesc, ARRAY_SIZE(ncp_iodesc));
s3c24xx_init_clocks(12000000);
s3c64xx_set_xtal_freq(12000000);
s3c24xx_init_uarts(ncp_uartcfgs, ARRAY_SIZE(ncp_uartcfgs));
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
}
......
arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c 0 → 100644
View file @ 0ebf7dc4
/*
* Samsung's S3C64XX flattened device tree enabled machine
*
* Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/clk-provider.h>
#include <linux/irqchip.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>
#include <plat/cpu.h>
#include <plat/watchdog-reset.h>
#include <mach/map.h>
#include "common.h"
/*
* IO mapping for shared system controller IP.
*
* FIXME: Make remaining drivers use dynamic mapping.
*/
static struct map_desc s3c64xx_dt_iodesc[] __initdata = {
{
.virtual = (unsigned long)S3C_VA_SYS,
.pfn = __phys_to_pfn(S3C64XX_PA_SYSCON),
.length = SZ_4K,
.type = MT_DEVICE,
},
};
static void __init s3c64xx_dt_map_io(void)
{
debug_ll_io_init();
iotable_init(s3c64xx_dt_iodesc, ARRAY_SIZE(s3c64xx_dt_iodesc));
s3c64xx_init_cpu();
if (!soc_is_s3c64xx())
panic("SoC is not S3C64xx!");
}
static void __init s3c64xx_dt_init_irq(void)
{
of_clk_init(NULL);
samsung_wdt_reset_of_init();
irqchip_init();
};
static void __init s3c64xx_dt_init_machine(void)
{
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static void s3c64xx_dt_restart(enum reboot_mode mode, const char *cmd)
{
if (mode != REBOOT_SOFT)
samsung_wdt_reset();
/* if all else fails, or mode was for soft, jump to 0 */
soft_restart(0);
}
static char const *s3c64xx_dt_compat[] __initdata = {
"samsung,s3c6400",
"samsung,s3c6410",
NULL
};
DT_MACHINE_START(S3C6400_DT, "Samsung S3C64xx (Flattened Device Tree)")
/* Maintainer: Tomasz Figa <tomasz.figa@gmail.com> */
.dt_compat = s3c64xx_dt_compat,
.map_io = s3c64xx_dt_map_io,
.init_irq = s3c64xx_dt_init_irq,
.init_machine = s3c64xx_dt_init_machine,
.restart = s3c64xx_dt_restart,
MACHINE_END
arch/arm/mach-s3c64xx/mach-smartq.c
View file @ 0ebf7dc4
......@@ -337,13 +337,6 @@ static int __init smartq_usb_host_init(void)
return ret;
}
static int __init smartq_usb_otg_init(void)
{
clk_xusbxti.rate = 12000000;
return 0;
}
static int __init smartq_wifi_init(void)
{
int ret;
......@@ -377,7 +370,8 @@ static struct map_desc smartq_iodesc[] __initdata = {};
void __init smartq_map_io(void)
{
s3c64xx_init_io(smartq_iodesc, ARRAY_SIZE(smartq_iodesc));
s3c24xx_init_clocks(12000000);
s3c64xx_set_xtal_freq(12000000);
s3c64xx_set_xusbxti_freq(12000000);
s3c24xx_init_uarts(smartq_uartcfgs, ARRAY_SIZE(smartq_uartcfgs));
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
......@@ -399,7 +393,6 @@ void __init smartq_machine_init(void)
WARN_ON(smartq_lcd_setup_gpio());
WARN_ON(smartq_power_off_init());
WARN_ON(smartq_usb_host_init());
WARN_ON(smartq_usb_otg_init());
WARN_ON(smartq_wifi_init());
platform_add_devices(smartq_devices, ARRAY_SIZE(smartq_devices));
......
arch/arm/mach-s3c64xx/mach-smdk6400.c
View file @ 0ebf7dc4
......@@ -65,7 +65,7 @@ static struct map_desc smdk6400_iodesc[] = {};
static void __init smdk6400_map_io(void)
{
s3c64xx_init_io(smdk6400_iodesc, ARRAY_SIZE(smdk6400_iodesc));
s3c24xx_init_clocks(12000000);
s3c64xx_set_xtal_freq(12000000);
s3c24xx_init_uarts(smdk6400_uartcfgs, ARRAY_SIZE(smdk6400_uartcfgs));
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
}
......
arch/arm/mach-s3c64xx/mach-smdk6410.c
View file @ 0ebf7dc4
......@@ -634,7 +634,7 @@ static void __init smdk6410_map_io(void)
u32 tmp;
s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
s3c24xx_init_clocks(12000000);
s3c64xx_set_xtal_freq(12000000);
s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
......
arch/arm/mach-s3c64xx/pm.c
View file @ 0ebf7dc4
......@@ -194,29 +194,8 @@ void s3c_pm_debug_smdkled(u32 set, u32 clear)
#endif
static struct sleep_save core_save[] = {
SAVE_ITEM(S3C_APLL_LOCK),
SAVE_ITEM(S3C_MPLL_LOCK),
SAVE_ITEM(S3C_EPLL_LOCK),
SAVE_ITEM(S3C_CLK_SRC),
SAVE_ITEM(S3C_CLK_DIV0),
SAVE_ITEM(S3C_CLK_DIV1),
SAVE_ITEM(S3C_CLK_DIV2),
SAVE_ITEM(S3C_CLK_OUT),
SAVE_ITEM(S3C_HCLK_GATE),
SAVE_ITEM(S3C_PCLK_GATE),
SAVE_ITEM(S3C_SCLK_GATE),
SAVE_ITEM(S3C_MEM0_GATE),
SAVE_ITEM(S3C_EPLL_CON1),
SAVE_ITEM(S3C_EPLL_CON0),
SAVE_ITEM(S3C64XX_MEM0DRVCON),
SAVE_ITEM(S3C64XX_MEM1DRVCON),
#ifndef CONFIG_CPU_FREQ
SAVE_ITEM(S3C_APLL_CON),
SAVE_ITEM(S3C_MPLL_CON),
#endif
};
static struct sleep_save misc_save[] = {
......
arch/arm/mach-s3c64xx/s3c6400.c
View file @ 0ebf7dc4
......@@ -9,6 +9,10 @@
* published by the Free Software Foundation.
*/
/*
* NOTE: Code in this file is not used when booting with Device Tree support.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
......@@ -20,6 +24,7 @@
#include <linux/device.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
......@@ -58,12 +63,6 @@ void __init s3c6400_map_io(void)
s3c64xx_onenand1_setname("s3c6400-onenand");
}
void __init s3c6400_init_clocks(int xtal)
{
s3c64xx_register_clocks(xtal, S3C6400_CLKDIV0_ARM_MASK);
s3c64xx_setup_clocks();
}
void __init s3c6400_init_irq(void)
{
/* VIC0 does not have IRQS 5..7,
......@@ -82,6 +81,10 @@ static struct device s3c6400_dev = {
static int __init s3c6400_core_init(void)
{
/* Not applicable when using DT. */
if (of_have_populated_dt())
return 0;
return subsys_system_register(&s3c6400_subsys, NULL);
}
......
arch/arm/mach-s3c64xx/s3c6410.c
View file @ 0ebf7dc4
......@@ -10,6 +10,10 @@
* published by the Free Software Foundation.
*/
/*
* NOTE: Code in this file is not used when booting with Device Tree support.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
......@@ -21,6 +25,7 @@
#include <linux/device.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
......@@ -62,13 +67,6 @@ void __init s3c6410_map_io(void)
s3c_cfcon_setname("s3c64xx-pata");
}
void __init s3c6410_init_clocks(int xtal)
{
printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
s3c64xx_register_clocks(xtal, S3C6410_CLKDIV0_ARM_MASK);
s3c64xx_setup_clocks();
}
void __init s3c6410_init_irq(void)
{
/* VIC0 is missing IRQ7, VIC1 is fully populated. */
......@@ -86,6 +84,10 @@ static struct device s3c6410_dev = {
static int __init s3c6410_core_init(void)
{
/* Not applicable when using DT. */
if (of_have_populated_dt())
return 0;
return subsys_system_register(&s3c6410_subsys, NULL);
}
......
arch/arm/plat-samsung/include/plat/cpu.h
View file @ 0ebf7dc4
......@@ -87,8 +87,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
#endif
#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
# define soc_is_s3c6400() is_samsung_s3c6400()
# define soc_is_s3c6410() is_samsung_s3c6410()
# define soc_is_s3c64xx() (is_samsung_s3c6400() || is_samsung_s3c6410())
#else
# define soc_is_s3c6400() 0
# define soc_is_s3c6410() 0
# define soc_is_s3c64xx() 0
#endif
......
arch/arm/plat-samsung/init.c
View file @ 0ebf7dc4
......@@ -11,12 +11,18 @@
* published by the Free Software Foundation.
*/
/*
* NOTE: Code in this file is not used on S3C64xx when booting with
* Device Tree support.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/serial_core.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <mach/hardware.h>
......@@ -148,8 +154,12 @@ static int __init s3c_arch_init(void)
// do the correct init for cpu
if (cpu == NULL)
if (cpu == NULL) {
/* Not needed when booting with device tree. */
if (of_have_populated_dt())
return 0;
panic("s3c_arch_init: NULL cpu\n");
}
ret = (cpu->init)();
if (ret != 0)
......
drivers/clk/samsung/Makefile
View file @ 0ebf7dc4
......@@ -8,6 +8,4 @@ obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
ifdef CONFIG_COMMON_CLK
obj-$(CONFIG_ARCH_S3C64XX) += clk-s3c64xx.o
endif
drivers/gpio/gpio-samsung.c
View file @ 0ebf7dc4
......@@ -2082,34 +2082,14 @@ static __init int samsung_gpiolib_init(void)
int i, nr_chips;
int group = 0;
#if defined(CONFIG_PINCTRL_EXYNOS) || defined(CONFIG_PINCTRL_EXYNOS5440)
/*
* This gpio driver includes support for device tree support and there
* are platforms using it. In order to maintain compatibility with those
* platforms, and to allow non-dt Exynos4210 platforms to use this
* gpiolib support, a check is added to find out if there is a active
* pin-controller driver support available. If it is available, this
* gpiolib support is ignored and the gpiolib support available in
* pin-controller driver is used. This is a temporary check and will go
* away when all of the Exynos4210 platforms have switched to using
* device tree and the pin-ctrl driver.
* Currently there are two drivers that can provide GPIO support for
* Samsung SoCs. For device tree enabled platforms, the new
* pinctrl-samsung driver is used, providing both GPIO and pin control
* interfaces. For legacy (non-DT) platforms this driver is used.
*/
struct device_node *pctrl_np;
static const struct of_device_id exynos_pinctrl_ids[] = {
{ .compatible = "samsung,s3c2412-pinctrl", },
{ .compatible = "samsung,s3c2416-pinctrl", },
{ .compatible = "samsung,s3c2440-pinctrl", },
{ .compatible = "samsung,s3c2450-pinctrl", },
{ .compatible = "samsung,exynos4210-pinctrl", },
{ .compatible = "samsung,exynos4x12-pinctrl", },
{ .compatible = "samsung,exynos5250-pinctrl", },
{ .compatible = "samsung,exynos5440-pinctrl", },
{ }
};
for_each_matching_node(pctrl_np, exynos_pinctrl_ids)
if (pctrl_np && of_device_is_available(pctrl_np))
if (of_have_populated_dt())
return -ENODEV;
#endif
samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
......
drivers/irqchip/irq-vic.c
View file @ 0ebf7dc4
......@@ -469,6 +469,8 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
int __init vic_of_init(struct device_node *node, struct device_node *parent)
{
void __iomem *regs;
u32 interrupt_mask = ~0;
u32 wakeup_mask = ~0;
if (WARN(parent, "non-root VICs are not supported"))
return -EINVAL;
......@@ -477,10 +479,13 @@ int __init vic_of_init(struct device_node *node, struct device_node *parent)
if (WARN_ON(!regs))
return -EIO;
of_property_read_u32(node, "valid-mask", &interrupt_mask);
of_property_read_u32(node, "valid-wakeup-mask", &wakeup_mask);
/*
* Passing 0 as first IRQ makes the simple domain allocate descriptors
*/
__vic_init(regs, 0, ~0, ~0, node);
__vic_init(regs, 0, interrupt_mask, wakeup_mask, node);
return 0;
}
......
drivers/usb/host/ohci-s3c2410.c
View file @ 0ebf7dc4
......@@ -47,10 +47,10 @@ static void s3c2410_start_hc(struct platform_device *dev, struct usb_hcd *hcd)
dev_dbg(&dev->dev, "s3c2410_start_hc:\n");
clk_enable(usb_clk);
clk_prepare_enable(usb_clk);
mdelay(2); /* let the bus clock stabilise */
clk_enable(clk);
clk_prepare_enable(clk);
if (info != NULL) {
info->hcd = hcd;
......@@ -75,8 +75,8 @@ static void s3c2410_stop_hc(struct platform_device *dev)
(info->enable_oc)(info, 0);
}
clk_disable(clk);
clk_disable(usb_clk);
clk_disable_unprepare(clk);
clk_disable_unprepare(usb_clk);
}
/* ohci_s3c2410_hub_status_data
......
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