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Commit 0eccf60b authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm 

* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (30 commits)
  [ARM] constify function pointer tables
  [ARM] 4823/1: AT91 section fix
  [ARM] 4824/1: pxa: clear RDH bit after any reset
  [ARM] pxa: remove debugging PM: printk
  ARM: OMAP1: Misc clean-up
  ARM: OMAP1: Update defconfigs for omap1
  ARM: OMAP1: Palm Tungsten E board clean-up
  ARM: OMAP1: Use I2C bus registration helper for omap1
  ARM: OMAP1: Remove omap_sram_idle()
  ARM: OMAP1: PM fixes for OMAP1
  ARM: OMAP1: Use MMC multislot structures for Siemens SX1 board
  ARM: OMAP1: Make omap1 use MMC multislot structures
  ARM: OMAP1: Change the comments to C style
  ARM: OMAP1: Make omap1 boards to use omap_nand_platform_data
  ARM: OMAP: Add helper module for board specific I2C bus registration
  ARM: OMAP: Add dmtimer support for OMAP3
  ARM: OMAP: Pre-3430 clean-up for dmtimer.c
  ARM: OMAP: Add DMA support for chaining and 3430
  ARM: OMAP: Add 24xx GPIO debounce support
  ARM: OMAP: Get rid of unnecessary ifdefs in GPIO code
  ...
parents b6ce068a f9166e73
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arch/arm/configs/omap_h2_1610_defconfig
View file @ 0eccf60b
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.23-rc6
# Mon Sep 17 14:21:45 2007
# Linux kernel version: 2.6.24-rc5
# Mon Dec 17 20:04:38 2007
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
......@@ -41,9 +41,14 @@ CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_USER_NS is not set
# CONFIG_PID_NS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_CGROUPS is not set
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_FAIR_USER_SCHED=y
# CONFIG_FAIR_CGROUP_SCHED is not set
# CONFIG_SYSFS_DEPRECATED is not set
# CONFIG_RELAY is not set
CONFIG_BLK_DEV_INITRD=y
......@@ -64,7 +69,6 @@ CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_VM_EVENT_COUNTERS=y
......@@ -224,10 +228,6 @@ CONFIG_ARM_THUMB=y
#
# CONFIG_PCI_SYSCALL is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
#
# PCCARD (PCMCIA/CardBus) support
#
# CONFIG_PCCARD is not set
#
......@@ -236,6 +236,7 @@ CONFIG_ARM_THUMB=y
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_PREEMPT=y
CONFIG_HZ=128
CONFIG_AEABI=y
......@@ -248,6 +249,7 @@ CONFIG_FLATMEM_MANUAL=y
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
CONFIG_SPLIT_PTLOCK_CPUS=4096
# CONFIG_RESOURCES_64BIT is not set
CONFIG_ZONE_DMA_FLAG=1
......@@ -275,6 +277,8 @@ CONFIG_CPU_FREQ_STAT=y
# CONFIG_CPU_FREQ_STAT_DETAILS is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
# CONFIG_CPU_FREQ_GOV_PERFORMANCE is not set
# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
CONFIG_CPU_FREQ_GOV_USERSPACE=y
......@@ -347,6 +351,7 @@ CONFIG_IP_PNP_BOOTP=y
CONFIG_INET_XFRM_MODE_TRANSPORT=y
CONFIG_INET_XFRM_MODE_TUNNEL=y
CONFIG_INET_XFRM_MODE_BEET=y
# CONFIG_INET_LRO is not set
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
......@@ -372,10 +377,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
#
......@@ -404,6 +405,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_FW_LOADER is not set
......@@ -422,6 +424,8 @@ CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
# CONFIG_CDROM_PKTCDVD is not set
CONFIG_ATA_OVER_ETH=m
CONFIG_MISC_DEVICES=y
# CONFIG_EEPROM_93CX6 is not set
#
# SCSI device support
......@@ -459,6 +463,7 @@ CONFIG_SCSI_WAIT_SCAN=m
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
CONFIG_SCSI_LOWLEVEL=y
# CONFIG_ISCSI_TCP is not set
# CONFIG_SCSI_DEBUG is not set
......@@ -471,12 +476,18 @@ CONFIG_NETDEVICES=y
# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_VETH is not set
# CONFIG_PHYLIB is not set
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
# CONFIG_AX88796 is not set
CONFIG_SMC91X=y
# CONFIG_DM9000 is not set
# CONFIG_IBM_NEW_EMAC_ZMII is not set
# CONFIG_IBM_NEW_EMAC_RGMII is not set
# CONFIG_IBM_NEW_EMAC_TAH is not set
# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
# CONFIG_B44 is not set
CONFIG_NETDEV_1000=y
CONFIG_NETDEV_10000=y
......@@ -522,7 +533,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
CONFIG_INPUT_EVDEV=y
CONFIG_INPUT_EVBUG=y
......@@ -576,20 +586,51 @@ CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_IPMI_HANDLER is not set
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_NOWAYOUT=y
#
# Watchdog Device Drivers
#
# CONFIG_SOFT_WATCHDOG is not set
# CONFIG_OMAP_WATCHDOG is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_NVRAM is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
# CONFIG_I2C is not set
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
# CONFIG_I2C_CHARDEV is not set
#
# I2C Algorithms
#
# CONFIG_I2C_ALGOBIT is not set
# CONFIG_I2C_ALGOPCF is not set
# CONFIG_I2C_ALGOPCA is not set
#
# I2C Hardware Bus support
#
# CONFIG_I2C_GPIO is not set
# CONFIG_I2C_OCORES is not set
CONFIG_I2C_OMAP=y
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_STUB is not set
#
# Miscellaneous I2C Chip support
#
# CONFIG_SENSORS_DS1337 is not set
# CONFIG_SENSORS_DS1374 is not set
# CONFIG_DS1682 is not set
# CONFIG_SENSORS_EEPROM is not set
# CONFIG_SENSORS_PCF8574 is not set
# CONFIG_SENSORS_PCA9539 is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_ISP1301_OMAP is not set
CONFIG_TPS65010=y
# CONFIG_SENSORS_MAX6875 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
#
# SPI support
......@@ -597,28 +638,73 @@ CONFIG_WATCHDOG_NOWAYOUT=y
# CONFIG_SPI is not set
# CONFIG_SPI_MASTER is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
CONFIG_HWMON=y
# CONFIG_HWMON_VID is not set
# CONFIG_SENSORS_ABITUGURU is not set
# CONFIG_SENSORS_ABITUGURU3 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
# CONFIG_SENSORS_ADM1026 is not set
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_F71882FG is not set
# CONFIG_SENSORS_F75375S is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_GL520SM is not set
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM77 is not set
# CONFIG_SENSORS_LM78 is not set
# CONFIG_SENSORS_LM80 is not set
# CONFIG_SENSORS_LM83 is not set
# CONFIG_SENSORS_LM85 is not set
# CONFIG_SENSORS_LM87 is not set
# CONFIG_SENSORS_LM90 is not set
# CONFIG_SENSORS_LM92 is not set
# CONFIG_SENSORS_LM93 is not set
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_MAX6650 is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_PC87427 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_HWMON_DEBUG_CHIP is not set
CONFIG_MISC_DEVICES=y
# CONFIG_EEPROM_93CX6 is not set
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_NOWAYOUT=y
#
# Watchdog Device Drivers
#
# CONFIG_SOFT_WATCHDOG is not set
# CONFIG_OMAP_WATCHDOG is not set
#
# Sonics Silicon Backplane
#
CONFIG_SSB_POSSIBLE=y
# CONFIG_SSB is not set
#
# Multifunction device drivers
#
# CONFIG_MFD_SM501 is not set
# CONFIG_NEW_LEDS is not set
#
# Multimedia devices
......@@ -630,12 +716,6 @@ CONFIG_DAB=y
#
# Graphics support
#
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
# CONFIG_VGASTATE is not set
CONFIG_VIDEO_OUTPUT_CONTROL=m
CONFIG_FB=y
......@@ -644,6 +724,7 @@ CONFIG_FIRMWARE_EDID=y
# CONFIG_FB_CFB_FILLRECT is not set
# CONFIG_FB_CFB_COPYAREA is not set
# CONFIG_FB_CFB_IMAGEBLIT is not set
# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
# CONFIG_FB_SYS_FILLRECT is not set
# CONFIG_FB_SYS_COPYAREA is not set
# CONFIG_FB_SYS_IMAGEBLIT is not set
......@@ -659,8 +740,14 @@ CONFIG_FB_MODE_HELPERS=y
# Frame buffer hardware drivers
#
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_OMAP is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_OMAP is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
#
# Console display driver support
......@@ -705,6 +792,7 @@ CONFIG_SOUND_PRIME=y
CONFIG_HID_SUPPORT=y
CONFIG_HID=y
CONFIG_HID_DEBUG=y
# CONFIG_HIDRAW is not set
CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
......@@ -720,22 +808,10 @@ CONFIG_USB_ARCH_HAS_OHCI=y
#
# CONFIG_USB_GADGET is not set
# CONFIG_MMC is not set
# CONFIG_NEW_LEDS is not set
CONFIG_RTC_LIB=y
# CONFIG_RTC_CLASS is not set
#
# DMA Engine support
#
# CONFIG_DMA_ENGINE is not set
#
# DMA Clients
#
#
# DMA Devices
#
#
# File systems
#
......@@ -771,8 +847,9 @@ CONFIG_DNOTIFY=y
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
# CONFIG_VFAT_FS is not set
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
# CONFIG_NTFS_FS is not set
#
......@@ -783,7 +860,6 @@ CONFIG_PROC_SYSCTL=y
CONFIG_SYSFS=y
# CONFIG_TMPFS is not set
# CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y
# CONFIG_CONFIGFS_FS is not set
#
......@@ -802,10 +878,7 @@ CONFIG_CRAMFS=y
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Network File Systems
#
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
......@@ -832,13 +905,9 @@ CONFIG_RPCSEC_GSS_KRB5=y
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
#
# Native Language Support
#
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NLS_CODEPAGE_437 is not set
CONFIG_NLS_CODEPAGE_437=y
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
# CONFIG_NLS_CODEPAGE_850 is not set
......@@ -862,7 +931,7 @@ CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
# CONFIG_NLS_ASCII is not set
# CONFIG_NLS_ISO8859_1 is not set
CONFIG_NLS_ISO8859_1=y
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
......@@ -876,21 +945,16 @@ CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_UTF8 is not set
#
# Distributed Lock Manager
#
# CONFIG_DLM is not set
#
# Profiling support
#
CONFIG_INSTRUMENTATION=y
# CONFIG_PROFILING is not set
# CONFIG_MARKERS is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
......@@ -899,6 +963,7 @@ CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_DEBUG_KERNEL is not set
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_FRAME_POINTER=y
# CONFIG_SAMPLES is not set
# CONFIG_DEBUG_USER is not set
#
......@@ -906,6 +971,7 @@ CONFIG_FRAME_POINTER=y
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
CONFIG_CRYPTO=y
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_BLKCIPHER=y
......@@ -925,6 +991,7 @@ CONFIG_CRYPTO_ECB=m
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_PCBC=m
# CONFIG_CRYPTO_LRW is not set
# CONFIG_CRYPTO_XTS is not set
# CONFIG_CRYPTO_CRYPTD is not set
CONFIG_CRYPTO_DES=y
# CONFIG_CRYPTO_FCRYPT is not set
......@@ -938,11 +1005,13 @@ CONFIG_CRYPTO_DES=y
# CONFIG_CRYPTO_ARC4 is not set
# CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_ANUBIS is not set
# CONFIG_CRYPTO_SEED is not set
# CONFIG_CRYPTO_DEFLATE is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_CRC32C is not set
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_TEST is not set
# CONFIG_CRYPTO_AUTHENC is not set
CONFIG_CRYPTO_HW=y
#
......
arch/arm/configs/omap_osk_5912_defconfig
View file @ 0eccf60b
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.23-rc6
# Mon Sep 17 14:15:05 2007
# Linux kernel version: 2.6.24-rc5
# Mon Dec 17 21:12:45 2007
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
......@@ -40,9 +40,14 @@ CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_USER_NS is not set
# CONFIG_PID_NS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_CGROUPS is not set
CONFIG_FAIR_GROUP_SCHED=y
CONFIG_FAIR_USER_SCHED=y
# CONFIG_FAIR_CGROUP_SCHED is not set
# CONFIG_SYSFS_DEPRECATED is not set
# CONFIG_RELAY is not set
CONFIG_BLK_DEV_INITRD=y
......@@ -63,7 +68,6 @@ CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_VM_EVENT_COUNTERS=y
......@@ -224,10 +228,6 @@ CONFIG_CPU_CP15_MMU=y
#
# CONFIG_PCI_SYSCALL is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
#
# PCCARD (PCMCIA/CardBus) support
#
CONFIG_PCCARD=y
# CONFIG_PCMCIA_DEBUG is not set
CONFIG_PCMCIA=y
......@@ -245,6 +245,7 @@ CONFIG_OMAP_CF=y
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
# CONFIG_PREEMPT is not set
CONFIG_HZ=128
CONFIG_AEABI=y
......@@ -257,6 +258,7 @@ CONFIG_FLATMEM_MANUAL=y
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
CONFIG_SPLIT_PTLOCK_CPUS=4096
# CONFIG_RESOURCES_64BIT is not set
CONFIG_ZONE_DMA_FLAG=1
......@@ -346,6 +348,7 @@ CONFIG_IP_PNP_BOOTP=y
CONFIG_INET_XFRM_MODE_TRANSPORT=y
CONFIG_INET_XFRM_MODE_TUNNEL=y
CONFIG_INET_XFRM_MODE_BEET=y
# CONFIG_INET_LRO is not set
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
......@@ -371,10 +374,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
#
......@@ -403,6 +402,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=y
......@@ -427,6 +427,7 @@ CONFIG_MTD_BLOCK=y
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_MTD_OOPS is not set
#
# RAM/ROM/Flash chip drivers
......@@ -495,6 +496,8 @@ CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_MISC_DEVICES=y
# CONFIG_EEPROM_93CX6 is not set
CONFIG_IDE=m
CONFIG_BLK_DEV_IDE=m
......@@ -515,9 +518,10 @@ CONFIG_IDE_PROC_FS=y
# IDE chipset support/bugfixes
#
# CONFIG_IDE_GENERIC is not set
# CONFIG_IDEPCI_PCIBUS_ORDER is not set
# CONFIG_BLK_DEV_PLATFORM is not set
# CONFIG_IDE_ARM is not set
# CONFIG_BLK_DEV_IDEDMA is not set
CONFIG_IDE_ARCH_OBSOLETE_INIT=y
# CONFIG_BLK_DEV_HD is not set
#
......@@ -536,12 +540,18 @@ CONFIG_NETDEVICES=y
# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_VETH is not set
# CONFIG_PHYLIB is not set
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
# CONFIG_AX88796 is not set
CONFIG_SMC91X=y
# CONFIG_DM9000 is not set
# CONFIG_IBM_NEW_EMAC_ZMII is not set
# CONFIG_IBM_NEW_EMAC_RGMII is not set
# CONFIG_IBM_NEW_EMAC_TAH is not set
# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
# CONFIG_B44 is not set
CONFIG_NETDEV_1000=y
CONFIG_NETDEV_10000=y
......@@ -585,7 +595,6 @@ CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set
......@@ -651,7 +660,6 @@ CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_IPMI_HANDLER is not set
# CONFIG_WATCHDOG is not set
CONFIG_HW_RANDOM=m
CONFIG_HW_RANDOM_OMAP=m
# CONFIG_NVRAM is not set
......@@ -712,10 +720,9 @@ CONFIG_TPS65010=y
# CONFIG_SPI is not set
# CONFIG_SPI_MASTER is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
CONFIG_HWMON=y
# CONFIG_HWMON_VID is not set
# CONFIG_SENSORS_ABITUGURU is not set
# CONFIG_SENSORS_ABITUGURU3 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
......@@ -723,12 +730,12 @@ CONFIG_HWMON=y
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ASB100 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_FSCHER is not set
# CONFIG_SENSORS_FSCPOS is not set
# CONFIG_SENSORS_F71882FG is not set
# CONFIG_SENSORS_F75375S is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_GL520SM is not set
# CONFIG_SENSORS_IT87 is not set
......@@ -761,14 +768,18 @@ CONFIG_HWMON=y
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_HWMON_DEBUG_CHIP is not set
CONFIG_MISC_DEVICES=y
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_WATCHDOG is not set
#
# Sonics Silicon Backplane
#
CONFIG_SSB_POSSIBLE=y
# CONFIG_SSB is not set
#
# Multifunction device drivers
#
# CONFIG_MFD_SM501 is not set
# CONFIG_NEW_LEDS is not set
#
# Multimedia devices
......@@ -780,12 +791,6 @@ CONFIG_DAB=y
#
# Graphics support
#
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
# CONFIG_VGASTATE is not set
CONFIG_VIDEO_OUTPUT_CONTROL=m
CONFIG_FB=y
......@@ -794,6 +799,7 @@ CONFIG_FIRMWARE_EDID=y
# CONFIG_FB_CFB_FILLRECT is not set
# CONFIG_FB_CFB_COPYAREA is not set
# CONFIG_FB_CFB_IMAGEBLIT is not set
# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
# CONFIG_FB_SYS_FILLRECT is not set
# CONFIG_FB_SYS_COPYAREA is not set
# CONFIG_FB_SYS_IMAGEBLIT is not set
......@@ -809,8 +815,14 @@ CONFIG_FB_MODE_HELPERS=y
# Frame buffer hardware drivers
#
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_OMAP is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_OMAP is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
#
# Console display driver support
......@@ -843,6 +855,7 @@ CONFIG_LOGO_LINUX_CLUT224=y
CONFIG_HID_SUPPORT=y
CONFIG_HID=y
CONFIG_HID_DEBUG=y
# CONFIG_HIDRAW is not set
CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
......@@ -858,22 +871,10 @@ CONFIG_USB_ARCH_HAS_OHCI=y
#
# CONFIG_USB_GADGET is not set
# CONFIG_MMC is not set
# CONFIG_NEW_LEDS is not set
CONFIG_RTC_LIB=y
# CONFIG_RTC_CLASS is not set
#
# DMA Engine support
#
# CONFIG_DMA_ENGINE is not set
#
# DMA Clients
#
#
# DMA Devices
#
#
# File systems
#
......@@ -922,7 +923,6 @@ CONFIG_PROC_SYSCTL=y
CONFIG_SYSFS=y
# CONFIG_TMPFS is not set
# CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y
# CONFIG_CONFIGFS_FS is not set
#
......@@ -938,10 +938,12 @@ CONFIG_RAMFS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
# CONFIG_JFFS2_SUMMARY is not set
# CONFIG_JFFS2_FS_XATTR is not set
# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
CONFIG_JFFS2_ZLIB=y
# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
# CONFIG_CRAMFS is not set
......@@ -950,10 +952,7 @@ CONFIG_JFFS2_RTIME=y
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Network File Systems
#
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
......@@ -979,10 +978,6 @@ CONFIG_SUNRPC=y
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
#
# Native Language Support
#
CONFIG_NLS=m
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=m
......@@ -1023,21 +1018,16 @@ CONFIG_NLS_ISO8859_1=m
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_UTF8 is not set
#
# Distributed Lock Manager
#
# CONFIG_DLM is not set
#
# Profiling support
#
CONFIG_INSTRUMENTATION=y
# CONFIG_PROFILING is not set
# CONFIG_MARKERS is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
......@@ -1046,6 +1036,7 @@ CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_DEBUG_KERNEL is not set
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_FRAME_POINTER=y
# CONFIG_SAMPLES is not set
# CONFIG_DEBUG_USER is not set
#
......@@ -1053,6 +1044,7 @@ CONFIG_FRAME_POINTER=y
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_CRYPTO is not set
#
......
arch/arm/configs/orion_defconfig
View file @ 0eccf60b
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.24-rc3
# Wed Nov 28 15:13:57 2007
# Linux kernel version: 2.6.24
# Thu Feb 7 14:10:30 2008
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
......@@ -63,17 +63,26 @@ CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_COMPAT_BRK=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
# CONFIG_PROFILING is not set
# CONFIG_MARKERS is not set
CONFIG_HAVE_OPROFILE=y
# CONFIG_KPROBES is not set
CONFIG_HAVE_KPROBES=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
......@@ -101,6 +110,8 @@ CONFIG_IOSCHED_CFQ=y
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="cfq"
CONFIG_CLASSIC_RCU=y
# CONFIG_PREEMPT_RCU is not set
#
# System Type
......@@ -139,6 +150,7 @@ CONFIG_ARCH_ORION=y
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP is not set
# CONFIG_ARCH_MSM7X00A is not set
#
# Orion Implementations
......@@ -226,6 +238,7 @@ CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE=""
# CONFIG_XIP_KERNEL is not set
# CONFIG_KEXEC is not set
# CONFIG_ATAGS_PROC is not set
#
# Floating point emulation
......@@ -250,7 +263,7 @@ CONFIG_BINFMT_ELF=y
# Power management options
#
# CONFIG_PM is not set
CONFIG_SUSPEND_UP_POSSIBLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
#
# Networking
......@@ -267,6 +280,7 @@ CONFIG_XFRM=y
# CONFIG_XFRM_USER is not set
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
# CONFIG_XFRM_STATISTICS is not set
# CONFIG_NET_KEY is not set
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
......@@ -322,6 +336,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
#
CONFIG_NET_PKTGEN=m
# CONFIG_HAMRADIO is not set
# CONFIG_CAN is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
......@@ -475,7 +490,7 @@ CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
# CONFIG_SCSI_TGT is not set
# CONFIG_SCSI_NETLINK is not set
CONFIG_SCSI_PROC_FS=y
# CONFIG_SCSI_PROC_FS is not set
#
# SCSI support type (disk, tape, CD-ROM)
......@@ -483,15 +498,15 @@ CONFIG_SCSI_PROC_FS=y
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CHR_DEV_OSST is not set
CONFIG_BLK_DEV_SR=y
CONFIG_BLK_DEV_SR=m
# CONFIG_BLK_DEV_SR_VENDOR is not set
CONFIG_CHR_DEV_SG=y
CONFIG_CHR_DEV_SG=m
# CONFIG_CHR_DEV_SCH is not set
#
# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
#
CONFIG_SCSI_MULTI_LUN=y
# CONFIG_SCSI_MULTI_LUN is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set
......@@ -528,16 +543,6 @@ CONFIG_SCSI_LOWLEVEL=y
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_STEX is not set
CONFIG_SCSI_MVSATA=y
#
# Sata options
#
# CONFIG_MV_SATA_SUPPORT_ATAPI is not set
# CONFIG_MV_SATA_ENABLE_1MB_IOS is not set
CONFIG_SATA_NO_DEBUG=y
# CONFIG_SATA_DEBUG_ON_ERROR is not set
# CONFIG_SATA_FULL_DEBUG is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_IPR is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
......@@ -549,12 +554,12 @@ CONFIG_SATA_NO_DEBUG=y
# CONFIG_SCSI_NSP32 is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_SRP is not set
CONFIG_ATA=m
CONFIG_ATA=y
# CONFIG_ATA_NONSTANDARD is not set
# CONFIG_SATA_AHCI is not set
# CONFIG_SATA_SVW is not set
# CONFIG_ATA_PIIX is not set
# CONFIG_SATA_MV is not set
CONFIG_SATA_MV=y
# CONFIG_SATA_NV is not set
# CONFIG_PDC_ADMA is not set
# CONFIG_SATA_QSTOR is not set
......@@ -590,6 +595,7 @@ CONFIG_ATA=m
# CONFIG_PATA_MPIIX is not set
# CONFIG_PATA_OLDPIIX is not set
# CONFIG_PATA_NETCELL is not set
# CONFIG_PATA_NINJA32 is not set
# CONFIG_PATA_NS87410 is not set
# CONFIG_PATA_NS87415 is not set
# CONFIG_PATA_OPTI is not set
......@@ -622,7 +628,6 @@ CONFIG_NETDEVICES=y
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_VETH is not set
# CONFIG_IP1000 is not set
# CONFIG_ARCNET is not set
# CONFIG_PHYLIB is not set
CONFIG_NET_ETHERNET=y
......@@ -653,6 +658,7 @@ CONFIG_E100=y
# CONFIG_NE2K_PCI is not set
# CONFIG_8139CP is not set
# CONFIG_8139TOO is not set
# CONFIG_R6040 is not set
# CONFIG_SIS900 is not set
# CONFIG_EPIC100 is not set
# CONFIG_SUNDANCE is not set
......@@ -666,6 +672,9 @@ CONFIG_E1000=y
CONFIG_E1000_NAPI=y
# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
# CONFIG_E1000E is not set
# CONFIG_E1000E_ENABLED is not set
# CONFIG_IP1000 is not set
# CONFIG_IGB is not set
# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
......@@ -691,6 +700,7 @@ CONFIG_NETDEV_10000=y
# CONFIG_NIU is not set
# CONFIG_MLX4_CORE is not set
# CONFIG_TEHUTI is not set
# CONFIG_BNX2X is not set
# CONFIG_TR is not set
#
......@@ -713,7 +723,6 @@ CONFIG_NETDEV_10000=y
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_NET_FC is not set
# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
......@@ -761,6 +770,7 @@ CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_NOZOMI is not set
#
# Serial drivers
......@@ -832,13 +842,12 @@ CONFIG_I2C_MV64XXX=y
#
# Miscellaneous I2C Chip support
#
# CONFIG_SENSORS_DS1337 is not set
# CONFIG_SENSORS_DS1374 is not set
# CONFIG_DS1682 is not set
# CONFIG_SENSORS_EEPROM is not set
# CONFIG_SENSORS_PCF8574 is not set
# CONFIG_SENSORS_PCA9539 is not set
# CONFIG_PCF8575 is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_TPS65010 is not set
# CONFIG_SENSORS_MAX6875 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
......@@ -967,6 +976,7 @@ CONFIG_USB_ARCH_HAS_OHCI=y
CONFIG_USB_ARCH_HAS_EHCI=y
CONFIG_USB=y
# CONFIG_USB_DEBUG is not set
# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
#
# Miscellaneous USB options
......@@ -980,16 +990,12 @@ CONFIG_USB_DEVICE_CLASS=y
# USB Host Controller Drivers
#
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_SPLIT_ISO=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
CONFIG_USB_EHCI_TT_NEWSCHED=y
# CONFIG_USB_ISP116X_HCD is not set
CONFIG_USB_OHCI_HCD=y
# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
CONFIG_USB_OHCI_LITTLE_ENDIAN=y
CONFIG_USB_UHCI_HCD=y
CONFIG_USB_SL811_HCD=y
# CONFIG_USB_OHCI_HCD is not set
# CONFIG_USB_UHCI_HCD is not set
# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_R8A66597_HCD is not set
#
......@@ -1029,10 +1035,6 @@ CONFIG_USB_STORAGE_JUMPSHOT=y
#
# USB port drivers
#
#
# USB Serial Converter support
#
# CONFIG_USB_SERIAL is not set
#
......@@ -1058,14 +1060,6 @@ CONFIG_USB_STORAGE_JUMPSHOT=y
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
#
# USB DSL modem support
#
#
# USB Gadget Support
#
# CONFIG_USB_GADGET is not set
# CONFIG_MMC is not set
CONFIG_NEW_LEDS=y
......@@ -1120,9 +1114,10 @@ CONFIG_RTC_DRV_M41T80=y
# Platform RTC drivers
#
# CONFIG_RTC_DRV_CMOS is not set
# CONFIG_RTC_DRV_DS1511 is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_V3020 is not set
......@@ -1298,9 +1293,6 @@ CONFIG_NLS_ISO8859_2=y
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_UTF8 is not set
# CONFIG_DLM is not set
CONFIG_INSTRUMENTATION=y
# CONFIG_PROFILING is not set
# CONFIG_MARKERS is not set
#
# Kernel hacking
......@@ -1327,6 +1319,7 @@ CONFIG_DEBUG_USER=y
CONFIG_CRYPTO=y
CONFIG_CRYPTO_ALGAPI=m
CONFIG_CRYPTO_BLKCIPHER=m
# CONFIG_CRYPTO_SEQIV is not set
CONFIG_CRYPTO_MANAGER=m
# CONFIG_CRYPTO_HMAC is not set
# CONFIG_CRYPTO_XCBC is not set
......@@ -1344,6 +1337,9 @@ CONFIG_CRYPTO_CBC=m
CONFIG_CRYPTO_PCBC=m
# CONFIG_CRYPTO_LRW is not set
# CONFIG_CRYPTO_XTS is not set
# CONFIG_CRYPTO_CTR is not set
# CONFIG_CRYPTO_GCM is not set
# CONFIG_CRYPTO_CCM is not set
# CONFIG_CRYPTO_CRYPTD is not set
# CONFIG_CRYPTO_DES is not set
# CONFIG_CRYPTO_FCRYPT is not set
......@@ -1358,13 +1354,16 @@ CONFIG_CRYPTO_PCBC=m
# CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_ANUBIS is not set
# CONFIG_CRYPTO_SEED is not set
# CONFIG_CRYPTO_SALSA20 is not set
# CONFIG_CRYPTO_DEFLATE is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_CRC32C is not set
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_TEST is not set
# CONFIG_CRYPTO_AUTHENC is not set
# CONFIG_CRYPTO_LZO is not set
CONFIG_CRYPTO_HW=y
# CONFIG_CRYPTO_DEV_HIFN_795X is not set
#
# Library routines
......
arch/arm/kernel/setup.c
View file @ 0eccf60b
......@@ -1001,7 +1001,7 @@ static void c_stop(struct seq_file *m, void *v)
{
}
struct seq_operations cpuinfo_op = {
const struct seq_operations cpuinfo_op = {
.start = c_start,
.next = c_next,
.stop = c_stop,
......
arch/arm/mach-at91/clock.c
View file @ 0eccf60b
......@@ -343,7 +343,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
EXPORT_SYMBOL(clk_set_parent);
/* establish PCK0..PCK3 parentage and rate */
static void init_programmable_clock(struct clk *clk)
static void __init init_programmable_clock(struct clk *clk)
{
struct clk *parent;
u32 pckr;
......
arch/arm/mach-davinci/clock.c
View file @ 0eccf60b
......@@ -290,7 +290,7 @@ static int davinci_ck_show(struct seq_file *m, void *v)
return 0;
}
static struct seq_operations davinci_ck_op = {
static const struct seq_operations davinci_ck_op = {
.start = davinci_ck_start,
.next = davinci_ck_next,
.stop = davinci_ck_stop,
......@@ -302,7 +302,7 @@ static int davinci_ck_open(struct inode *inode, struct file *file)
return seq_open(file, &davinci_ck_op);
}
static struct file_operations proc_davinci_ck_operations = {
static const struct file_operations proc_davinci_ck_operations = {
.open = davinci_ck_open,
.read = seq_read,
.llseek = seq_lseek,
......
arch/arm/mach-omap1/Makefile
View file @ 0eccf60b
......@@ -13,20 +13,20 @@ obj-$(CONFIG_PM) += pm.o sleep.o
led-y := leds.o
# Specific board support
obj-$(CONFIG_MACH_OMAP_H2) += board-h2.o
obj-$(CONFIG_MACH_OMAP_H2) += board-h2.o board-h2-mmc.o
obj-$(CONFIG_MACH_OMAP_INNOVATOR) += board-innovator.o
obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
obj-$(CONFIG_MACH_OMAP_PERSEUS2) += board-perseus2.o
obj-$(CONFIG_MACH_OMAP_FSAMPLE) += board-fsample.o
obj-$(CONFIG_MACH_OMAP_OSK) += board-osk.o
obj-$(CONFIG_MACH_OMAP_H3) += board-h3.o
obj-$(CONFIG_MACH_OMAP_H3) += board-h3.o board-h3-mmc.o
obj-$(CONFIG_MACH_VOICEBLUE) += board-voiceblue.o
obj-$(CONFIG_MACH_OMAP_PALMTE) += board-palmte.o
obj-$(CONFIG_MACH_OMAP_PALMZ71) += board-palmz71.o
obj-$(CONFIG_MACH_OMAP_PALMTT) += board-palmtt.o
obj-$(CONFIG_MACH_NOKIA770) += board-nokia770.o
obj-$(CONFIG_MACH_AMS_DELTA) += board-ams-delta.o
obj-$(CONFIG_MACH_SX1) += board-sx1.o
obj-$(CONFIG_MACH_SX1) += board-sx1.o board-sx1-mmc.o
ifeq ($(CONFIG_ARCH_OMAP15XX),y)
# Innovator-1510 FPGA
......
arch/arm/mach-omap1/board-ams-delta.c
View file @ 0eccf60b
......@@ -135,21 +135,21 @@ static void __init ams_delta_init_irq(void)
}
static struct map_desc ams_delta_io_desc[] __initdata = {
// AMS_DELTA_LATCH1
/* AMS_DELTA_LATCH1 */
{
.virtual = AMS_DELTA_LATCH1_VIRT,
.pfn = __phys_to_pfn(AMS_DELTA_LATCH1_PHYS),
.length = 0x01000000,
.type = MT_DEVICE
},
// AMS_DELTA_LATCH2
/* AMS_DELTA_LATCH2 */
{
.virtual = AMS_DELTA_LATCH2_VIRT,
.pfn = __phys_to_pfn(AMS_DELTA_LATCH2_PHYS),
.length = 0x01000000,
.type = MT_DEVICE
},
// AMS_DELTA_MODEM
/* AMS_DELTA_MODEM */
{
.virtual = AMS_DELTA_MODEM_VIRT,
.pfn = __phys_to_pfn(AMS_DELTA_MODEM_PHYS),
......@@ -227,6 +227,7 @@ static void __init ams_delta_init(void)
omap_board_config = ams_delta_config;
omap_board_config_size = ARRAY_SIZE(ams_delta_config);
omap_serial_init();
omap_register_i2c_bus(1, 100, NULL, 0);
/* Clear latch2 (NAND, LCD, modem enable) */
ams_delta_latch2_write(~0, 0);
......
arch/arm/mach-omap1/board-fsample.c
View file @ 0eccf60b
......@@ -30,6 +30,7 @@
#include <asm/arch/gpio.h>
#include <asm/arch/mux.h>
#include <asm/arch/fpga.h>
#include <asm/arch/nand.h>
#include <asm/arch/keypad.h>
#include <asm/arch/common.h>
#include <asm/arch/board.h>
......@@ -134,7 +135,7 @@ static struct platform_device nor_device = {
.resource = &nor_resource,
};
static struct nand_platform_data nand_data = {
static struct omap_nand_platform_data nand_data = {
.options = NAND_SAMSUNG_LP_OPTIONS,
};
......@@ -202,7 +203,7 @@ static struct platform_device *devices[] __initdata = {
#define P2_NAND_RB_GPIO_PIN 62
static int nand_dev_ready(struct nand_platform_data *data)
static int nand_dev_ready(struct omap_nand_platform_data *data)
{
return omap_get_gpio_datain(P2_NAND_RB_GPIO_PIN);
}
......@@ -233,6 +234,7 @@ static void __init omap_fsample_init(void)
omap_board_config = fsample_config;
omap_board_config_size = ARRAY_SIZE(fsample_config);
omap_serial_init();
omap_register_i2c_bus(1, 100, NULL, 0);
}
static void __init fsample_init_smc91x(void)
......
arch/arm/mach-omap1/board-generic.c
View file @ 0eccf60b
......@@ -55,33 +55,14 @@ static struct omap_usb_config generic1610_usb_config __initdata = {
.hmc_mode = 16,
.pins[0] = 6,
};
static struct omap_mmc_config generic_mmc_config __initdata = {
.mmc [0] = {
.enabled = 0,
.wire4 = 0,
.wp_pin = -1,
.power_pin = -1,
.switch_pin = -1,
},
.mmc [1] = {
.enabled = 0,
.wire4 = 0,
.wp_pin = -1,
.power_pin = -1,
.switch_pin = -1,
},
};
#endif
static struct omap_uart_config generic_uart_config __initdata = {
.enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
};
static struct omap_board_config_kernel generic_config[] = {
{ OMAP_TAG_USB, NULL },
{ OMAP_TAG_MMC, &generic_mmc_config },
static struct omap_board_config_kernel generic_config[] __initdata = {
{ OMAP_TAG_USB, NULL },
{ OMAP_TAG_UART, &generic_uart_config },
};
......@@ -101,6 +82,7 @@ static void __init omap_generic_init(void)
omap_board_config = generic_config;
omap_board_config_size = ARRAY_SIZE(generic_config);
omap_serial_init();
omap_register_i2c_bus(1, 100, NULL, 0);
}
static void __init omap_generic_map_io(void)
......
arch/arm/mach-omap1/board-h2-mmc.c 0 → 100644
View file @ 0eccf60b
/*
* linux/arch/arm/mach-omap1/board-h2-mmc.c
*
* Copyright (C) 2007 Instituto Nokia de Tecnologia - INdT
* Author: Felipe Balbi <felipe.lima@indt.org.br>
*
* This code is based on linux/arch/arm/mach-omap2/board-n800-mmc.c, which is:
* Copyright (C) 2006 Nokia Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <asm/arch/mmc.h>
#include <asm/arch/gpio.h>
#ifdef CONFIG_MMC_OMAP
static int slot_cover_open;
static struct device *mmc_device;
static int h2_mmc_set_power(struct device *dev, int slot, int power_on,
int vdd)
{
#ifdef CONFIG_MMC_DEBUG
dev_dbg(dev, "Set slot %d power: %s (vdd %d)\n", slot + 1,
power_on ? "on" : "off", vdd);
#endif
if (slot != 0) {
dev_err(dev, "No such slot %d\n", slot + 1);
return -ENODEV;
}
return 0;
}
static int h2_mmc_set_bus_mode(struct device *dev, int slot, int bus_mode)
{
#ifdef CONFIG_MMC_DEBUG
dev_dbg(dev, "Set slot %d bus_mode %s\n", slot + 1,
bus_mode == MMC_BUSMODE_OPENDRAIN ? "open-drain" : "push-pull");
#endif
if (slot != 0) {
dev_err(dev, "No such slot %d\n", slot + 1);
return -ENODEV;
}
return 0;
}
static int h2_mmc_get_cover_state(struct device *dev, int slot)
{
BUG_ON(slot != 0);
return slot_cover_open;
}
void h2_mmc_slot_cover_handler(void *arg, int state)
{
if (mmc_device == NULL)
return;
slot_cover_open = state;
omap_mmc_notify_cover_event(mmc_device, 0, state);
}
static int h2_mmc_late_init(struct device *dev)
{
int ret = 0;
mmc_device = dev;
return ret;
}
static void h2_mmc_cleanup(struct device *dev)
{
}
static struct omap_mmc_platform_data h2_mmc_data = {
.nr_slots = 1,
.switch_slot = NULL,
.init = h2_mmc_late_init,
.cleanup = h2_mmc_cleanup,
.slots[0] = {
.set_power = h2_mmc_set_power,
.set_bus_mode = h2_mmc_set_bus_mode,
.get_ro = NULL,
.get_cover_state = h2_mmc_get_cover_state,
.ocr_mask = MMC_VDD_28_29 | MMC_VDD_30_31 |
MMC_VDD_32_33 | MMC_VDD_33_34,
.name = "mmcblk",
},
};
void __init h2_mmc_init(void)
{
omap_set_mmc_info(1, &h2_mmc_data);
}
#else
void __init h2_mmc_init(void)
{
}
void h2_mmc_slot_cover_handler(void *arg, int state)
{
}
#endif
arch/arm/mach-omap1/board-h2.c
View file @ 0eccf60b
......@@ -37,8 +37,10 @@
#include <asm/mach/flash.h>
#include <asm/mach/map.h>
#include <asm/arch/gpio-switch.h>
#include <asm/arch/mux.h>
#include <asm/arch/tc.h>
#include <asm/arch/nand.h>
#include <asm/arch/irda.h>
#include <asm/arch/usb.h>
#include <asm/arch/keypad.h>
......@@ -46,8 +48,6 @@
#include <asm/arch/mcbsp.h>
#include <asm/arch/omap-alsa.h>
extern int omap_gpio_init(void);
static int h2_keymap[] = {
KEY(0, 0, KEY_LEFT),
KEY(0, 1, KEY_RIGHT),
......@@ -140,8 +140,6 @@ static struct platform_device h2_nor_device = {
.resource = &h2_nor_resource,
};
#if 0 /* REVISIT: Enable when nand_platform_data is applied */
static struct mtd_partition h2_nand_partitions[] = {
#if 0
/* REVISIT: enable these partitions if you make NAND BOOT
......@@ -179,7 +177,7 @@ static struct mtd_partition h2_nand_partitions[] = {
};
/* dip switches control NAND chip access: 8 bit, 16 bit, or neither */
static struct nand_platform_data h2_nand_data = {
static struct omap_nand_platform_data h2_nand_data = {
.options = NAND_SAMSUNG_LP_OPTIONS,
.parts = h2_nand_partitions,
.nr_parts = ARRAY_SIZE(h2_nand_partitions),
......@@ -198,7 +196,6 @@ static struct platform_device h2_nand_device = {
.num_resources = 1,
.resource = &h2_nand_resource,
};
#endif
static struct resource h2_smc91x_resources[] = {
[0] = {
......@@ -311,18 +308,18 @@ static struct omap_mcbsp_reg_cfg mcbsp_regs = {
.srgr2 = GSYNC | CLKSP | FSGM | FPER(31),
.pcr0 = CLKXM | CLKRM | FSXP | FSRP | CLKXP | CLKRP,
//.pcr0 = CLKXP | CLKRP, /* mcbsp: slave */
/*.pcr0 = CLKXP | CLKRP,*/ /* mcbsp: slave */
};
static struct omap_alsa_codec_config alsa_config = {
.name = "H2 TSC2101",
.mcbsp_regs_alsa = &mcbsp_regs,
.codec_configure_dev = NULL, // tsc2101_configure,
.codec_set_samplerate = NULL, // tsc2101_set_samplerate,
.codec_clock_setup = NULL, // tsc2101_clock_setup,
.codec_clock_on = NULL, // tsc2101_clock_on,
.codec_clock_off = NULL, // tsc2101_clock_off,
.get_default_samplerate = NULL, // tsc2101_get_default_samplerate,
.codec_configure_dev = NULL, /* tsc2101_configure, */
.codec_set_samplerate = NULL, /* tsc2101_set_samplerate, */
.codec_clock_setup = NULL, /* tsc2101_clock_setup, */
.codec_clock_on = NULL, /* tsc2101_clock_on, */
.codec_clock_off = NULL, /* tsc2101_clock_off, */
.get_default_samplerate = NULL, /* tsc2101_get_default_samplerate, */
};
static struct platform_device h2_mcbsp1_device = {
......@@ -335,7 +332,7 @@ static struct platform_device h2_mcbsp1_device = {
static struct platform_device *h2_devices[] __initdata = {
&h2_nor_device,
//&h2_nand_device,
&h2_nand_device,
&h2_smc91x_device,
&h2_irda_device,
&h2_kp_device,
......@@ -343,22 +340,6 @@ static struct platform_device *h2_devices[] __initdata = {
&h2_mcbsp1_device,
};
#ifdef CONFIG_I2C_BOARDINFO
static struct i2c_board_info __initdata h2_i2c_board_info[] = {
{
I2C_BOARD_INFO("tps65010", 0x48),
.type = "tps65010",
.irq = OMAP_GPIO_IRQ(58),
},
/* TODO when driver support is ready:
* - isp1301 OTG transceiver
* - optional ov9640 camera sensor at 0x30
* - pcf9754 for aGPS control
* - ... etc
*/
};
#endif
static void __init h2_init_smc91x(void)
{
if ((omap_request_gpio(0)) < 0) {
......@@ -367,6 +348,14 @@ static void __init h2_init_smc91x(void)
}
}
static struct i2c_board_info __initdata h2_i2c_board_info[] = {
{
I2C_BOARD_INFO("isp1301_omap", 0x2d),
.type = "isp1301_omap",
.irq = OMAP_GPIO_IRQ(2),
},
};
static void __init h2_init_irq(void)
{
omap1_init_common_hw();
......@@ -380,26 +369,25 @@ static struct omap_usb_config h2_usb_config __initdata = {
.otg = 2,
#ifdef CONFIG_USB_GADGET_OMAP
.hmc_mode = 19, // 0:host(off) 1:dev|otg 2:disabled
// .hmc_mode = 21, // 0:host(off) 1:dev(loopback) 2:host(loopback)
.hmc_mode = 19, /* 0:host(off) 1:dev|otg 2:disabled */
/* .hmc_mode = 21,*/ /* 0:host(off) 1:dev(loopback) 2:host(loopback) */
#elif defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
/* needs OTG cable, or NONSTANDARD (B-to-MiniB) */
.hmc_mode = 20, // 1:dev|otg(off) 1:host 2:disabled
.hmc_mode = 20, /* 1:dev|otg(off) 1:host 2:disabled */
#endif
.pins[1] = 3,
};
static struct omap_mmc_config h2_mmc_config __initdata = {
.mmc [0] = {
.enabled = 1,
.mmc[0] = {
.enabled = 1,
.wire4 = 1,
.wp_pin = OMAP_MPUIO(3),
.power_pin = -1, /* tps65010 gpio3 */
.switch_pin = OMAP_MPUIO(1),
},
};
extern struct omap_mmc_platform_data h2_mmc_data;
static struct omap_uart_config h2_uart_config __initdata = {
.enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
};
......@@ -409,15 +397,15 @@ static struct omap_lcd_config h2_lcd_config __initdata = {
};
static struct omap_board_config_kernel h2_config[] __initdata = {
{ OMAP_TAG_USB, &h2_usb_config },
{ OMAP_TAG_MMC, &h2_mmc_config },
{ OMAP_TAG_USB, &h2_usb_config },
{ OMAP_TAG_MMC, &h2_mmc_config },
{ OMAP_TAG_UART, &h2_uart_config },
{ OMAP_TAG_LCD, &h2_lcd_config },
};
#define H2_NAND_RB_GPIO_PIN 62
static int h2_nand_dev_ready(struct nand_platform_data *data)
static int h2_nand_dev_ready(struct omap_nand_platform_data *data)
{
return omap_get_gpio_datain(H2_NAND_RB_GPIO_PIN);
}
......@@ -436,18 +424,16 @@ static void __init h2_init(void)
h2_nor_resource.end = h2_nor_resource.start = omap_cs3_phys();
h2_nor_resource.end += SZ_32M - 1;
#if 0 /* REVISIT: Enable when nand_platform_data is applied */
h2_nand_resource.end = h2_nand_resource.start = OMAP_CS2B_PHYS;
h2_nand_resource.end += SZ_4K - 1;
if (!(omap_request_gpio(H2_NAND_RB_GPIO_PIN)))
h2_nand_data.dev_ready = h2_nand_dev_ready;
#endif
omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
/* MMC: card detect and WP */
// omap_cfg_reg(U19_ARMIO1); /* CD */
/* omap_cfg_reg(U19_ARMIO1); */ /* CD */
omap_cfg_reg(BALLOUT_V8_ARMIO3); /* WP */
/* Irda */
......@@ -463,16 +449,9 @@ static void __init h2_init(void)
omap_board_config = h2_config;
omap_board_config_size = ARRAY_SIZE(h2_config);
omap_serial_init();
/* irq for tps65010 chip */
omap_cfg_reg(W4_GPIO58);
if (gpio_request(58, "tps65010") == 0)
gpio_direction_input(58);
#ifdef CONFIG_I2C_BOARDINFO
i2c_register_board_info(1, h2_i2c_board_info,
ARRAY_SIZE(h2_i2c_board_info));
#endif
omap_register_i2c_bus(1, 100, h2_i2c_board_info,
ARRAY_SIZE(h2_i2c_board_info));
h2_mmc_init();
}
static void __init h2_map_io(void)
......@@ -480,22 +459,6 @@ static void __init h2_map_io(void)
omap1_map_common_io();
}
#ifdef CONFIG_TPS65010
static int __init h2_tps_init(void)
{
if (!machine_is_omap_h2())
return 0;
/* gpio3 for SD, gpio4 for VDD_DSP */
/* FIXME send power to DSP iff it's configured */
/* Enable LOW_PWR */
tps65010_set_low_pwr(ON);
return 0;
}
fs_initcall(h2_tps_init);
#endif
MACHINE_START(OMAP_H2, "TI-H2")
/* Maintainer: Imre Deak <imre.deak@nokia.com> */
.phys_io = 0xfff00000,
......
arch/arm/mach-omap1/board-h3-mmc.c 0 → 100644
View file @ 0eccf60b
/*
* linux/arch/arm/mach-omap1/board-h3-mmc.c
*
* Copyright (C) 2007 Instituto Nokia de Tecnologia - INdT
* Author: Felipe Balbi <felipe.lima@indt.org.br>
*
* This code is based on linux/arch/arm/mach-omap2/board-n800-mmc.c, which is:
* Copyright (C) 2006 Nokia Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <asm/arch/mmc.h>
#include <asm/arch/gpio.h>
#ifdef CONFIG_MMC_OMAP
static int slot_cover_open;
static struct device *mmc_device;
static int h3_mmc_set_power(struct device *dev, int slot, int power_on,
int vdd)
{
#ifdef CONFIG_MMC_DEBUG
dev_dbg(dev, "Set slot %d power: %s (vdd %d)\n", slot + 1,
power_on ? "on" : "off", vdd);
#endif
if (slot != 0) {
dev_err(dev, "No such slot %d\n", slot + 1);
return -ENODEV;
}
return 0;
}
static int h3_mmc_set_bus_mode(struct device *dev, int slot, int bus_mode)
{
int ret = 0;
#ifdef CONFIG_MMC_DEBUG
dev_dbg(dev, "Set slot %d bus_mode %s\n", slot + 1,
bus_mode == MMC_BUSMODE_OPENDRAIN ? "open-drain" : "push-pull");
#endif
if (slot != 0) {
dev_err(dev, "No such slot %d\n", slot + 1);
return -ENODEV;
}
/* Treated on upper level */
return bus_mode;
}
static int h3_mmc_get_cover_state(struct device *dev, int slot)
{
BUG_ON(slot != 0);
return slot_cover_open;
}
void h3_mmc_slot_cover_handler(void *arg, int state)
{
if (mmc_device == NULL)
return;
slot_cover_open = state;
omap_mmc_notify_cover_event(mmc_device, 0, state);
}
static int h3_mmc_late_init(struct device *dev)
{
int ret = 0;
mmc_device = dev;
return ret;
}
static void h3_mmc_cleanup(struct device *dev)
{
}
static struct omap_mmc_platform_data h3_mmc_data = {
.nr_slots = 1,
.switch_slot = NULL,
.init = h3_mmc_late_init,
.cleanup = h3_mmc_cleanup,
.slots[0] = {
.set_power = h3_mmc_set_power,
.set_bus_mode = h3_mmc_set_bus_mode,
.get_ro = NULL,
.get_cover_state = h3_mmc_get_cover_state,
.ocr_mask = MMC_VDD_28_29 | MMC_VDD_30_31 |
MMC_VDD_32_33 | MMC_VDD_33_34,
.name = "mmcblk",
},
};
void __init h3_mmc_init(void)
{
omap_set_mmc_info(1, &h3_mmc_data);
}
#else
void __init h3_mmc_init(void)
{
}
void h3_mmc_slot_cover_handler(void *arg, int state)
{
}
#endif
arch/arm/mach-omap1/board-h3.c
View file @ 0eccf60b
......@@ -42,6 +42,7 @@
#include <asm/arch/irqs.h>
#include <asm/arch/mux.h>
#include <asm/arch/tc.h>
#include <asm/arch/nand.h>
#include <asm/arch/irda.h>
#include <asm/arch/usb.h>
#include <asm/arch/keypad.h>
......@@ -50,8 +51,6 @@
#include <asm/arch/mcbsp.h>
#include <asm/arch/omap-alsa.h>
extern int omap_gpio_init(void);
static int h3_keymap[] = {
KEY(0, 0, KEY_LEFT),
KEY(0, 1, KEY_RIGHT),
......@@ -179,7 +178,7 @@ static struct mtd_partition nand_partitions[] = {
};
/* dip switches control NAND chip access: 8 bit, 16 bit, or neither */
static struct nand_platform_data nand_data = {
static struct omap_nand_platform_data nand_data = {
.options = NAND_SAMSUNG_LP_OPTIONS,
.parts = nand_partitions,
.nr_parts = ARRAY_SIZE(nand_partitions),
......@@ -387,18 +386,18 @@ static struct omap_mcbsp_reg_cfg mcbsp_regs = {
.srgr2 = GSYNC | CLKSP | FSGM | FPER(31),
.pcr0 = CLKRM | SCLKME | FSXP | FSRP | CLKXP | CLKRP,
//.pcr0 = CLKXP | CLKRP, /* mcbsp: slave */
/*.pcr0 = CLKXP | CLKRP,*/ /* mcbsp: slave */
};
static struct omap_alsa_codec_config alsa_config = {
.name = "H3 TSC2101",
.mcbsp_regs_alsa = &mcbsp_regs,
.codec_configure_dev = NULL, // tsc2101_configure,
.codec_set_samplerate = NULL, // tsc2101_set_samplerate,
.codec_clock_setup = NULL, // tsc2101_clock_setup,
.codec_clock_on = NULL, // tsc2101_clock_on,
.codec_clock_off = NULL, // tsc2101_clock_off,
.get_default_samplerate = NULL, // tsc2101_get_default_samplerate,
.codec_configure_dev = NULL, /* tsc2101_configure, */
.codec_set_samplerate = NULL, /* tsc2101_set_samplerate, */
.codec_clock_setup = NULL, /* tsc2101_clock_setup, */
.codec_clock_on = NULL, /* tsc2101_clock_on, */
.codec_clock_off = NULL, /* tsc2101_clock_off, */
.get_default_samplerate = NULL, /* tsc2101_get_default_samplerate, */
};
static struct platform_device h3_mcbsp1_device = {
......@@ -436,12 +435,13 @@ static struct omap_usb_config h3_usb_config __initdata = {
static struct omap_mmc_config h3_mmc_config __initdata = {
.mmc[0] = {
.enabled = 1,
.power_pin = -1, /* tps65010 GPIO4 */
.switch_pin = OMAP_MPUIO(1),
},
.enabled = 1,
.wire4 = 1,
},
};
extern struct omap_mmc_platform_data h3_mmc_data;
static struct omap_uart_config h3_uart_config __initdata = {
.enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
};
......@@ -450,29 +450,28 @@ static struct omap_lcd_config h3_lcd_config __initdata = {
.ctrl_name = "internal",
};
static struct omap_board_config_kernel h3_config[] = {
static struct omap_board_config_kernel h3_config[] __initdata = {
{ OMAP_TAG_USB, &h3_usb_config },
{ OMAP_TAG_MMC, &h3_mmc_config },
{ OMAP_TAG_UART, &h3_uart_config },
{ OMAP_TAG_LCD, &h3_lcd_config },
};
static struct i2c_board_info __initdata h3_i2c_board_info[] = {
static struct omap_gpio_switch h3_gpio_switches[] __initdata = {
{
I2C_BOARD_INFO("tps65010", 0x48),
.type = "tps65013",
/* .irq = OMAP_GPIO_IRQ(??), */
.name = "mmc_slot",
.gpio = OMAP_MPUIO(1),
.type = OMAP_GPIO_SWITCH_TYPE_COVER,
.debounce_rising = 100,
.debounce_falling = 0,
.notify = h3_mmc_slot_cover_handler,
.notify_data = NULL,
},
/* TODO when driver support is ready:
* - isp1301 OTG transceiver
* - optional ov9640 camera sensor at 0x30
* - ...
*/
};
#define H3_NAND_RB_GPIO_PIN 10
static int nand_dev_ready(struct nand_platform_data *data)
static int nand_dev_ready(struct omap_nand_platform_data *data)
{
return omap_get_gpio_datain(H3_NAND_RB_GPIO_PIN);
}
......@@ -500,13 +499,14 @@ static void __init h3_init(void)
omap_cfg_reg(V2_1710_GPIO10);
platform_add_devices(devices, ARRAY_SIZE(devices));
spi_register_board_info(h3_spi_board_info,
ARRAY_SIZE(h3_spi_board_info));
omap_board_config = h3_config;
omap_board_config_size = ARRAY_SIZE(h3_config);
omap_serial_init();
/* FIXME setup irq for tps65013 chip */
i2c_register_board_info(1, h3_i2c_board_info,
ARRAY_SIZE(h3_i2c_board_info));
omap_register_i2c_bus(1, 100, h3_i2c_board_info,
ARRAY_SIZE(h3_i2c_board_info));
h3_mmc_init();
}
static void __init h3_init_smc91x(void)
......@@ -531,23 +531,6 @@ static void __init h3_map_io(void)
omap1_map_common_io();
}
#ifdef CONFIG_TPS65010
static int __init h3_tps_init(void)
{
if (!machine_is_omap_h3())
return 0;
/* gpio4 for SD, gpio3 for VDD_DSP */
/* FIXME send power to DSP iff it's configured */
/* Enable LOW_PWR */
tps65013_set_low_pwr(ON);
return 0;
}
fs_initcall(h3_tps_init);
#endif
MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
/* Maintainer: Texas Instruments, Inc. */
.phys_io = 0xfff00000,
......
arch/arm/mach-omap1/board-innovator.c
View file @ 0eccf60b
......@@ -134,12 +134,12 @@ static struct omap_mcbsp_reg_cfg mcbsp_regs = {
static struct omap_alsa_codec_config alsa_config = {
.name = "OMAP Innovator AIC23",
.mcbsp_regs_alsa = &mcbsp_regs,
.codec_configure_dev = NULL, // aic23_configure,
.codec_set_samplerate = NULL, // aic23_set_samplerate,
.codec_clock_setup = NULL, // aic23_clock_setup,
.codec_clock_on = NULL, // aic23_clock_on,
.codec_clock_off = NULL, // aic23_clock_off,
.get_default_samplerate = NULL, // aic23_get_default_samplerate,
.codec_configure_dev = NULL, /* aic23_configure, */
.codec_set_samplerate = NULL, /* aic23_set_samplerate, */
.codec_clock_setup = NULL, /* aic23_clock_setup, */
.codec_clock_on = NULL, /* aic23_clock_on, */
.codec_clock_off = NULL, /* aic23_clock_off, */
.get_default_samplerate = NULL, /* aic23_get_default_samplerate, */
};
static struct platform_device innovator_mcbsp1_device = {
......@@ -345,11 +345,11 @@ static struct omap_usb_config h2_usb_config __initdata = {
.otg = 2,
#ifdef CONFIG_USB_GADGET_OMAP
.hmc_mode = 19, // 0:host(off) 1:dev|otg 2:disabled
// .hmc_mode = 21, // 0:host(off) 1:dev(loopback) 2:host(loopback)
.hmc_mode = 19, /* 0:host(off) 1:dev|otg 2:disabled */
/* .hmc_mode = 21,*/ /* 0:host(off) 1:dev(loopback) 2:host(loopback) */
#elif defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
/* NONSTANDARD CABLE NEEDED (B-to-Mini-B) */
.hmc_mode = 20, // 1:dev|otg(off) 1:host 2:disabled
.hmc_mode = 20, /* 1:dev|otg(off) 1:host 2:disabled */
#endif
.pins[1] = 3,
......@@ -411,6 +411,7 @@ static void __init innovator_init(void)
omap_board_config = innovator_config;
omap_board_config_size = ARRAY_SIZE(innovator_config);
omap_serial_init();
omap_register_i2c_bus(1, 100, NULL, 0);
}
static void __init innovator_map_io(void)
......
arch/arm/mach-omap1/board-nokia770.c
View file @ 0eccf60b
......@@ -189,7 +189,7 @@ static struct omap_mmc_config nokia770_mmc_config __initdata = {
},
};
static struct omap_board_config_kernel nokia770_config[] = {
static struct omap_board_config_kernel nokia770_config[] __initdata = {
{ OMAP_TAG_USB, NULL },
{ OMAP_TAG_MMC, &nokia770_mmc_config },
};
......@@ -330,6 +330,7 @@ static void __init omap_nokia770_init(void)
omap_board_config_size = ARRAY_SIZE(nokia770_config);
omap_gpio_init();
omap_serial_init();
omap_register_i2c_bus(1, 100, NULL, 0);
omap_dsp_init();
ads7846_dev_init();
mipid_dev_init();
......
arch/arm/mach-omap1/board-osk.c
View file @ 0eccf60b
......@@ -160,12 +160,12 @@ static struct omap_mcbsp_reg_cfg mcbsp_regs = {
static struct omap_alsa_codec_config alsa_config = {
.name = "OSK AIC23",
.mcbsp_regs_alsa = &mcbsp_regs,
.codec_configure_dev = NULL, // aic23_configure,
.codec_set_samplerate = NULL, // aic23_set_samplerate,
.codec_clock_setup = NULL, // aic23_clock_setup,
.codec_clock_on = NULL, // aic23_clock_on,
.codec_clock_off = NULL, // aic23_clock_off,
.get_default_samplerate = NULL, // aic23_get_default_samplerate,
.codec_configure_dev = NULL, /* aic23_configure, */
.codec_set_samplerate = NULL, /* aic23_set_samplerate, */
.codec_clock_setup = NULL, /* aic23_clock_setup, */
.codec_clock_on = NULL, /* aic23_clock_on, */
.codec_clock_off = NULL, /* aic23_clock_off, */
.get_default_samplerate = NULL, /* aic23_get_default_samplerate, */
};
static struct platform_device osk5912_mcbsp1_device = {
......@@ -253,7 +253,7 @@ static struct omap_lcd_config osk_lcd_config __initdata = {
};
#endif
static struct omap_board_config_kernel osk_config[] = {
static struct omap_board_config_kernel osk_config[] __initdata = {
{ OMAP_TAG_USB, &osk_usb_config },
{ OMAP_TAG_UART, &osk_uart_config },
#ifdef CONFIG_OMAP_OSK_MISTRAL
......@@ -392,7 +392,7 @@ static void __init osk_mistral_init(void)
omap_cfg_reg(W13_1610_CCP_CLKM);
omap_cfg_reg(Y12_1610_CCP_CLKP);
/* CCP_DATAM CONFLICTS WITH UART1.TX (and serial console) */
// omap_cfg_reg(Y14_1610_CCP_DATAM);
/* omap_cfg_reg(Y14_1610_CCP_DATAM); */
omap_cfg_reg(W14_1610_CCP_DATAP);
/* CAM_PWDN */
......@@ -404,8 +404,8 @@ static void __init osk_mistral_init(void)
pr_debug("OSK+Mistral: CAM_PWDN is awol\n");
// omap_cfg_reg(P19_1610_GPIO6); // BUSY
omap_cfg_reg(P20_1610_GPIO4); // PENIRQ
/* omap_cfg_reg(P19_1610_GPIO6); */ /* BUSY */
omap_cfg_reg(P20_1610_GPIO4); /* PENIRQ */
set_irq_type(OMAP_GPIO_IRQ(4), IRQT_FALLING);
spi_register_board_info(mistral_boardinfo,
ARRAY_SIZE(mistral_boardinfo));
......@@ -473,10 +473,9 @@ static void __init osk_init(void)
if (gpio_request(OMAP_MPUIO(1), "tps65010") == 0)
gpio_direction_input(OMAP_MPUIO(1));
i2c_register_board_info(1, osk_i2c_board_info,
ARRAY_SIZE(osk_i2c_board_info));
omap_serial_init();
omap_register_i2c_bus(1, 400, osk_i2c_board_info,
ARRAY_SIZE(osk_i2c_board_info));
osk_mistral_init();
}
......
arch/arm/mach-omap1/board-palmte.c
View file @ 0eccf60b
......@@ -10,6 +10,8 @@
* Maintainers : http://palmtelinux.sf.net
* palmtelinux-developpers@lists.sf.net
*
* Copyright (c) 2006 Andrzej Zaborowski <balrog@zabor.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
......@@ -24,8 +26,8 @@
#include <linux/spi/spi.h>
#include <linux/spi/tsc2102.h>
#include <linux/interrupt.h>
#include <linux/apm-emulation.h>
#include <asm/apm.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
......@@ -51,11 +53,11 @@ static void __init omap_palmte_init_irq(void)
omap_gpio_init();
}
static int palmte_keymap[] = {
KEY(0, 0, KEY_F1),
KEY(0, 1, KEY_F2),
KEY(0, 2, KEY_F3),
KEY(0, 3, KEY_F4),
static const int palmte_keymap[] = {
KEY(0, 0, KEY_F1), /* Calendar */
KEY(0, 1, KEY_F2), /* Contacts */
KEY(0, 2, KEY_F3), /* Tasks List */
KEY(0, 3, KEY_F4), /* Note Pad */
KEY(0, 4, KEY_POWER),
KEY(1, 0, KEY_LEFT),
KEY(1, 1, KEY_DOWN),
......@@ -68,7 +70,7 @@ static int palmte_keymap[] = {
static struct omap_kp_platform_data palmte_kp_data = {
.rows = 8,
.cols = 8,
.keymap = palmte_keymap,
.keymap = (int *) palmte_keymap,
.rep = 1,
.delay = 12,
};
......@@ -180,7 +182,7 @@ static struct platform_device palmte_irda_device = {
.resource = palmte_irda_resources,
};
static struct platform_device *devices[] __initdata = {
static struct platform_device *palmte_devices[] __initdata = {
&palmte_rom_device,
&palmte_kp_device,
&palmte_lcd_device,
......@@ -273,7 +275,7 @@ static void palmte_get_power_status(struct apm_power_info *info, int *battery)
info->time = 0;
} else {
while (hi > lo + 1) {
mid = (hi + lo) >> 2;
mid = (hi + lo) >> 1;
if (batt <= palmte_battery_sample[mid])
lo = mid;
else
......@@ -321,7 +323,7 @@ static struct tsc2102_config palmte_tsc2102_config = {
.alsa_config = &palmte_alsa_config,
};
static struct omap_board_config_kernel palmte_config[] = {
static struct omap_board_config_kernel palmte_config[] __initdata = {
{ OMAP_TAG_USB, &palmte_usb_config },
{ OMAP_TAG_MMC, &palmte_mmc_config },
{ OMAP_TAG_LCD, &palmte_lcd_config },
......@@ -339,74 +341,34 @@ static struct spi_board_info palmte_spi_info[] __initdata = {
},
};
/* Periodically check for changes on important input pins */
struct timer_list palmte_pin_timer;
int prev_power, prev_headphones;
static void palmte_pin_handler(unsigned long data) {
int power, headphones;
power = !omap_get_gpio_datain(PALMTE_DC_GPIO);
headphones = omap_get_gpio_datain(PALMTE_HEADPHONES_GPIO);
if (power && !prev_power)
printk(KERN_INFO "PM: cable connected\n");
else if (!power && prev_power)
printk(KERN_INFO "PM: cable disconnected\n");
if (headphones && !prev_headphones) {
static void palmte_headphones_detect(void *data, int state)
{
if (state) {
/* Headphones connected, disable speaker */
omap_set_gpio_dataout(PALMTE_SPEAKER_GPIO, 0);
printk(KERN_INFO "PM: speaker off\n");
} else if (!headphones && prev_headphones) {
} else {
/* Headphones unplugged, re-enable speaker */
omap_set_gpio_dataout(PALMTE_SPEAKER_GPIO, 1);
printk(KERN_INFO "PM: speaker on\n");
}
prev_power = power;
prev_headphones = headphones;
mod_timer(&palmte_pin_timer, jiffies + msecs_to_jiffies(500));
}
static void __init palmte_gpio_setup(void)
static void __init palmte_misc_gpio_setup(void)
{
/* Set TSC2102 PINTDAV pin as input */
/* Set TSC2102 PINTDAV pin as input (used by TSC2102 driver) */
if (omap_request_gpio(PALMTE_PINTDAV_GPIO)) {
printk(KERN_ERR "Could not reserve PINTDAV GPIO!\n");
return;
}
omap_set_gpio_direction(PALMTE_PINTDAV_GPIO, 1);
/* Monitor cable-connected signals */
if (omap_request_gpio(PALMTE_DC_GPIO) ||
omap_request_gpio(PALMTE_USB_OR_DC_GPIO) ||
omap_request_gpio(PALMTE_USBDETECT_GPIO)) {
/* Set USB-or-DC-IN pin as input (unused) */
if (omap_request_gpio(PALMTE_USB_OR_DC_GPIO)) {
printk(KERN_ERR "Could not reserve cable signal GPIO!\n");
return;
}
omap_set_gpio_direction(PALMTE_DC_GPIO, 1);
omap_set_gpio_direction(PALMTE_USB_OR_DC_GPIO, 1);
omap_set_gpio_direction(PALMTE_USBDETECT_GPIO, 1);
/* Set speaker-enable pin as output */
if (omap_request_gpio(PALMTE_SPEAKER_GPIO)) {
printk(KERN_ERR "Could not reserve speaker GPIO!\n");
return;
}
omap_set_gpio_direction(PALMTE_SPEAKER_GPIO, 0);
/* Monitor the headphones-connected signal */
if (omap_request_gpio(PALMTE_HEADPHONES_GPIO)) {
printk(KERN_ERR "Could not reserve headphones signal GPIO!\n");
return;
}
omap_set_gpio_direction(PALMTE_HEADPHONES_GPIO, 1);
prev_power = omap_get_gpio_datain(PALMTE_DC_GPIO);
prev_headphones = !omap_get_gpio_datain(PALMTE_HEADPHONES_GPIO);
setup_timer(&palmte_pin_timer, palmte_pin_handler, 0);
palmte_pin_handler(0);
}
static void __init omap_palmte_init(void)
......@@ -414,12 +376,12 @@ static void __init omap_palmte_init(void)
omap_board_config = palmte_config;
omap_board_config_size = ARRAY_SIZE(palmte_config);
platform_add_devices(devices, ARRAY_SIZE(devices));
platform_add_devices(palmte_devices, ARRAY_SIZE(palmte_devices));
spi_register_board_info(palmte_spi_info, ARRAY_SIZE(palmte_spi_info));
palmte_misc_gpio_setup();
omap_serial_init();
palmte_gpio_setup();
omap_register_i2c_bus(1, 100, NULL, 0);
}
static void __init omap_palmte_map_io(void)
......
arch/arm/mach-omap1/board-palmtt.c
View file @ 0eccf60b
......@@ -144,12 +144,12 @@ static struct omap_mcbsp_reg_cfg mcbsp_regs = {
static struct omap_alsa_codec_config alsa_config = {
.name = "PalmTT AIC23",
.mcbsp_regs_alsa = &mcbsp_regs,
.codec_configure_dev = NULL, // aic23_configure,
.codec_set_samplerate = NULL, // aic23_set_samplerate,
.codec_clock_setup = NULL, // aic23_clock_setup,
.codec_clock_on = NULL, // aic23_clock_on,
.codec_clock_off = NULL, // aic23_clock_off,
.get_default_samplerate = NULL, // aic23_get_default_samplerate,
.codec_configure_dev = NULL, /* aic23_configure, */
.codec_set_samplerate = NULL, /* aic23_set_samplerate, */
.codec_clock_setup = NULL, /* aic23_clock_setup, */
.codec_clock_on = NULL, /* aic23_clock_on, */
.codec_clock_off = NULL, /* aic23_clock_off, */
.get_default_samplerate = NULL, /* aic23_get_default_samplerate, */
};
static struct platform_device palmtt_mcbsp1_device = {
......@@ -312,7 +312,7 @@ static struct omap_uart_config palmtt_uart_config __initdata = {
.enabled_uarts = (1 << 0) | (1 << 1) | (0 << 2),
};
static struct omap_board_config_kernel palmtt_config[] = {
static struct omap_board_config_kernel palmtt_config[] __initdata = {
{ OMAP_TAG_USB, &palmtt_usb_config },
{ OMAP_TAG_LCD, &palmtt_lcd_config },
{ OMAP_TAG_UART, &palmtt_uart_config },
......@@ -338,6 +338,7 @@ static void __init omap_palmtt_init(void)
spi_register_board_info(palmtt_boardinfo,ARRAY_SIZE(palmtt_boardinfo));
omap_serial_init();
omap_register_i2c_bus(1, 100, NULL, 0);
}
static void __init omap_palmtt_map_io(void)
......
arch/arm/mach-omap1/board-palmz71.c
View file @ 0eccf60b
......@@ -285,7 +285,7 @@ static struct omap_uart_config palmz71_uart_config __initdata = {
.enabled_uarts = (1 << 0) | (1 << 1) | (0 << 2),
};
static struct omap_board_config_kernel palmz71_config[] = {
static struct omap_board_config_kernel palmz71_config[] __initdata = {
{OMAP_TAG_USB, &palmz71_usb_config},
{OMAP_TAG_MMC, &palmz71_mmc_config},
{OMAP_TAG_LCD, &palmz71_lcd_config},
......@@ -363,6 +363,7 @@ omap_palmz71_init(void)
spi_register_board_info(palmz71_boardinfo,
ARRAY_SIZE(palmz71_boardinfo));
omap_serial_init();
omap_register_i2c_bus(1, 100, NULL, 0);
palmz71_gpio_setup(0);
}
......
arch/arm/mach-omap1/board-perseus2.c
View file @ 0eccf60b
......@@ -30,6 +30,7 @@
#include <asm/arch/gpio.h>
#include <asm/arch/mux.h>
#include <asm/arch/fpga.h>
#include <asm/arch/nand.h>
#include <asm/arch/keypad.h>
#include <asm/arch/common.h>
#include <asm/arch/board.h>
......@@ -133,7 +134,7 @@ static struct platform_device nor_device = {
.resource = &nor_resource,
};
static struct nand_platform_data nand_data = {
static struct omap_nand_platform_data nand_data = {
.options = NAND_SAMSUNG_LP_OPTIONS,
};
......@@ -202,7 +203,7 @@ static struct platform_device *devices[] __initdata = {
#define P2_NAND_RB_GPIO_PIN 62
static int nand_dev_ready(struct nand_platform_data *data)
static int nand_dev_ready(struct omap_nand_platform_data *data)
{
return omap_get_gpio_datain(P2_NAND_RB_GPIO_PIN);
}
......@@ -215,7 +216,7 @@ static struct omap_lcd_config perseus2_lcd_config __initdata = {
.ctrl_name = "internal",
};
static struct omap_board_config_kernel perseus2_config[] = {
static struct omap_board_config_kernel perseus2_config[] __initdata = {
{ OMAP_TAG_UART, &perseus2_uart_config },
{ OMAP_TAG_LCD, &perseus2_lcd_config },
};
......@@ -233,6 +234,7 @@ static void __init omap_perseus2_init(void)
omap_board_config = perseus2_config;
omap_board_config_size = ARRAY_SIZE(perseus2_config);
omap_serial_init();
omap_register_i2c_bus(1, 100, NULL, 0);
}
static void __init perseus2_init_smc91x(void)
......
arch/arm/mach-omap1/board-sx1-mmc.c 0 → 100644
View file @ 0eccf60b
/*
* linux/arch/arm/mach-omap1/board-sx1-mmc.c
*
* Copyright (C) 2007 Instituto Nokia de Tecnologia - INdT
* Author: Carlos Eduardo Aguiar <carlos.aguiar@indt.org.br>
*
* This code is based on linux/arch/arm/mach-omap1/board-h2-mmc.c, which is:
* Copyright (C) 2007 Instituto Nokia de Tecnologia - INdT
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <asm/arch/hardware.h>
#include <asm/arch/mmc.h>
#include <asm/arch/gpio.h>
#ifdef CONFIG_MMC_OMAP
static int slot_cover_open;
static struct device *mmc_device;
static int sx1_mmc_set_power(struct device *dev, int slot, int power_on,
int vdd)
{
int err;
u8 dat = 0;
#ifdef CONFIG_MMC_DEBUG
dev_dbg(dev, "Set slot %d power: %s (vdd %d)\n", slot + 1,
power_on ? "on" : "off", vdd);
#endif
if (slot != 0) {
dev_err(dev, "No such slot %d\n", slot + 1);
return -ENODEV;
}
err = sx1_i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, &dat);
if (err < 0)
return err;
if (power_on)
dat |= SOFIA_MMC_POWER;
else
dat &= ~SOFIA_MMC_POWER;
return sx1_i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, dat);
}
static int sx1_mmc_set_bus_mode(struct device *dev, int slot, int bus_mode)
{
#ifdef CONFIG_MMC_DEBUG
dev_dbg(dev, "Set slot %d bus_mode %s\n", slot + 1,
bus_mode == MMC_BUSMODE_OPENDRAIN ? "open-drain" : "push-pull");
#endif
if (slot != 0) {
dev_err(dev, "No such slot %d\n", slot + 1);
return -ENODEV;
}
return 0;
}
static int sx1_mmc_get_cover_state(struct device *dev, int slot)
{
BUG_ON(slot != 0);
return slot_cover_open;
}
void sx1_mmc_slot_cover_handler(void *arg, int state)
{
if (mmc_device == NULL)
return;
slot_cover_open = state;
omap_mmc_notify_cover_event(mmc_device, 0, state);
}
static int sx1_mmc_late_init(struct device *dev)
{
int ret = 0;
mmc_device = dev;
return ret;
}
static void sx1_mmc_cleanup(struct device *dev)
{
}
static struct omap_mmc_platform_data sx1_mmc_data = {
.nr_slots = 1,
.switch_slot = NULL,
.init = sx1_mmc_late_init,
.cleanup = sx1_mmc_cleanup,
.slots[0] = {
.set_power = sx1_mmc_set_power,
.set_bus_mode = sx1_mmc_set_bus_mode,
.get_ro = NULL,
.get_cover_state = sx1_mmc_get_cover_state,
.ocr_mask = MMC_VDD_28_29 | MMC_VDD_30_31 |
MMC_VDD_32_33 | MMC_VDD_33_34,
.name = "mmcblk",
},
};
void __init sx1_mmc_init(void)
{
omap_set_mmc_info(1, &sx1_mmc_data);
}
#else
void __init sx1_mmc_init(void)
{
}
void sx1_mmc_slot_cover_handler(void *arg, int state)
{
}
#endif
arch/arm/mach-omap1/board-sx1.c
View file @ 0eccf60b
......@@ -44,7 +44,7 @@
#include <asm/arch/keypad.h>
/* Write to I2C device */
int i2c_write_byte(u8 devaddr, u8 regoffset, u8 value)
int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value)
{
struct i2c_adapter *adap;
int err;
......@@ -67,7 +67,7 @@ int i2c_write_byte(u8 devaddr, u8 regoffset, u8 value)
}
/* Read from I2C device */
int i2c_read_byte(u8 devaddr, u8 regoffset, u8 * value)
int sx1_i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value)
{
struct i2c_adapter *adap;
int err;
......@@ -101,66 +101,55 @@ int sx1_setkeylight(u8 keylight)
{
if (keylight > SOFIA_MAX_LIGHT_VAL)
keylight = SOFIA_MAX_LIGHT_VAL;
return i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_KEYLIGHT_REG, keylight);
return sx1_i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_KEYLIGHT_REG, keylight);
}
/* get current keylight intensity */
int sx1_getkeylight(u8 * keylight)
{
return i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_KEYLIGHT_REG, keylight);
return sx1_i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_KEYLIGHT_REG, keylight);
}
/* set LCD backlight intensity */
int sx1_setbacklight(u8 backlight)
{
if (backlight > SOFIA_MAX_LIGHT_VAL)
backlight = SOFIA_MAX_LIGHT_VAL;
return i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_BACKLIGHT_REG, backlight);
return sx1_i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_BACKLIGHT_REG,
backlight);
}
/* get current LCD backlight intensity */
int sx1_getbacklight (u8 * backlight)
{
return i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_BACKLIGHT_REG, backlight);
return sx1_i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_BACKLIGHT_REG,
backlight);
}
/* set LCD backlight power on/off */
int sx1_setmmipower(u8 onoff)
{
int err;
u8 dat = 0;
err = i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, &dat);
err = sx1_i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, &dat);
if (err < 0)
return err;
if (onoff)
dat |= SOFIA_MMILIGHT_POWER;
else
dat &= ~SOFIA_MMILIGHT_POWER;
return i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, dat);
}
/* set MMC power on/off */
int sx1_setmmcpower(u8 onoff)
{
int err;
u8 dat = 0;
err = i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, &dat);
if (err < 0)
return err;
if (onoff)
dat |= SOFIA_MMC_POWER;
else
dat &= ~SOFIA_MMC_POWER;
return i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, dat);
return sx1_i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, dat);
}
/* set USB power on/off */
int sx1_setusbpower(u8 onoff)
{
int err;
u8 dat = 0;
err = i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, &dat);
err = sx1_i2c_read_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, &dat);
if (err < 0)
return err;
if (onoff)
dat |= SOFIA_USB_POWER;
else
dat &= ~SOFIA_USB_POWER;
return i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, dat);
return sx1_i2c_write_byte(SOFIA_I2C_ADDR, SOFIA_POWER1_REG, dat);
}
EXPORT_SYMBOL(sx1_setkeylight);
......@@ -168,7 +157,6 @@ EXPORT_SYMBOL(sx1_getkeylight);
EXPORT_SYMBOL(sx1_setbacklight);
EXPORT_SYMBOL(sx1_getbacklight);
EXPORT_SYMBOL(sx1_setmmipower);
EXPORT_SYMBOL(sx1_setmmcpower);
EXPORT_SYMBOL(sx1_setusbpower);
/*----------- Keypad -------------------------*/
......@@ -280,21 +268,6 @@ static struct omap_mcbsp_reg_cfg mcbsp1_regs = {
/* PCR0 =0f0f */
};
/* TODO: PCM interface - McBSP2 */
static struct omap_mcbsp_reg_cfg mcbsp2_regs = {
.spcr2 = FRST | GRST | XRST | XINTM(3), /* SPCR2=F1 */
.spcr1 = RINTM(3) | RRST, /* SPCR1=30 */
.rcr2 = 0, /* RCR2 =00 */
.rcr1 = RFRLEN1(1) | RWDLEN1(OMAP_MCBSP_WORD_16), /* RCR1 = 140 */
.xcr2 = 0, /* XCR2 = 0 */
.xcr1 = XFRLEN1(1) | XWDLEN1(OMAP_MCBSP_WORD_16), /* XCR1 = 140 */
.srgr1 = FWID(15) | CLKGDV(12), /* SRGR1=0f0c */
.srgr2 = FSGM | FPER(31), /* SRGR2=101f */
.pcr0 = FSXM | FSRM | CLKXM | CLKRM | FSXP | FSRP | CLKXP | CLKRP,
/* PCR0=0f0f */
/* mcbsp: slave */
};
static struct omap_alsa_codec_config sx1_alsa_config = {
.name = "SX1 EGold",
.mcbsp_regs_alsa = &mcbsp1_regs,
......@@ -407,11 +380,8 @@ static struct omap_usb_config sx1_usb_config __initdata = {
static struct omap_mmc_config sx1_mmc_config __initdata = {
.mmc [0] = {
.enabled = 1,
.enabled = 1,
.wire4 = 0,
.wp_pin = -1,
.power_pin = -1, /* power is in Sofia */
.switch_pin = OMAP_MPUIO(3),
},
};
......@@ -440,13 +410,15 @@ static struct omap_uart_config sx1_uart_config __initdata = {
.enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
};
static struct omap_board_config_kernel sx1_config[] = {
static struct omap_board_config_kernel sx1_config[] __initdata = {
{ OMAP_TAG_USB, &sx1_usb_config },
{ OMAP_TAG_MMC, &sx1_mmc_config },
{ OMAP_TAG_LCD, &sx1_lcd_config },
{ OMAP_TAG_UART, &sx1_uart_config },
};
/*-----------------------------------------*/
static void __init omap_sx1_init(void)
{
platform_add_devices(sx1_devices, ARRAY_SIZE(sx1_devices));
......@@ -454,6 +426,8 @@ static void __init omap_sx1_init(void)
omap_board_config = sx1_config;
omap_board_config_size = ARRAY_SIZE(sx1_config);
omap_serial_init();
omap_register_i2c_bus(1, 100, NULL, 0);
sx1_mmc_init();
/* turn on USB power */
/* sx1_setusbpower(1); cant do it here because i2c is not ready */
......
arch/arm/mach-omap1/board-voiceblue.c
View file @ 0eccf60b
......@@ -34,9 +34,6 @@
#include <asm/arch/tc.h>
#include <asm/arch/usb.h>
extern void omap_init_time(void);
extern int omap_gpio_init(void);
static struct plat_serial8250_port voiceblue_ports[] = {
{
.mapbase = (unsigned long)(OMAP_CS1_PHYS + 0x40000),
......@@ -198,6 +195,7 @@ static void __init voiceblue_init(void)
omap_board_config = voiceblue_config;
omap_board_config_size = ARRAY_SIZE(voiceblue_config);
omap_serial_init();
omap_register_i2c_bus(1, 100, NULL, 0);
/* There is a good chance board is going up, so enable power LED
* (it is connected through invertor) */
......
arch/arm/mach-omap1/clock.c
View file @ 0eccf60b
//kernel/linux-omap-fsample/arch/arm/mach-omap1/clock.c#2 - edit change 3808 (text)
/*
* linux/arch/arm/mach-omap1/clock.c
*
......@@ -650,9 +649,9 @@ static void __init omap1_clk_disable_unused(struct clk *clk)
/* FIXME: This clock seems to be necessary but no-one
* has asked for its activation. */
if (clk == &tc2_ck // FIX: pm.c (SRAM), CCP, Camera
|| clk == &ck_dpll1out.clk // FIX: SoSSI, SSR
|| clk == &arm_gpio_ck // FIX: GPIO code for 1510
if (clk == &tc2_ck /* FIX: pm.c (SRAM), CCP, Camera */
|| clk == &ck_dpll1out.clk /* FIX: SoSSI, SSR */
|| clk == &arm_gpio_ck /* FIX: GPIO code for 1510 */
) {
printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
clk->name);
......
arch/arm/mach-omap1/leds-osk.c
View file @ 0eccf60b
......@@ -82,7 +82,7 @@ static void mistral_setled(void)
red = 1;
else if (hw_led_state & IDLE_LED)
green = 1;
// else both sides are disabled
/* else both sides are disabled */
omap_set_gpio_dataout(GPIO_LED_GREEN, green);
omap_set_gpio_dataout(GPIO_LED_RED, red);
......@@ -112,7 +112,7 @@ void osk_leds_event(led_event_t evt)
case led_stop:
led_state &= ~LED_STATE_ENABLED;
hw_led_state = 0;
// NOTE: work may still be pending!!
/* NOTE: work may still be pending!! */
break;
case led_claim:
......
arch/arm/mach-omap1/mailbox.c
View file @ 0eccf60b
......@@ -51,7 +51,7 @@ static inline void mbox_write_reg(unsigned int val, unsigned int reg)
}
/* msg */
static inline mbox_msg_t omap1_mbox_fifo_read(struct omap_mbox *mbox)
static mbox_msg_t omap1_mbox_fifo_read(struct omap_mbox *mbox)
{
struct omap_mbox1_fifo *fifo =
&((struct omap_mbox1_priv *)mbox->priv)->rx_fifo;
......@@ -63,7 +63,7 @@ static inline mbox_msg_t omap1_mbox_fifo_read(struct omap_mbox *mbox)
return msg;
}
static inline void
static void
omap1_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
{
struct omap_mbox1_fifo *fifo =
......@@ -73,12 +73,12 @@ omap1_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
mbox_write_reg(msg >> 16, fifo->cmd);
}
static inline int omap1_mbox_fifo_empty(struct omap_mbox *mbox)
static int omap1_mbox_fifo_empty(struct omap_mbox *mbox)
{
return 0;
}
static inline int omap1_mbox_fifo_full(struct omap_mbox *mbox)
static int omap1_mbox_fifo_full(struct omap_mbox *mbox)
{
struct omap_mbox1_fifo *fifo =
&((struct omap_mbox1_priv *)mbox->priv)->rx_fifo;
......@@ -87,21 +87,21 @@ static inline int omap1_mbox_fifo_full(struct omap_mbox *mbox)
}
/* irq */
static inline void
static void
omap1_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
{
if (irq == IRQ_RX)
enable_irq(mbox->irq);
}
static inline void
static void
omap1_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
{
if (irq == IRQ_RX)
disable_irq(mbox->irq);
}
static inline int
static int
omap1_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
{
if (irq == IRQ_TX)
......
arch/arm/mach-omap1/pm.c
View file @ 0eccf60b
......@@ -57,7 +57,6 @@
#include <asm/arch/pm.h>
#include <asm/arch/mux.h>
#include <asm/arch/dma.h>
#include <asm/arch/dsp_common.h>
#include <asm/arch/dmtimer.h>
static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
......@@ -67,6 +66,8 @@ static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE];
static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
#ifdef CONFIG_OMAP_32K_TIMER
static unsigned short enable_dyn_sleep = 1;
static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
......@@ -91,7 +92,8 @@ static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
static struct kobj_attribute sleep_while_idle_attr =
__ATTR(sleep_while_idle, 0644, idle_show, idle_store);
static void (*omap_sram_idle)(void) = NULL;
#endif
static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
/*
......@@ -104,9 +106,7 @@ void omap_pm_idle(void)
{
extern __u32 arm_idlect1_mask;
__u32 use_idlect1 = arm_idlect1_mask;
#ifndef CONFIG_OMAP_MPU_TIMER
int do_sleep;
#endif
int do_sleep = 0;
local_irq_disable();
local_fiq_disable();
......@@ -128,7 +128,6 @@ void omap_pm_idle(void)
use_idlect1 = use_idlect1 & ~(1 << 9);
#else
do_sleep = 0;
while (enable_dyn_sleep) {
#ifdef CONFIG_CBUS_TAHVO_USB
......@@ -141,6 +140,8 @@ void omap_pm_idle(void)
break;
}
#endif
#ifdef CONFIG_OMAP_DM_TIMER
use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
#endif
......@@ -168,7 +169,6 @@ void omap_pm_idle(void)
}
omap_sram_suspend(omap_readl(ARM_IDLECT1),
omap_readl(ARM_IDLECT2));
#endif
local_fiq_enable();
local_irq_enable();
......@@ -661,7 +661,10 @@ static struct platform_suspend_ops omap_pm_ops ={
static int __init omap_pm_init(void)
{
#ifdef CONFIG_OMAP_32K_TIMER
int error;
#endif
printk("Power Management for TI OMAP.\n");
......@@ -671,23 +674,17 @@ static int __init omap_pm_init(void)
* memory the MPU can see when it wakes up.
*/
if (cpu_is_omap730()) {
omap_sram_idle = omap_sram_push(omap730_idle_loop_suspend,
omap730_idle_loop_suspend_sz);
omap_sram_suspend = omap_sram_push(omap730_cpu_suspend,
omap730_cpu_suspend_sz);
} else if (cpu_is_omap15xx()) {
omap_sram_idle = omap_sram_push(omap1510_idle_loop_suspend,
omap1510_idle_loop_suspend_sz);
omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
omap1510_cpu_suspend_sz);
} else if (cpu_is_omap16xx()) {
omap_sram_idle = omap_sram_push(omap1610_idle_loop_suspend,
omap1610_idle_loop_suspend_sz);
omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
omap1610_cpu_suspend_sz);
}
if (omap_sram_idle == NULL || omap_sram_suspend == NULL) {
if (omap_sram_suspend == NULL) {
printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
return -ENODEV;
}
......@@ -719,9 +716,11 @@ static int __init omap_pm_init(void)
omap_pm_init_proc();
#endif
#ifdef CONFIG_OMAP_32K_TIMER
error = sysfs_create_file(power_kobj, &sleep_while_idle_attr);
if (error)
printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
#endif
if (cpu_is_omap16xx()) {
/* configure LOW_PWR pin */
......
arch/arm/mach-omap1/sleep.S
View file @ 0eccf60b
......@@ -39,167 +39,6 @@
.text
/*
* Forces OMAP into idle state
*
* omapXXXX_idle_loop_suspend()
*
* Note: This code get's copied to internal SRAM at boot. When the OMAP
* wakes up it continues execution at the point it went to sleep.
*
* Note: Because of slightly different configuration values we have
* processor specific functions here.
*/
#if defined(CONFIG_ARCH_OMAP730)
ENTRY(omap730_idle_loop_suspend)
stmfd sp!, {r0 - r12, lr} @ save registers on stack
@ load base address of ARM_IDLECT1 and ARM_IDLECT2
mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000
orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
@ turn off clock domains
@ get ARM_IDLECT2 into r2
ldrh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
mov r5, #OMAP730_IDLECT2_SLEEP_VAL & 0xff
orr r5, r5, #OMAP730_IDLECT2_SLEEP_VAL & 0xff00
strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
@ request ARM idle
@ get ARM_IDLECT1 into r1
ldrh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
orr r3, r1, #OMAP730_IDLE_LOOP_REQUEST & 0xffff
strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
mov r5, #IDLE_WAIT_CYCLES & 0xff
orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00
l_730: subs r5, r5, #1
bne l_730
/*
* Let's wait for the next clock tick to wake us up.
*/
mov r0, #0
mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
/*
* omap730_idle_loop_suspend()'s resume point.
*
* It will just start executing here, so we'll restore stuff from the
* stack, reset the ARM_IDLECT1 and ARM_IDLECT2.
*/
@ restore ARM_IDLECT1 and ARM_IDLECT2 and return
@ r1 has ARM_IDLECT1 and r2 still has ARM_IDLECT2
strh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
strh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
ldmfd sp!, {r0 - r12, pc} @ restore regs and return
ENTRY(omap730_idle_loop_suspend_sz)
.word . - omap730_idle_loop_suspend
#endif /* CONFIG_ARCH_OMAP730 */
#ifdef CONFIG_ARCH_OMAP15XX
ENTRY(omap1510_idle_loop_suspend)
stmfd sp!, {r0 - r12, lr} @ save registers on stack
@ load base address of ARM_IDLECT1 and ARM_IDLECT2
mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000
orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
@ turn off clock domains
@ get ARM_IDLECT2 into r2
ldrh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
mov r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff
orr r5, r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff00
strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
@ request ARM idle
@ get ARM_IDLECT1 into r1
ldrh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
orr r3, r1, #OMAP1510_IDLE_LOOP_REQUEST & 0xffff
strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
mov r5, #IDLE_WAIT_CYCLES & 0xff
orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00
l_1510: subs r5, r5, #1
bne l_1510
/*
* Let's wait for the next clock tick to wake us up.
*/
mov r0, #0
mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
/*
* omap1510_idle_loop_suspend()'s resume point.
*
* It will just start executing here, so we'll restore stuff from the
* stack, reset the ARM_IDLECT1 and ARM_IDLECT2.
*/
@ restore ARM_IDLECT1 and ARM_IDLECT2 and return
@ r1 has ARM_IDLECT1 and r2 still has ARM_IDLECT2
strh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
strh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
ldmfd sp!, {r0 - r12, pc} @ restore regs and return
ENTRY(omap1510_idle_loop_suspend_sz)
.word . - omap1510_idle_loop_suspend
#endif /* CONFIG_ARCH_OMAP15XX */
#if defined(CONFIG_ARCH_OMAP16XX)
ENTRY(omap1610_idle_loop_suspend)
stmfd sp!, {r0 - r12, lr} @ save registers on stack
@ load base address of ARM_IDLECT1 and ARM_IDLECT2
mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000
orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
@ turn off clock domains
@ get ARM_IDLECT2 into r2
ldrh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
mov r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff
orr r5, r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff00
strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
@ request ARM idle
@ get ARM_IDLECT1 into r1
ldrh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
orr r3, r1, #OMAP1610_IDLE_LOOP_REQUEST & 0xffff
strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
mov r5, #IDLE_WAIT_CYCLES & 0xff
orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00
l_1610: subs r5, r5, #1
bne l_1610
/*
* Let's wait for the next clock tick to wake us up.
*/
mov r0, #0
mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
/*
* omap1610_idle_loop_suspend()'s resume point.
*
* It will just start executing here, so we'll restore stuff from the
* stack, reset the ARM_IDLECT1 and ARM_IDLECT2.
*/
@ restore ARM_IDLECT1 and ARM_IDLECT2 and return
@ r1 has ARM_IDLECT1 and r2 still has ARM_IDLECT2
strh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
strh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
ldmfd sp!, {r0 - r12, pc} @ restore regs and return
ENTRY(omap1610_idle_loop_suspend_sz)
.word . - omap1610_idle_loop_suspend
#endif /* CONFIG_ARCH_OMAP16XX */
/*
* Forces OMAP into deep sleep state
......
arch/arm/mach-orion/addr-map.c
View file @ 0eccf60b
......@@ -265,15 +265,15 @@ void __init orion_setup_cpu_wins(void)
}
/*
* Setup windows for PCI+PCIE IO+MAM space
* Setup windows for PCI+PCIe IO+MEM space.
*/
orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_BASE,
ORION_PCIE_IO_SIZE, ORION_PCIE_IO_REMAP);
orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_BASE,
ORION_PCI_IO_SIZE, ORION_PCI_IO_REMAP);
orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_BASE,
orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_PHYS_BASE,
ORION_PCIE_IO_SIZE, ORION_PCIE_IO_BUS_BASE);
orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_PHYS_BASE,
ORION_PCI_IO_SIZE, ORION_PCI_IO_BUS_BASE);
orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_PHYS_BASE,
ORION_PCIE_MEM_SIZE, -1);
orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_BASE,
orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_PHYS_BASE,
ORION_PCI_MEM_SIZE, -1);
}
......
arch/arm/mach-orion/common.c
View file @ 0eccf60b
......@@ -19,7 +19,7 @@
#include <asm/page.h>
#include <asm/timex.h>
#include <asm/mach/map.h>
#include <asm/arch/orion.h>
#include <asm/arch/hardware.h>
#include "common.h"
/*****************************************************************************
......@@ -27,26 +27,26 @@
****************************************************************************/
static struct map_desc orion_io_desc[] __initdata = {
{
.virtual = ORION_REGS_BASE,
.pfn = __phys_to_pfn(ORION_REGS_BASE),
.virtual = ORION_REGS_VIRT_BASE,
.pfn = __phys_to_pfn(ORION_REGS_PHYS_BASE),
.length = ORION_REGS_SIZE,
.type = MT_DEVICE
},
{
.virtual = ORION_PCIE_IO_BASE,
.pfn = __phys_to_pfn(ORION_PCIE_IO_BASE),
.virtual = ORION_PCIE_IO_VIRT_BASE,
.pfn = __phys_to_pfn(ORION_PCIE_IO_PHYS_BASE),
.length = ORION_PCIE_IO_SIZE,
.type = MT_DEVICE
},
{
.virtual = ORION_PCI_IO_BASE,
.pfn = __phys_to_pfn(ORION_PCI_IO_BASE),
.virtual = ORION_PCI_IO_VIRT_BASE,
.pfn = __phys_to_pfn(ORION_PCI_IO_PHYS_BASE),
.length = ORION_PCI_IO_SIZE,
.type = MT_DEVICE
},
{
.virtual = ORION_PCIE_WA_BASE,
.pfn = __phys_to_pfn(ORION_PCIE_WA_BASE),
.virtual = ORION_PCIE_WA_VIRT_BASE,
.pfn = __phys_to_pfn(ORION_PCIE_WA_PHYS_BASE),
.length = ORION_PCIE_WA_SIZE,
.type = MT_DEVICE
},
......@@ -63,8 +63,8 @@ void __init orion_map_io(void)
static struct resource orion_uart_resources[] = {
{
.start = UART0_BASE,
.end = UART0_BASE + 0xff,
.start = UART0_PHYS_BASE,
.end = UART0_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
{
......@@ -73,8 +73,8 @@ static struct resource orion_uart_resources[] = {
.flags = IORESOURCE_IRQ,
},
{
.start = UART1_BASE,
.end = UART1_BASE + 0xff,
.start = UART1_PHYS_BASE,
.end = UART1_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
{
......@@ -86,8 +86,8 @@ static struct resource orion_uart_resources[] = {
static struct plat_serial8250_port orion_uart_data[] = {
{
.mapbase = UART0_BASE,
.membase = (char *)UART0_BASE,
.mapbase = UART0_PHYS_BASE,
.membase = (char *)UART0_VIRT_BASE,
.irq = IRQ_ORION_UART0,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
......@@ -95,8 +95,8 @@ static struct plat_serial8250_port orion_uart_data[] = {
.uartclk = ORION_TCLK,
},
{
.mapbase = UART1_BASE,
.membase = (char *)UART1_BASE,
.mapbase = UART1_PHYS_BASE,
.membase = (char *)UART1_VIRT_BASE,
.irq = IRQ_ORION_UART1,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
......@@ -122,8 +122,8 @@ static struct platform_device orion_uart = {
static struct resource orion_ehci0_resources[] = {
{
.start = ORION_USB0_REG_BASE,
.end = ORION_USB0_REG_BASE + SZ_4K,
.start = ORION_USB0_PHYS_BASE,
.end = ORION_USB0_PHYS_BASE + SZ_4K,
.flags = IORESOURCE_MEM,
},
{
......@@ -135,8 +135,8 @@ static struct resource orion_ehci0_resources[] = {
static struct resource orion_ehci1_resources[] = {
{
.start = ORION_USB1_REG_BASE,
.end = ORION_USB1_REG_BASE + SZ_4K,
.start = ORION_USB1_PHYS_BASE,
.end = ORION_USB1_PHYS_BASE + SZ_4K,
.flags = IORESOURCE_MEM,
},
{
......@@ -177,8 +177,8 @@ static struct platform_device orion_ehci1 = {
static struct resource orion_eth_shared_resources[] = {
{
.start = ORION_ETH_REG_BASE,
.end = ORION_ETH_REG_BASE + 0xffff,
.start = ORION_ETH_PHYS_BASE,
.end = ORION_ETH_PHYS_BASE + 0xffff,
.flags = IORESOURCE_MEM,
},
};
......@@ -227,8 +227,8 @@ static struct mv64xxx_i2c_pdata orion_i2c_pdata = {
static struct resource orion_i2c_resources[] = {
{
.name = "i2c base",
.start = I2C_BASE,
.end = I2C_BASE + 0x20 -1,
.start = I2C_PHYS_BASE,
.end = I2C_PHYS_BASE + 0x20 -1,
.flags = IORESOURCE_MEM,
},
{
......@@ -249,6 +249,40 @@ static struct platform_device orion_i2c = {
},
};
/*****************************************************************************
* Sata port
****************************************************************************/
static struct resource orion_sata_resources[] = {
{
.name = "sata base",
.start = ORION_SATA_PHYS_BASE,
.end = ORION_SATA_PHYS_BASE + 0x5000 - 1,
.flags = IORESOURCE_MEM,
},
{
.name = "sata irq",
.start = IRQ_ORION_SATA,
.end = IRQ_ORION_SATA,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device orion_sata = {
.name = "sata_mv",
.id = 0,
.dev = {
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(orion_sata_resources),
.resource = orion_sata_resources,
};
void __init orion_sata_init(struct mv_sata_platform_data *sata_data)
{
orion_sata.dev.platform_data = sata_data;
platform_device_register(&orion_sata);
}
/*****************************************************************************
* General
****************************************************************************/
......
arch/arm/mach-orion/common.h
View file @ 0eccf60b
......@@ -75,4 +75,12 @@ struct mv643xx_eth_platform_data;
void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data);
/*
* Orion Sata platform_data, used by machine-setup
*/
struct mv_sata_platform_data;
void __init orion_sata_init(struct mv_sata_platform_data *sata_data);
#endif /* __ARCH_ORION_COMMON_H__ */
arch/arm/mach-orion/db88f5281-setup.c
View file @ 0eccf60b
......@@ -354,8 +354,8 @@ static void __init db88f5281_init(void)
MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
/* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */
.phys_io = ORION_REGS_BASE,
.io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xfffc,
.phys_io = ORION_REGS_PHYS_BASE,
.io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xfffc,
.boot_params = 0x00000100,
.init_machine = db88f5281_init,
.map_io = orion_map_io,
......
arch/arm/mach-orion/dns323-setup.c
View file @ 0eccf60b
......@@ -259,8 +259,8 @@ static void __init dns323_init(void)
*
* Open a special address decode windows for the PCIE WA.
*/
orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE);
orion_write(ORION_REGS_BASE | 0x20070,
orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
orion_write(ORION_REGS_VIRT_BASE | 0x20070,
(0x7941 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
/* set MPP to 0 as D-Link's 2.6.12.6 kernel did */
......@@ -312,8 +312,8 @@ static void __init dns323_init(void)
/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */
MACHINE_START(DNS323, "D-Link DNS-323")
/* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */
.phys_io = ORION_REGS_BASE,
.io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC,
.phys_io = ORION_REGS_PHYS_BASE,
.io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
.boot_params = 0x00000100,
.init_machine = dns323_init,
.map_io = orion_map_io,
......
arch/arm/mach-orion/kurobox_pro-setup.c
View file @ 0eccf60b
......@@ -17,6 +17,7 @@
#include <linux/mtd/nand.h>
#include <linux/mv643xx_eth.h>
#include <linux/i2c.h>
#include <linux/ata_platform.h>
#include <asm/mach-types.h>
#include <asm/gpio.h>
#include <asm/mach/arch.h>
......@@ -166,6 +167,13 @@ static struct i2c_board_info __initdata kurobox_pro_i2c_rtc = {
.addr = 0x32,
};
/*****************************************************************************
* SATA
****************************************************************************/
static struct mv_sata_platform_data kurobox_pro_sata_data = {
.n_ports = 2,
};
/*****************************************************************************
* General Setup
****************************************************************************/
......@@ -192,8 +200,8 @@ static void __init kurobox_pro_init(void)
/*
* Open a special address decode windows for the PCIE WA.
*/
orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE);
orion_write(ORION_REGS_BASE | 0x20070, (0x7941 |
orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
(((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
/*
......@@ -220,12 +228,13 @@ static void __init kurobox_pro_init(void)
platform_add_devices(kurobox_pro_devices, ARRAY_SIZE(kurobox_pro_devices));
i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1);
orion_eth_init(&kurobox_pro_eth_data);
orion_sata_init(&kurobox_pro_sata_data);
}
MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro")
/* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
.phys_io = ORION_REGS_BASE,
.io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC,
.phys_io = ORION_REGS_PHYS_BASE,
.io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
.boot_params = 0x00000100,
.init_machine = kurobox_pro_init,
.map_io = orion_map_io,
......
arch/arm/mach-orion/pci.c
View file @ 0eccf60b
......@@ -156,7 +156,7 @@ static int orion_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
orion_pcie_id(&dev, &rev);
if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
/* extended register space */
pcie_addr = ORION_PCIE_WA_BASE;
pcie_addr = ORION_PCIE_WA_VIRT_BASE;
pcie_addr |= PCIE_CONF_BUS(bus->number) |
PCIE_CONF_DEV(PCI_SLOT(devfn)) |
PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
......@@ -241,7 +241,7 @@ static int orion_pcie_setup(struct pci_sys_data *sys)
*/
res[0].name = "PCI-EX I/O Space";
res[0].flags = IORESOURCE_IO;
res[0].start = ORION_PCIE_IO_REMAP;
res[0].start = ORION_PCIE_IO_BUS_BASE;
res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1;
if (request_resource(&ioport_resource, &res[0]))
panic("Request PCIE IO resource failed\n");
......@@ -252,7 +252,7 @@ static int orion_pcie_setup(struct pci_sys_data *sys)
*/
res[1].name = "PCI-EX Memory Space";
res[1].flags = IORESOURCE_MEM;
res[1].start = ORION_PCIE_MEM_BASE;
res[1].start = ORION_PCIE_MEM_PHYS_BASE;
res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1;
if (request_resource(&iomem_resource, &res[1]))
panic("Request PCIE Memory resource failed\n");
......@@ -477,7 +477,7 @@ static int orion_pci_setup(struct pci_sys_data *sys)
*/
res[0].name = "PCI I/O Space";
res[0].flags = IORESOURCE_IO;
res[0].start = ORION_PCI_IO_REMAP;
res[0].start = ORION_PCI_IO_BUS_BASE;
res[0].end = res[0].start + ORION_PCI_IO_SIZE - 1;
if (request_resource(&ioport_resource, &res[0]))
panic("Request PCI IO resource failed\n");
......@@ -488,7 +488,7 @@ static int orion_pci_setup(struct pci_sys_data *sys)
*/
res[1].name = "PCI Memory Space";
res[1].flags = IORESOURCE_MEM;
res[1].start = ORION_PCI_MEM_BASE;
res[1].start = ORION_PCI_MEM_PHYS_BASE;
res[1].end = res[1].start + ORION_PCI_MEM_SIZE - 1;
if (request_resource(&iomem_resource, &res[1]))
panic("Request PCI Memory resource failed\n");
......
arch/arm/mach-orion/rd88f5182-setup.c
View file @ 0eccf60b
......@@ -17,6 +17,7 @@
#include <linux/irq.h>
#include <linux/mtd/physmap.h>
#include <linux/mv643xx_eth.h>
#include <linux/ata_platform.h>
#include <linux/i2c.h>
#include <asm/mach-types.h>
#include <asm/gpio.h>
......@@ -229,6 +230,13 @@ static struct i2c_board_info __initdata rd88f5182_i2c_rtc = {
.addr = 0x68,
};
/*****************************************************************************
* Sata
****************************************************************************/
static struct mv_sata_platform_data rd88f5182_sata_data = {
.n_ports = 2,
};
/*****************************************************************************
* General Setup
****************************************************************************/
......@@ -255,8 +263,8 @@ static void __init rd88f5182_init(void)
/*
* Open a special address decode windows for the PCIE WA.
*/
orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE);
orion_write(ORION_REGS_BASE | 0x20070, (0x7941 |
orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
(((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
/*
......@@ -292,12 +300,13 @@ static void __init rd88f5182_init(void)
platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices));
i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1);
orion_eth_init(&rd88f5182_eth_data);
orion_sata_init(&rd88f5182_sata_data);
}
MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
/* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
.phys_io = ORION_REGS_BASE,
.io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC,
.phys_io = ORION_REGS_PHYS_BASE,
.io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
.boot_params = 0x00000100,
.init_machine = rd88f5182_init,
.map_io = orion_map_io,
......
arch/arm/mach-orion/ts209-setup.c
View file @ 0eccf60b
......@@ -21,6 +21,7 @@
#include <linux/input.h>
#include <linux/i2c.h>
#include <linux/serial_reg.h>
#include <linux/ata_platform.h>
#include <asm/mach-types.h>
#include <asm/gpio.h>
#include <asm/mach/arch.h>
......@@ -232,6 +233,14 @@ static struct platform_device qnap_ts209_button_device = {
};
/*****************************************************************************
* SATA
****************************************************************************/
static struct mv_sata_platform_data qnap_ts209_sata_data = {
.n_ports = 2,
};
/*****************************************************************************
* General Setup
****************************************************************************/
......@@ -244,7 +253,7 @@ static struct platform_device *qnap_ts209_devices[] __initdata = {
* QNAP TS-[12]09 specific power off method via UART1-attached PIC
*/
#define UART1_REG(x) (UART1_BASE + ((UART_##x) << 2))
#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2))
static void qnap_ts209_power_off(void)
{
......@@ -282,8 +291,8 @@ static void __init qnap_ts209_init(void)
/*
* Open a special address decode windows for the PCIE WA.
*/
orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE);
orion_write(ORION_REGS_BASE | 0x20070, (0x7941 |
orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
(((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
/*
......@@ -321,12 +330,13 @@ static void __init qnap_ts209_init(void)
ARRAY_SIZE(qnap_ts209_devices));
i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1);
orion_eth_init(&qnap_ts209_eth_data);
orion_sata_init(&qnap_ts209_sata_data);
}
MACHINE_START(TS209, "QNAP TS-109/TS-209")
/* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */
.phys_io = ORION_REGS_BASE,
.io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC,
.phys_io = ORION_REGS_PHYS_BASE,
.io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
.boot_params = 0x00000100,
.init_machine = qnap_ts209_init,
.map_io = orion_map_io,
......
arch/arm/mach-pxa/pxa3xx.c
View file @ 0eccf60b
......@@ -266,8 +266,6 @@ static void pxa3xx_cpu_standby(unsigned int pwrmode)
AD2D0ER = 0;
AD2D1ER = 0;
printk("PM: AD2D0SR=%08x ASCR=%08x\n", AD2D0SR, ASCR);
}
/*
......@@ -515,6 +513,14 @@ static int __init pxa3xx_init(void)
int i, ret = 0;
if (cpu_is_pxa3xx()) {
/*
* clear RDH bit every time after reset
*
* Note: the last 3 bits DxS are write-1-to-clear so carefully
* preserve them here in case they will be referenced later
*/
ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks));
if ((ret = pxa_init_dma(32)))
......
arch/arm/plat-omap/Makefile
View file @ 0eccf60b
......@@ -19,3 +19,4 @@ obj-$(CONFIG_CPU_FREQ) += cpu-omap.o
obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o
obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
obj-$(CONFIG_I2C_OMAP) += i2c.o
arch/arm/plat-omap/dma.c
View file @ 0eccf60b
......@@ -6,7 +6,7 @@
* DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
* Graphics DMA and LCD DMA graphics tranformations
* by Imre Deak <imre.deak@nokia.com>
* OMAP2 support Copyright (C) 2004-2005 Texas Instruments, Inc.
* OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
* Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
* Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
*
......@@ -33,12 +33,14 @@
#include <asm/arch/tc.h>
#define DEBUG_PRINTS
#undef DEBUG_PRINTS
#ifdef DEBUG_PRINTS
#define debug_printk(x) printk x
#else
#define debug_printk(x)
#undef DEBUG
#ifndef CONFIG_ARCH_OMAP1
enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
};
enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
#endif
#define OMAP_DMA_ACTIVE 0x01
......@@ -57,9 +59,66 @@ struct omap_dma_lch {
const char *dev_name;
void (* callback)(int lch, u16 ch_status, void *data);
void *data;
#ifndef CONFIG_ARCH_OMAP1
/* required for Dynamic chaining */
int prev_linked_ch;
int next_linked_ch;
int state;
int chain_id;
int status;
#endif
long flags;
};
#ifndef CONFIG_ARCH_OMAP1
struct dma_link_info {
int *linked_dmach_q;
int no_of_lchs_linked;
int q_count;
int q_tail;
int q_head;
int chain_state;
int chain_mode;
};
static struct dma_link_info dma_linked_lch[OMAP_LOGICAL_DMA_CH_COUNT];
/* Chain handling macros */
#define OMAP_DMA_CHAIN_QINIT(chain_id) \
do { \
dma_linked_lch[chain_id].q_head = \
dma_linked_lch[chain_id].q_tail = \
dma_linked_lch[chain_id].q_count = 0; \
} while (0)
#define OMAP_DMA_CHAIN_QFULL(chain_id) \
(dma_linked_lch[chain_id].no_of_lchs_linked == \
dma_linked_lch[chain_id].q_count)
#define OMAP_DMA_CHAIN_QLAST(chain_id) \
do { \
((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
dma_linked_lch[chain_id].q_count) \
} while (0)
#define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
(0 == dma_linked_lch[chain_id].q_count)
#define __OMAP_DMA_CHAIN_INCQ(end) \
((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
#define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
do { \
__OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
dma_linked_lch[chain_id].q_count--; \
} while (0)
#define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
do { \
__OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
dma_linked_lch[chain_id].q_count++; \
} while (0)
#endif
static int dma_chan_count;
static spinlock_t dma_chan_lock;
......@@ -73,6 +132,10 @@ static const u8 omap1_dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = {
INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
};
static inline void disable_lnk(int lch);
static void omap_disable_channel_irq(int lch);
static inline void omap_enable_channel_irq(int lch);
#define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
__FUNCTION__);
......@@ -148,7 +211,7 @@ void omap_set_dma_priority(int lch, int dst_port, int priority)
omap_writel(l, reg);
}
if (cpu_is_omap24xx()) {
if (cpu_class_is_omap2()) {
if (priority)
OMAP_DMA_CCR_REG(lch) |= (1 << 6);
else
......@@ -173,7 +236,7 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
OMAP1_DMA_CCR2_REG(lch) |= 1 << 2;
}
if (cpu_is_omap24xx() && dma_trigger) {
if (cpu_class_is_omap2() && dma_trigger) {
u32 val = OMAP_DMA_CCR_REG(lch);
val &= ~(3 << 19);
......@@ -213,7 +276,7 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
BUG_ON(omap_dma_in_1510_mode());
if (cpu_is_omap24xx()) {
if (cpu_class_is_omap2()) {
REVISIT_24XX();
return;
}
......@@ -245,7 +308,7 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
{
if (cpu_is_omap24xx()) {
if (cpu_class_is_omap2()) {
OMAP_DMA_CSDP_REG(lch) &= ~(0x3 << 16);
OMAP_DMA_CSDP_REG(lch) |= (mode << 16);
}
......@@ -269,7 +332,7 @@ void omap_set_dma_src_params(int lch, int src_port, int src_amode,
OMAP1_DMA_CSSA_L_REG(lch) = src_start;
}
if (cpu_is_omap24xx())
if (cpu_class_is_omap2())
OMAP2_DMA_CSSA_REG(lch) = src_start;
OMAP_DMA_CSEI_REG(lch) = src_ei;
......@@ -289,11 +352,14 @@ void omap_set_dma_params(int lch, struct omap_dma_channel_params * params)
omap_set_dma_dest_params(lch, params->dst_port,
params->dst_amode, params->dst_start,
params->dst_ei, params->dst_fi);
if (params->read_prio || params->write_prio)
omap_dma_set_prio_lch(lch, params->read_prio,
params->write_prio);
}
void omap_set_dma_src_index(int lch, int eidx, int fidx)
{
if (cpu_is_omap24xx()) {
if (cpu_class_is_omap2()) {
REVISIT_24XX();
return;
}
......@@ -317,13 +383,13 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
case OMAP_DMA_DATA_BURST_DIS:
break;
case OMAP_DMA_DATA_BURST_4:
if (cpu_is_omap24xx())
if (cpu_class_is_omap2())
burst = 0x1;
else
burst = 0x2;
break;
case OMAP_DMA_DATA_BURST_8:
if (cpu_is_omap24xx()) {
if (cpu_class_is_omap2()) {
burst = 0x2;
break;
}
......@@ -332,7 +398,7 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
* fall through
*/
case OMAP_DMA_DATA_BURST_16:
if (cpu_is_omap24xx()) {
if (cpu_class_is_omap2()) {
burst = 0x3;
break;
}
......@@ -363,7 +429,7 @@ void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
OMAP1_DMA_CDSA_L_REG(lch) = dest_start;
}
if (cpu_is_omap24xx())
if (cpu_class_is_omap2())
OMAP2_DMA_CDSA_REG(lch) = dest_start;
OMAP_DMA_CDEI_REG(lch) = dst_ei;
......@@ -372,7 +438,7 @@ void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
void omap_set_dma_dest_index(int lch, int eidx, int fidx)
{
if (cpu_is_omap24xx()) {
if (cpu_class_is_omap2()) {
REVISIT_24XX();
return;
}
......@@ -396,19 +462,19 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
case OMAP_DMA_DATA_BURST_DIS:
break;
case OMAP_DMA_DATA_BURST_4:
if (cpu_is_omap24xx())
if (cpu_class_is_omap2())
burst = 0x1;
else
burst = 0x2;
break;
case OMAP_DMA_DATA_BURST_8:
if (cpu_is_omap24xx())
if (cpu_class_is_omap2())
burst = 0x2;
else
burst = 0x3;
break;
case OMAP_DMA_DATA_BURST_16:
if (cpu_is_omap24xx()) {
if (cpu_class_is_omap2()) {
burst = 0x3;
break;
}
......@@ -430,7 +496,7 @@ static inline void omap_enable_channel_irq(int lch)
/* Clear CSR */
if (cpu_class_is_omap1())
status = OMAP_DMA_CSR_REG(lch);
else if (cpu_is_omap24xx())
else if (cpu_class_is_omap2())
OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
/* Enable some nice interrupts. */
......@@ -441,7 +507,7 @@ static inline void omap_enable_channel_irq(int lch)
static void omap_disable_channel_irq(int lch)
{
if (cpu_is_omap24xx())
if (cpu_class_is_omap2())
OMAP_DMA_CICR_REG(lch) = 0;
}
......@@ -464,6 +530,12 @@ static inline void enable_lnk(int lch)
if (dma_chan[lch].next_lch != -1)
OMAP_DMA_CLNK_CTRL_REG(lch) =
dma_chan[lch].next_lch | (1 << 15);
#ifndef CONFIG_ARCH_OMAP1
if (dma_chan[lch].next_linked_ch != -1)
OMAP_DMA_CLNK_CTRL_REG(lch) =
dma_chan[lch].next_linked_ch | (1 << 15);
#endif
}
static inline void disable_lnk(int lch)
......@@ -475,7 +547,7 @@ static inline void disable_lnk(int lch)
OMAP_DMA_CLNK_CTRL_REG(lch) |= 1 << 14;
}
if (cpu_is_omap24xx()) {
if (cpu_class_is_omap2()) {
omap_disable_channel_irq(lch);
/* Clear the ENABLE_LNK bit */
OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 15);
......@@ -488,7 +560,7 @@ static inline void omap2_enable_irq_lch(int lch)
{
u32 val;
if (!cpu_is_omap24xx())
if (!cpu_class_is_omap2())
return;
val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
......@@ -522,7 +594,7 @@ int omap_request_dma(int dev_id, const char *dev_name,
if (cpu_class_is_omap1())
clear_lch_regs(free_ch);
if (cpu_is_omap24xx())
if (cpu_class_is_omap2())
omap_clear_dma(free_ch);
spin_unlock_irqrestore(&dma_chan_lock, flags);
......@@ -530,11 +602,14 @@ int omap_request_dma(int dev_id, const char *dev_name,
chan->dev_name = dev_name;
chan->callback = callback;
chan->data = data;
#ifndef CONFIG_ARCH_OMAP1
chan->chain_id = -1;
#endif
chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
if (cpu_class_is_omap1())
chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
else if (cpu_is_omap24xx())
else if (cpu_class_is_omap2())
chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
OMAP2_DMA_TRANS_ERR_IRQ;
......@@ -551,7 +626,7 @@ int omap_request_dma(int dev_id, const char *dev_name,
OMAP_DMA_CCR_REG(free_ch) = dev_id;
}
if (cpu_is_omap24xx()) {
if (cpu_class_is_omap2()) {
omap2_enable_irq_lch(free_ch);
omap_enable_channel_irq(free_ch);
......@@ -588,7 +663,7 @@ void omap_free_dma(int lch)
OMAP_DMA_CCR_REG(lch) = 0;
}
if (cpu_is_omap24xx()) {
if (cpu_class_is_omap2()) {
u32 val;
/* Disable interrupts */
val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
......@@ -608,6 +683,67 @@ void omap_free_dma(int lch)
}
}
/**
* @brief omap_dma_set_global_params : Set global priority settings for dma
*
* @param arb_rate
* @param max_fifo_depth
* @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
* DMA_THREAD_RESERVE_ONET
* DMA_THREAD_RESERVE_TWOT
* DMA_THREAD_RESERVE_THREET
*/
void
omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
{
u32 reg;
if (!cpu_class_is_omap2()) {
printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __FUNCTION__);
return;
}
if (arb_rate == 0)
arb_rate = 1;
reg = (arb_rate & 0xff) << 16;
reg |= (0xff & max_fifo_depth);
omap_writel(reg, OMAP_DMA4_GCR_REG);
}
EXPORT_SYMBOL(omap_dma_set_global_params);
/**
* @brief omap_dma_set_prio_lch : Set channel wise priority settings
*
* @param lch
* @param read_prio - Read priority
* @param write_prio - Write priority
* Both of the above can be set with one of the following values :
* DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
*/
int
omap_dma_set_prio_lch(int lch, unsigned char read_prio,
unsigned char write_prio)
{
u32 w;
if (unlikely((lch < 0 || lch >= OMAP_LOGICAL_DMA_CH_COUNT))) {
printk(KERN_ERR "Invalid channel id\n");
return -EINVAL;
}
w = OMAP_DMA_CCR_REG(lch);
w &= ~((1 << 6) | (1 << 26));
if (cpu_is_omap2430() || cpu_is_omap34xx())
w |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
else
w |= ((read_prio & 0x1) << 6);
OMAP_DMA_CCR_REG(lch) = w;
return 0;
}
EXPORT_SYMBOL(omap_dma_set_prio_lch);
/*
* Clears any DMA state so the DMA engine is ready to restart with new buffers
* through omap_start_dma(). Any buffers in flight are discarded.
......@@ -626,9 +762,9 @@ void omap_clear_dma(int lch)
status = OMAP_DMA_CSR_REG(lch);
}
if (cpu_is_omap24xx()) {
if (cpu_class_is_omap2()) {
int i;
u32 lch_base = OMAP24XX_DMA_BASE + lch * 0x60 + 0x80;
u32 lch_base = OMAP_DMA4_BASE + lch * 0x60 + 0x80;
for (i = 0; i < 0x44; i += 4)
omap_writel(0, lch_base + i);
}
......@@ -662,7 +798,7 @@ void omap_start_dma(int lch)
cur_lch = next_lch;
} while (next_lch != -1);
} else if (cpu_is_omap24xx()) {
} else if (cpu_class_is_omap2()) {
/* Errata: Need to write lch even if not using chaining */
OMAP_DMA_CLNK_CTRL_REG(lch) = lch;
}
......@@ -753,7 +889,7 @@ dma_addr_t omap_get_dma_src_pos(int lch)
offset = (dma_addr_t) (OMAP1_DMA_CSSA_L_REG(lch) |
(OMAP1_DMA_CSSA_U_REG(lch) << 16));
if (cpu_is_omap24xx())
if (cpu_class_is_omap2())
offset = OMAP_DMA_CSAC_REG(lch);
return offset;
......@@ -775,8 +911,8 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
offset = (dma_addr_t) (OMAP1_DMA_CDSA_L_REG(lch) |
(OMAP1_DMA_CDSA_U_REG(lch) << 16));
if (cpu_is_omap24xx())
offset = OMAP2_DMA_CDSA_REG(lch);
if (cpu_class_is_omap2())
offset = OMAP_DMA_CDAC_REG(lch);
return offset;
}
......@@ -859,6 +995,605 @@ void omap_dma_unlink_lch (int lch_head, int lch_queue)
dma_chan[lch_head].next_lch = -1;
}
#ifndef CONFIG_ARCH_OMAP1
/* Create chain of DMA channesls */
static void create_dma_lch_chain(int lch_head, int lch_queue)
{
u32 w;
/* Check if this is the first link in chain */
if (dma_chan[lch_head].next_linked_ch == -1) {
dma_chan[lch_head].next_linked_ch = lch_queue;
dma_chan[lch_head].prev_linked_ch = lch_queue;
dma_chan[lch_queue].next_linked_ch = lch_head;
dma_chan[lch_queue].prev_linked_ch = lch_head;
}
/* a link exists, link the new channel in circular chain */
else {
dma_chan[lch_queue].next_linked_ch =
dma_chan[lch_head].next_linked_ch;
dma_chan[lch_queue].prev_linked_ch = lch_head;
dma_chan[lch_head].next_linked_ch = lch_queue;
dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
lch_queue;
}
w = OMAP_DMA_CLNK_CTRL_REG(lch_head);
w &= ~(0x0f);
w |= lch_queue;
OMAP_DMA_CLNK_CTRL_REG(lch_head) = w;
w = OMAP_DMA_CLNK_CTRL_REG(lch_queue);
w &= ~(0x0f);
w |= (dma_chan[lch_queue].next_linked_ch);
OMAP_DMA_CLNK_CTRL_REG(lch_queue) = w;
}
/**
* @brief omap_request_dma_chain : Request a chain of DMA channels
*
* @param dev_id - Device id using the dma channel
* @param dev_name - Device name
* @param callback - Call back function
* @chain_id -
* @no_of_chans - Number of channels requested
* @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
* OMAP_DMA_DYNAMIC_CHAIN
* @params - Channel parameters
*
* @return - Succes : 0
* Failure: -EINVAL/-ENOMEM
*/
int omap_request_dma_chain(int dev_id, const char *dev_name,
void (*callback) (int chain_id, u16 ch_status,
void *data),
int *chain_id, int no_of_chans, int chain_mode,
struct omap_dma_channel_params params)
{
int *channels;
int i, err;
/* Is the chain mode valid ? */
if (chain_mode != OMAP_DMA_STATIC_CHAIN
&& chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
printk(KERN_ERR "Invalid chain mode requested\n");
return -EINVAL;
}
if (unlikely((no_of_chans < 1
|| no_of_chans > OMAP_LOGICAL_DMA_CH_COUNT))) {
printk(KERN_ERR "Invalid Number of channels requested\n");
return -EINVAL;
}
/* Allocate a queue to maintain the status of the channels
* in the chain */
channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
if (channels == NULL) {
printk(KERN_ERR "omap_dma: No memory for channel queue\n");
return -ENOMEM;
}
/* request and reserve DMA channels for the chain */
for (i = 0; i < no_of_chans; i++) {
err = omap_request_dma(dev_id, dev_name,
callback, 0, &channels[i]);
if (err < 0) {
int j;
for (j = 0; j < i; j++)
omap_free_dma(channels[j]);
kfree(channels);
printk(KERN_ERR "omap_dma: Request failed %d\n", err);
return err;
}
dma_chan[channels[i]].next_linked_ch = -1;
dma_chan[channels[i]].prev_linked_ch = -1;
dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
/*
* Allowing client drivers to set common parameters now,
* so that later only relevant (src_start, dest_start
* and element count) can be set
*/
omap_set_dma_params(channels[i], &params);
}
*chain_id = channels[0];
dma_linked_lch[*chain_id].linked_dmach_q = channels;
dma_linked_lch[*chain_id].chain_mode = chain_mode;
dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
for (i = 0; i < no_of_chans; i++)
dma_chan[channels[i]].chain_id = *chain_id;
/* Reset the Queue pointers */
OMAP_DMA_CHAIN_QINIT(*chain_id);
/* Set up the chain */
if (no_of_chans == 1)
create_dma_lch_chain(channels[0], channels[0]);
else {
for (i = 0; i < (no_of_chans - 1); i++)
create_dma_lch_chain(channels[i], channels[i + 1]);
}
return 0;
}
EXPORT_SYMBOL(omap_request_dma_chain);
/**
* @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
* params after setting it. Dont do this while dma is running!!
*
* @param chain_id - Chained logical channel id.
* @param params
*
* @return - Success : 0
* Failure : -EINVAL
*/
int omap_modify_dma_chain_params(int chain_id,
struct omap_dma_channel_params params)
{
int *channels;
u32 i;
/* Check for input params */
if (unlikely((chain_id < 0
|| chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
printk(KERN_ERR "Invalid chain id\n");
return -EINVAL;
}
/* Check if the chain exists */
if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
printk(KERN_ERR "Chain doesn't exists\n");
return -EINVAL;
}
channels = dma_linked_lch[chain_id].linked_dmach_q;
for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
/*
* Allowing client drivers to set common parameters now,
* so that later only relevant (src_start, dest_start
* and element count) can be set
*/
omap_set_dma_params(channels[i], &params);
}
return 0;
}
EXPORT_SYMBOL(omap_modify_dma_chain_params);
/**
* @brief omap_free_dma_chain - Free all the logical channels in a chain.
*
* @param chain_id
*
* @return - Success : 0
* Failure : -EINVAL
*/
int omap_free_dma_chain(int chain_id)
{
int *channels;
u32 i;
/* Check for input params */
if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
printk(KERN_ERR "Invalid chain id\n");
return -EINVAL;
}
/* Check if the chain exists */
if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
printk(KERN_ERR "Chain doesn't exists\n");
return -EINVAL;
}
channels = dma_linked_lch[chain_id].linked_dmach_q;
for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
dma_chan[channels[i]].next_linked_ch = -1;
dma_chan[channels[i]].prev_linked_ch = -1;
dma_chan[channels[i]].chain_id = -1;
dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
omap_free_dma(channels[i]);
}
kfree(channels);
dma_linked_lch[chain_id].linked_dmach_q = NULL;
dma_linked_lch[chain_id].chain_mode = -1;
dma_linked_lch[chain_id].chain_state = -1;
return (0);
}
EXPORT_SYMBOL(omap_free_dma_chain);
/**
* @brief omap_dma_chain_status - Check if the chain is in
* active / inactive state.
* @param chain_id
*
* @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
* Failure : -EINVAL
*/
int omap_dma_chain_status(int chain_id)
{
/* Check for input params */
if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
printk(KERN_ERR "Invalid chain id\n");
return -EINVAL;
}
/* Check if the chain exists */
if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
printk(KERN_ERR "Chain doesn't exists\n");
return -EINVAL;
}
pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
dma_linked_lch[chain_id].q_count);
if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
return OMAP_DMA_CHAIN_INACTIVE;
return OMAP_DMA_CHAIN_ACTIVE;
}
EXPORT_SYMBOL(omap_dma_chain_status);
/**
* @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
* set the params and start the transfer.
*
* @param chain_id
* @param src_start - buffer start address
* @param dest_start - Dest address
* @param elem_count
* @param frame_count
* @param callbk_data - channel callback parameter data.
*
* @return - Success : start_dma status
* Failure: -EINVAL/-EBUSY
*/
int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
int elem_count, int frame_count, void *callbk_data)
{
int *channels;
u32 w, lch;
int start_dma = 0;
/* if buffer size is less than 1 then there is
* no use of starting the chain */
if (elem_count < 1) {
printk(KERN_ERR "Invalid buffer size\n");
return -EINVAL;
}
/* Check for input params */
if (unlikely((chain_id < 0
|| chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
printk(KERN_ERR "Invalid chain id\n");
return -EINVAL;
}
/* Check if the chain exists */
if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
printk(KERN_ERR "Chain doesn't exist\n");
return -EINVAL;
}
/* Check if all the channels in chain are in use */
if (OMAP_DMA_CHAIN_QFULL(chain_id))
return -EBUSY;
/* Frame count may be negative in case of indexed transfers */
channels = dma_linked_lch[chain_id].linked_dmach_q;
/* Get a free channel */
lch = channels[dma_linked_lch[chain_id].q_tail];
/* Store the callback data */
dma_chan[lch].data = callbk_data;
/* Increment the q_tail */
OMAP_DMA_CHAIN_INCQTAIL(chain_id);
/* Set the params to the free channel */
if (src_start != 0)
OMAP2_DMA_CSSA_REG(lch) = src_start;
if (dest_start != 0)
OMAP2_DMA_CDSA_REG(lch) = dest_start;
/* Write the buffer size */
OMAP_DMA_CEN_REG(lch) = elem_count;
OMAP_DMA_CFN_REG(lch) = frame_count;
/* If the chain is dynamically linked,
* then we may have to start the chain if its not active */
if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
/* In Dynamic chain, if the chain is not started,
* queue the channel */
if (dma_linked_lch[chain_id].chain_state ==
DMA_CHAIN_NOTSTARTED) {
/* Enable the link in previous channel */
if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
DMA_CH_QUEUED)
enable_lnk(dma_chan[lch].prev_linked_ch);
dma_chan[lch].state = DMA_CH_QUEUED;
}
/* Chain is already started, make sure its active,
* if not then start the chain */
else {
start_dma = 1;
if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
DMA_CH_STARTED) {
enable_lnk(dma_chan[lch].prev_linked_ch);
dma_chan[lch].state = DMA_CH_QUEUED;
start_dma = 0;
if (0 == ((1 << 7) & (OMAP_DMA_CCR_REG
(dma_chan[lch].prev_linked_ch)))) {
disable_lnk(dma_chan[lch].
prev_linked_ch);
pr_debug("\n prev ch is stopped\n");
start_dma = 1;
}
}
else if (dma_chan[dma_chan[lch].prev_linked_ch].state
== DMA_CH_QUEUED) {
enable_lnk(dma_chan[lch].prev_linked_ch);
dma_chan[lch].state = DMA_CH_QUEUED;
start_dma = 0;
}
omap_enable_channel_irq(lch);
w = OMAP_DMA_CCR_REG(lch);
if ((0 == (w & (1 << 24))))
w &= ~(1 << 25);
else
w |= (1 << 25);
if (start_dma == 1) {
if (0 == (w & (1 << 7))) {
w |= (1 << 7);
dma_chan[lch].state = DMA_CH_STARTED;
pr_debug("starting %d\n", lch);
OMAP_DMA_CCR_REG(lch) = w;
} else
start_dma = 0;
} else {
if (0 == (w & (1 << 7)))
OMAP_DMA_CCR_REG(lch) = w;
}
dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
}
}
return start_dma;
}
EXPORT_SYMBOL(omap_dma_chain_a_transfer);
/**
* @brief omap_start_dma_chain_transfers - Start the chain
*
* @param chain_id
*
* @return - Success : 0
* Failure : -EINVAL/-EBUSY
*/
int omap_start_dma_chain_transfers(int chain_id)
{
int *channels;
u32 w, i;
if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
printk(KERN_ERR "Invalid chain id\n");
return -EINVAL;
}
channels = dma_linked_lch[chain_id].linked_dmach_q;
if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
printk(KERN_ERR "Chain is already started\n");
return -EBUSY;
}
if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
i++) {
enable_lnk(channels[i]);
omap_enable_channel_irq(channels[i]);
}
} else {
omap_enable_channel_irq(channels[0]);
}
w = OMAP_DMA_CCR_REG(channels[0]);
w |= (1 << 7);
dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
dma_chan[channels[0]].state = DMA_CH_STARTED;
if ((0 == (w & (1 << 24))))
w &= ~(1 << 25);
else
w |= (1 << 25);
OMAP_DMA_CCR_REG(channels[0]) = w;
dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
return 0;
}
EXPORT_SYMBOL(omap_start_dma_chain_transfers);
/**
* @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
*
* @param chain_id
*
* @return - Success : 0
* Failure : EINVAL
*/
int omap_stop_dma_chain_transfers(int chain_id)
{
int *channels;
u32 w, i;
u32 sys_cf;
/* Check for input params */
if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
printk(KERN_ERR "Invalid chain id\n");
return -EINVAL;
}
/* Check if the chain exists */
if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
printk(KERN_ERR "Chain doesn't exists\n");
return -EINVAL;
}
channels = dma_linked_lch[chain_id].linked_dmach_q;
/* DMA Errata:
* Special programming model needed to disable DMA before end of block
*/
sys_cf = omap_readl(OMAP_DMA4_OCP_SYSCONFIG);
w = sys_cf;
/* Middle mode reg set no Standby */
w &= ~((1 << 12)|(1 << 13));
omap_writel(w, OMAP_DMA4_OCP_SYSCONFIG);
for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
/* Stop the Channel transmission */
w = OMAP_DMA_CCR_REG(channels[i]);
w &= ~(1 << 7);
OMAP_DMA_CCR_REG(channels[i]) = w;
/* Disable the link in all the channels */
disable_lnk(channels[i]);
dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
}
dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
/* Reset the Queue pointers */
OMAP_DMA_CHAIN_QINIT(chain_id);
/* Errata - put in the old value */
omap_writel(sys_cf, OMAP_DMA4_OCP_SYSCONFIG);
return 0;
}
EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
/* Get the index of the ongoing DMA in chain */
/**
* @brief omap_get_dma_chain_index - Get the element and frame index
* of the ongoing DMA in chain
*
* @param chain_id
* @param ei - Element index
* @param fi - Frame index
*
* @return - Success : 0
* Failure : -EINVAL
*/
int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
{
int lch;
int *channels;
/* Check for input params */
if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
printk(KERN_ERR "Invalid chain id\n");
return -EINVAL;
}
/* Check if the chain exists */
if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
printk(KERN_ERR "Chain doesn't exists\n");
return -EINVAL;
}
if ((!ei) || (!fi))
return -EINVAL;
channels = dma_linked_lch[chain_id].linked_dmach_q;
/* Get the current channel */
lch = channels[dma_linked_lch[chain_id].q_head];
*ei = OMAP2_DMA_CCEN_REG(lch);
*fi = OMAP2_DMA_CCFN_REG(lch);
return 0;
}
EXPORT_SYMBOL(omap_get_dma_chain_index);
/**
* @brief omap_get_dma_chain_dst_pos - Get the destination position of the
* ongoing DMA in chain
*
* @param chain_id
*
* @return - Success : Destination position
* Failure : -EINVAL
*/
int omap_get_dma_chain_dst_pos(int chain_id)
{
int lch;
int *channels;
/* Check for input params */
if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
printk(KERN_ERR "Invalid chain id\n");
return -EINVAL;
}
/* Check if the chain exists */
if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
printk(KERN_ERR "Chain doesn't exists\n");
return -EINVAL;
}
channels = dma_linked_lch[chain_id].linked_dmach_q;
/* Get the current channel */
lch = channels[dma_linked_lch[chain_id].q_head];
return (OMAP_DMA_CDAC_REG(lch));
}
EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
/**
* @brief omap_get_dma_chain_src_pos - Get the source position
* of the ongoing DMA in chain
* @param chain_id
*
* @return - Success : Destination position
* Failure : -EINVAL
*/
int omap_get_dma_chain_src_pos(int chain_id)
{
int lch;
int *channels;
/* Check for input params */
if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) {
printk(KERN_ERR "Invalid chain id\n");
return -EINVAL;
}
/* Check if the chain exists */
if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
printk(KERN_ERR "Chain doesn't exists\n");
return -EINVAL;
}
channels = dma_linked_lch[chain_id].linked_dmach_q;
/* Get the current channel */
lch = channels[dma_linked_lch[chain_id].q_head];
return (OMAP_DMA_CSAC_REG(lch));
}
EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
#endif
/*----------------------------------------------------------------------------*/
#ifdef CONFIG_ARCH_OMAP1
......@@ -919,7 +1654,7 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
#define omap1_dma_irq_handler NULL
#endif
#ifdef CONFIG_ARCH_OMAP2
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
static int omap2_dma_handle_ch(int ch)
{
......@@ -953,8 +1688,33 @@ static int omap2_dma_handle_ch(int ch)
OMAP_DMA_CSR_REG(ch) = OMAP2_DMA_CSR_CLEAR_MASK;
omap_writel(1 << ch, OMAP_DMA4_IRQSTATUS_L0);
if (likely(dma_chan[ch].callback != NULL))
dma_chan[ch].callback(ch, status, dma_chan[ch].data);
/* If the ch is not chained then chain_id will be -1 */
if (dma_chan[ch].chain_id != -1) {
int chain_id = dma_chan[ch].chain_id;
dma_chan[ch].state = DMA_CH_NOTSTARTED;
if (OMAP_DMA_CLNK_CTRL_REG(ch) & (1 << 15))
dma_chan[dma_chan[ch].next_linked_ch].state =
DMA_CH_STARTED;
if (dma_linked_lch[chain_id].chain_mode ==
OMAP_DMA_DYNAMIC_CHAIN)
disable_lnk(ch);
if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
OMAP_DMA_CHAIN_INCQHEAD(chain_id);
status = OMAP_DMA_CSR_REG(ch);
}
if (likely(dma_chan[ch].callback != NULL)) {
if (dma_chan[ch].chain_id != -1)
dma_chan[ch].callback(dma_chan[ch].chain_id, status,
dma_chan[ch].data);
else
dma_chan[ch].callback(ch, status, dma_chan[ch].data);
}
OMAP_DMA_CSR_REG(ch) = status;
return 0;
}
......@@ -1385,7 +2145,7 @@ static int __init omap_init_dma(void)
w &= ~(1 << 8);
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
}
} else if (cpu_is_omap24xx()) {
} else if (cpu_class_is_omap2()) {
u8 revision = omap_readb(OMAP_DMA4_REVISION);
printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
revision >> 4, revision & 0xf);
......@@ -1428,7 +2188,11 @@ static int __init omap_init_dma(void)
}
}
if (cpu_is_omap24xx())
if (cpu_is_omap2430() || cpu_is_omap34xx())
omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
DMA_DEFAULT_FIFO_DEPTH, 0);
if (cpu_class_is_omap2())
setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
/* FIXME: Update LCD DMA to work on 24xx */
......
arch/arm/plat-omap/dmtimer.c
View file @ 0eccf60b
......@@ -48,7 +48,7 @@
#define OMAP_TIMER_COUNTER_REG 0x28
#define OMAP_TIMER_LOAD_REG 0x2c
#define OMAP_TIMER_TRIGGER_REG 0x30
#define OMAP_TIMER_WRITE_PEND_REG 0x34
#define OMAP_TIMER_WRITE_PEND_REG 0x34
#define OMAP_TIMER_MATCH_REG 0x38
#define OMAP_TIMER_CAPTURE_REG 0x3c
#define OMAP_TIMER_IF_CTRL_REG 0x40
......@@ -70,7 +70,7 @@
struct omap_dm_timer {
unsigned long phys_base;
int irq;
#ifdef CONFIG_ARCH_OMAP2
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
struct clk *iclk, *fclk;
#endif
void __iomem *io_base;
......@@ -82,8 +82,14 @@ struct omap_dm_timer {
#define omap_dm_clk_enable(x)
#define omap_dm_clk_disable(x)
static struct omap_dm_timer dm_timers[] = {
#define omap2_dm_timers NULL
#define omap2_dm_source_names NULL
#define omap2_dm_source_clocks NULL
#define omap3_dm_timers NULL
#define omap3_dm_source_names NULL
#define omap3_dm_source_clocks NULL
static struct omap_dm_timer omap1_dm_timers[] = {
{ .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
{ .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
{ .phys_base = 0xfffb2400, .irq = INT_1610_GPTIMER3 },
......@@ -94,12 +100,18 @@ static struct omap_dm_timer dm_timers[] = {
{ .phys_base = 0xfffbd400, .irq = INT_1610_GPTIMER8 },
};
static const int dm_timer_count = ARRAY_SIZE(omap1_dm_timers);
#elif defined(CONFIG_ARCH_OMAP2)
#define omap_dm_clk_enable(x) clk_enable(x)
#define omap_dm_clk_disable(x) clk_disable(x)
#define omap_dm_clk_enable(x) clk_enable(x)
#define omap_dm_clk_disable(x) clk_disable(x)
#define omap1_dm_timers NULL
#define omap3_dm_timers NULL
#define omap3_dm_source_names NULL
#define omap3_dm_source_clocks NULL
static struct omap_dm_timer dm_timers[] = {
static struct omap_dm_timer omap2_dm_timers[] = {
{ .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
{ .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
{ .phys_base = 0x48078000, .irq = INT_24XX_GPTIMER3 },
......@@ -114,13 +126,48 @@ static struct omap_dm_timer dm_timers[] = {
{ .phys_base = 0x4808a000, .irq = INT_24XX_GPTIMER12 },
};
static const char *dm_source_names[] = {
static const char *omap2_dm_source_names[] __initdata = {
"sys_ck",
"func_32k_ck",
"alt_ck"
"alt_ck",
NULL
};
static struct clk **omap2_dm_source_clocks[3];
static const int dm_timer_count = ARRAY_SIZE(omap2_dm_timers);
#elif defined(CONFIG_ARCH_OMAP3)
#define omap_dm_clk_enable(x) clk_enable(x)
#define omap_dm_clk_disable(x) clk_disable(x)
#define omap1_dm_timers NULL
#define omap2_dm_timers NULL
#define omap2_dm_source_names NULL
#define omap2_dm_source_clocks NULL
static struct omap_dm_timer omap3_dm_timers[] = {
{ .phys_base = 0x48318000, .irq = INT_24XX_GPTIMER1 },
{ .phys_base = 0x49032000, .irq = INT_24XX_GPTIMER2 },
{ .phys_base = 0x49034000, .irq = INT_24XX_GPTIMER3 },
{ .phys_base = 0x49036000, .irq = INT_24XX_GPTIMER4 },
{ .phys_base = 0x49038000, .irq = INT_24XX_GPTIMER5 },
{ .phys_base = 0x4903A000, .irq = INT_24XX_GPTIMER6 },
{ .phys_base = 0x4903C000, .irq = INT_24XX_GPTIMER7 },
{ .phys_base = 0x4903E000, .irq = INT_24XX_GPTIMER8 },
{ .phys_base = 0x49040000, .irq = INT_24XX_GPTIMER9 },
{ .phys_base = 0x48086000, .irq = INT_24XX_GPTIMER10 },
{ .phys_base = 0x48088000, .irq = INT_24XX_GPTIMER11 },
{ .phys_base = 0x48304000, .irq = INT_24XX_GPTIMER12 },
};
static const char *omap3_dm_source_names[] __initdata = {
"sys_ck",
"omap_32k_fck",
NULL
};
static struct clk *dm_source_clocks[3];
static struct clk **omap3_dm_source_clocks[2];
static const int dm_timer_count = ARRAY_SIZE(omap3_dm_timers);
#else
......@@ -128,7 +175,10 @@ static struct clk *dm_source_clocks[3];
#endif
static const int dm_timer_count = ARRAY_SIZE(dm_timers);
static struct omap_dm_timer *dm_timers;
static char **dm_source_names;
static struct clk **dm_source_clocks;
static spinlock_t dm_timer_lock;
static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg)
......@@ -299,7 +349,7 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
return inputmask;
}
#elif defined(CONFIG_ARCH_OMAP2)
#elif defined(CONFIG_ARCH_OMAP2) || defined (CONFIG_ARCH_OMAP3)
struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
{
......@@ -486,36 +536,46 @@ int omap_dm_timers_active(void)
return 0;
}
int omap_dm_timer_init(void)
int __init omap_dm_timer_init(void)
{
struct omap_dm_timer *timer;
int i;
if (!(cpu_is_omap16xx() || cpu_is_omap24xx()))
if (!(cpu_is_omap16xx() || cpu_class_is_omap2()))
return -ENODEV;
spin_lock_init(&dm_timer_lock);
#ifdef CONFIG_ARCH_OMAP2
for (i = 0; i < ARRAY_SIZE(dm_source_names); i++) {
dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]);
BUG_ON(dm_source_clocks[i] == NULL);
if (cpu_class_is_omap1())
dm_timers = omap1_dm_timers;
else if (cpu_is_omap24xx()) {
dm_timers = omap2_dm_timers;
dm_source_names = (char **)omap2_dm_source_names;
dm_source_clocks = (struct clk **)omap2_dm_source_clocks;
} else if (cpu_is_omap34xx()) {
dm_timers = omap3_dm_timers;
dm_source_names = (char **)omap3_dm_source_names;
dm_source_clocks = (struct clk **)omap3_dm_source_clocks;
}
#endif
if (cpu_class_is_omap2())
for (i = 0; dm_source_names[i] != NULL; i++)
dm_source_clocks[i] = clk_get(NULL, dm_source_names[i]);
if (cpu_is_omap243x())
dm_timers[0].phys_base = 0x49018000;
for (i = 0; i < dm_timer_count; i++) {
#ifdef CONFIG_ARCH_OMAP2
char clk_name[16];
#endif
timer = &dm_timers[i];
timer->io_base = (void __iomem *) io_p2v(timer->phys_base);
#ifdef CONFIG_ARCH_OMAP2
sprintf(clk_name, "gpt%d_ick", i + 1);
timer->iclk = clk_get(NULL, clk_name);
sprintf(clk_name, "gpt%d_fck", i + 1);
timer->fclk = clk_get(NULL, clk_name);
timer->io_base = (void __iomem *)io_p2v(timer->phys_base);
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
if (cpu_class_is_omap2()) {
char clk_name[16];
sprintf(clk_name, "gpt%d_ick", i + 1);
timer->iclk = clk_get(NULL, clk_name);
sprintf(clk_name, "gpt%d_fck", i + 1);
timer->fclk = clk_get(NULL, clk_name);
}
#endif
}
......
arch/arm/plat-omap/gpio.c
View file @ 0eccf60b
......@@ -110,6 +110,8 @@
#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
#define OMAP24XX_GPIO_RISINGDETECT 0x0048
#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
......@@ -117,17 +119,29 @@
#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
#define OMAP24XX_GPIO_SETDATAOUT 0x0094
/*
* omap34xx specific GPIO registers
*/
#define OMAP34XX_GPIO1_BASE (void __iomem *)0x48310000
#define OMAP34XX_GPIO2_BASE (void __iomem *)0x49050000
#define OMAP34XX_GPIO3_BASE (void __iomem *)0x49052000
#define OMAP34XX_GPIO4_BASE (void __iomem *)0x49054000
#define OMAP34XX_GPIO5_BASE (void __iomem *)0x49056000
#define OMAP34XX_GPIO6_BASE (void __iomem *)0x49058000
struct gpio_bank {
void __iomem *base;
u16 irq;
u16 virtual_irq_start;
int method;
u32 reserved_map;
#if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
u32 suspend_wakeup;
u32 saved_wakeup;
#endif
#ifdef CONFIG_ARCH_OMAP24XX
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
u32 non_wakeup_gpios;
u32 enabled_non_wakeup_gpios;
......@@ -192,48 +206,52 @@ static struct gpio_bank gpio_bank_243x[5] = {
#endif
#ifdef CONFIG_ARCH_OMAP34XX
static struct gpio_bank gpio_bank_34xx[6] = {
{ OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
{ OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
{ OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
{ OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
{ OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
{ OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
};
#endif
static struct gpio_bank *gpio_bank;
static int gpio_bank_count;
static inline struct gpio_bank *get_gpio_bank(int gpio)
{
#ifdef CONFIG_ARCH_OMAP15XX
if (cpu_is_omap15xx()) {
if (OMAP_GPIO_IS_MPUIO(gpio))
return &gpio_bank[0];
return &gpio_bank[1];
}
#endif
#if defined(CONFIG_ARCH_OMAP16XX)
if (cpu_is_omap16xx()) {
if (OMAP_GPIO_IS_MPUIO(gpio))
return &gpio_bank[0];
return &gpio_bank[1 + (gpio >> 4)];
}
#endif
#ifdef CONFIG_ARCH_OMAP730
if (cpu_is_omap730()) {
if (OMAP_GPIO_IS_MPUIO(gpio))
return &gpio_bank[0];
return &gpio_bank[1 + (gpio >> 5)];
}
#endif
#ifdef CONFIG_ARCH_OMAP24XX
if (cpu_is_omap24xx())
return &gpio_bank[gpio >> 5];
#endif
if (cpu_is_omap34xx())
return &gpio_bank[gpio >> 5];
}
static inline int get_gpio_index(int gpio)
{
#ifdef CONFIG_ARCH_OMAP730
if (cpu_is_omap730())
return gpio & 0x1f;
#endif
#ifdef CONFIG_ARCH_OMAP24XX
if (cpu_is_omap24xx())
return gpio & 0x1f;
#endif
if (cpu_is_omap34xx())
return gpio & 0x1f;
return gpio & 0x0f;
}
......@@ -241,29 +259,21 @@ static inline int gpio_valid(int gpio)
{
if (gpio < 0)
return -1;
#ifndef CONFIG_ARCH_OMAP24XX
if (OMAP_GPIO_IS_MPUIO(gpio)) {
if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
if (gpio >= OMAP_MAX_GPIO_LINES + 16)
return -1;
return 0;
}
#endif
#ifdef CONFIG_ARCH_OMAP15XX
if (cpu_is_omap15xx() && gpio < 16)
return 0;
#endif
#if defined(CONFIG_ARCH_OMAP16XX)
if ((cpu_is_omap16xx()) && gpio < 64)
return 0;
#endif
#ifdef CONFIG_ARCH_OMAP730
if (cpu_is_omap730() && gpio < 192)
return 0;
#endif
#ifdef CONFIG_ARCH_OMAP24XX
if (cpu_is_omap24xx() && gpio < 128)
return 0;
#endif
if (cpu_is_omap34xx() && gpio < 160)
return 0;
return -1;
}
......@@ -303,7 +313,7 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
reg += OMAP730_GPIO_DIR_CONTROL;
break;
#endif
#ifdef CONFIG_ARCH_OMAP24XX
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
case METHOD_GPIO_24XX:
reg += OMAP24XX_GPIO_OE;
break;
......@@ -377,7 +387,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
l &= ~(1 << gpio);
break;
#endif
#ifdef CONFIG_ARCH_OMAP24XX
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
case METHOD_GPIO_24XX:
if (enable)
reg += OMAP24XX_GPIO_SETDATAOUT;
......@@ -435,7 +445,7 @@ int omap_get_gpio_datain(int gpio)
reg += OMAP730_GPIO_DATA_INPUT;
break;
#endif
#ifdef CONFIG_ARCH_OMAP24XX
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
case METHOD_GPIO_24XX:
reg += OMAP24XX_GPIO_DATAIN;
break;
......@@ -455,8 +465,50 @@ do { \
__raw_writel(l, base + reg); \
} while(0)
#ifdef CONFIG_ARCH_OMAP24XX
static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
void omap_set_gpio_debounce(int gpio, int enable)
{
struct gpio_bank *bank;
void __iomem *reg;
u32 val, l = 1 << get_gpio_index(gpio);
if (cpu_class_is_omap1())
return;
bank = get_gpio_bank(gpio);
reg = bank->base;
reg += OMAP24XX_GPIO_DEBOUNCE_EN;
val = __raw_readl(reg);
if (enable)
val |= l;
else
val &= ~l;
__raw_writel(val, reg);
}
EXPORT_SYMBOL(omap_set_gpio_debounce);
void omap_set_gpio_debounce_time(int gpio, int enc_time)
{
struct gpio_bank *bank;
void __iomem *reg;
if (cpu_class_is_omap1())
return;
bank = get_gpio_bank(gpio);
reg = bank->base;
enc_time &= 0xff;
reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
__raw_writel(enc_time, reg);
}
EXPORT_SYMBOL(omap_set_gpio_debounce_time);
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
int trigger)
{
void __iomem *base = bank->base;
u32 gpio_bit = 1 << gpio;
......@@ -469,19 +521,25 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, in
trigger & __IRQT_RISEDGE);
MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
trigger & __IRQT_FALEDGE);
if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
if (trigger != 0)
__raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_SETWKUENA);
__raw_writel(1 << gpio, bank->base
+ OMAP24XX_GPIO_SETWKUENA);
else
__raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_CLEARWKUENA);
__raw_writel(1 << gpio, bank->base
+ OMAP24XX_GPIO_CLEARWKUENA);
} else {
if (trigger != 0)
bank->enabled_non_wakeup_gpios |= gpio_bit;
else
bank->enabled_non_wakeup_gpios &= ~gpio_bit;
}
/* FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only level
* triggering requested. */
/*
* FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only
* level triggering requested.
*/
}
#endif
......@@ -547,7 +605,7 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
goto bad;
break;
#endif
#ifdef CONFIG_ARCH_OMAP24XX
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
case METHOD_GPIO_24XX:
set_24xx_gpio_triggering(bank, gpio, trigger);
break;
......@@ -567,7 +625,7 @@ static int gpio_irq_type(unsigned irq, unsigned type)
unsigned gpio;
int retval;
if (!cpu_is_omap24xx() && irq > IH_MPUIO_BASE)
if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
else
gpio = irq - IH_GPIO_BASE;
......@@ -579,7 +637,7 @@ static int gpio_irq_type(unsigned irq, unsigned type)
return -EINVAL;
/* OMAP1 allows only only edge triggering */
if (!cpu_is_omap24xx()
if (!cpu_class_is_omap2()
&& (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
return -EINVAL;
......@@ -620,7 +678,7 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
reg += OMAP730_GPIO_INT_STATUS;
break;
#endif
#ifdef CONFIG_ARCH_OMAP24XX
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
case METHOD_GPIO_24XX:
reg += OMAP24XX_GPIO_IRQSTATUS1;
break;
......@@ -632,8 +690,10 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
__raw_writel(gpio_mask, reg);
/* Workaround for clearing DSP GPIO interrupts to allow retention */
if (cpu_is_omap2420())
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
if (cpu_is_omap24xx() || cpu_is_omap34xx())
__raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
#endif
}
static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
......@@ -676,7 +736,7 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
inv = 1;
break;
#endif
#ifdef CONFIG_ARCH_OMAP24XX
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
case METHOD_GPIO_24XX:
reg += OMAP24XX_GPIO_IRQENABLE1;
mask = 0xffffffff;
......@@ -739,7 +799,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
l |= gpio_mask;
break;
#endif
#ifdef CONFIG_ARCH_OMAP24XX
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
case METHOD_GPIO_24XX:
if (enable)
reg += OMAP24XX_GPIO_SETIRQENABLE1;
......@@ -785,7 +845,7 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
spin_unlock(&bank->lock);
return 0;
#endif
#ifdef CONFIG_ARCH_OMAP24XX
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
case METHOD_GPIO_24XX:
if (bank->non_wakeup_gpios & (1 << gpio)) {
printk(KERN_ERR "Unable to modify wakeup on "
......@@ -891,7 +951,7 @@ void omap_free_gpio(int gpio)
__raw_writel(1 << get_gpio_index(gpio), reg);
}
#endif
#ifdef CONFIG_ARCH_OMAP24XX
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
if (bank->method == METHOD_GPIO_24XX) {
/* Disable wake-up during idle for dynamic tick */
void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
......@@ -940,7 +1000,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
if (bank->method == METHOD_GPIO_730)
isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
#endif
#ifdef CONFIG_ARCH_OMAP24XX
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
if (bank->method == METHOD_GPIO_24XX)
isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
#endif
......@@ -954,7 +1014,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
isr &= 0x0000ffff;
if (cpu_is_omap24xx()) {
if (cpu_class_is_omap2()) {
level_mask =
__raw_readl(bank->base +
OMAP24XX_GPIO_LEVELDETECT0) |
......@@ -1023,7 +1083,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
}
}
if (cpu_is_omap24xx()) {
if (cpu_class_is_omap2()) {
/* clear level sensitive interrupts after handler(s) */
_enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
_clear_gpio_irqbank(bank, isr_saved & level_mask);
......@@ -1199,21 +1259,35 @@ static inline void mpuio_init(void) {}
/*---------------------------------------------------------------------*/
static int initialized;
#if !defined(CONFIG_ARCH_OMAP3)
static struct clk * gpio_ick;
#endif
#if defined(CONFIG_ARCH_OMAP2)
static struct clk * gpio_fck;
#endif
#ifdef CONFIG_ARCH_OMAP2430
#if defined(CONFIG_ARCH_OMAP2430)
static struct clk * gpio5_ick;
static struct clk * gpio5_fck;
#endif
#if defined(CONFIG_ARCH_OMAP3)
static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS];
static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
#endif
static int __init _omap_gpio_init(void)
{
int i;
struct gpio_bank *bank;
#if defined(CONFIG_ARCH_OMAP3)
char clk_name[11];
#endif
initialized = 1;
#if defined(CONFIG_ARCH_OMAP1)
if (cpu_is_omap15xx()) {
gpio_ick = clk_get(NULL, "arm_gpio_ck");
if (IS_ERR(gpio_ick))
......@@ -1221,7 +1295,9 @@ static int __init _omap_gpio_init(void)
else
clk_enable(gpio_ick);
}
if (cpu_is_omap24xx()) {
#endif
#if defined(CONFIG_ARCH_OMAP2)
if (cpu_class_is_omap2()) {
gpio_ick = clk_get(NULL, "gpios_ick");
if (IS_ERR(gpio_ick))
printk("Could not get gpios_ick\n");
......@@ -1234,9 +1310,9 @@ static int __init _omap_gpio_init(void)
clk_enable(gpio_fck);
/*
* On 2430 GPIO 5 uses CORE L4 ICLK
* On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
*/
#ifdef CONFIG_ARCH_OMAP2430
#if defined(CONFIG_ARCH_OMAP2430)
if (cpu_is_omap2430()) {
gpio5_ick = clk_get(NULL, "gpio5_ick");
if (IS_ERR(gpio5_ick))
......@@ -1250,7 +1326,28 @@ static int __init _omap_gpio_init(void)
clk_enable(gpio5_fck);
}
#endif
}
}
#endif
#if defined(CONFIG_ARCH_OMAP3)
if (cpu_is_omap34xx()) {
for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
sprintf(clk_name, "gpio%d_ick", i + 1);
gpio_iclks[i] = clk_get(NULL, clk_name);
if (IS_ERR(gpio_iclks[i]))
printk(KERN_ERR "Could not get %s\n", clk_name);
else
clk_enable(gpio_iclks[i]);
sprintf(clk_name, "gpio%d_fck", i + 1);
gpio_fclks[i] = clk_get(NULL, clk_name);
if (IS_ERR(gpio_fclks[i]))
printk(KERN_ERR "Could not get %s\n", clk_name);
else
clk_enable(gpio_fclks[i]);
}
}
#endif
#ifdef CONFIG_ARCH_OMAP15XX
if (cpu_is_omap15xx()) {
......@@ -1297,6 +1394,17 @@ static int __init _omap_gpio_init(void)
printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
(rev >> 4) & 0x0f, rev & 0x0f);
}
#endif
#ifdef CONFIG_ARCH_OMAP34XX
if (cpu_is_omap34xx()) {
int rev;
gpio_bank_count = OMAP34XX_NR_GPIOS;
gpio_bank = gpio_bank_34xx;
rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
(rev >> 4) & 0x0f, rev & 0x0f);
}
#endif
for (i = 0; i < gpio_bank_count; i++) {
int j, gpio_count = 16;
......@@ -1307,28 +1415,23 @@ static int __init _omap_gpio_init(void)
spin_lock_init(&bank->lock);
if (bank_is_mpuio(bank))
omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
#ifdef CONFIG_ARCH_OMAP15XX
if (bank->method == METHOD_GPIO_1510) {
if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
__raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
__raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
}
#endif
#if defined(CONFIG_ARCH_OMAP16XX)
if (bank->method == METHOD_GPIO_1610) {
if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
__raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
__raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
__raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
}
#endif
#ifdef CONFIG_ARCH_OMAP730
if (bank->method == METHOD_GPIO_730) {
if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) {
__raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
__raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
gpio_count = 32; /* 730 has 32-bit GPIOs */
}
#endif
#ifdef CONFIG_ARCH_OMAP24XX
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
if (bank->method == METHOD_GPIO_24XX) {
static const u32 non_wakeup_gpios[] = {
0xe203ffc0, 0x08700040
......@@ -1364,21 +1467,21 @@ static int __init _omap_gpio_init(void)
if (cpu_is_omap16xx())
omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
#ifdef CONFIG_ARCH_OMAP24XX
/* Enable autoidle for the OCP interface */
if (cpu_is_omap24xx())
omap_writel(1 << 0, 0x48019010);
#endif
if (cpu_is_omap34xx())
omap_writel(1 << 0, 0x48306814);
return 0;
}
#if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
{
int i;
if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
return 0;
for (i = 0; i < gpio_bank_count; i++) {
......@@ -1395,7 +1498,7 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
break;
#endif
#ifdef CONFIG_ARCH_OMAP24XX
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
case METHOD_GPIO_24XX:
wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
......@@ -1435,7 +1538,7 @@ static int omap_gpio_resume(struct sys_device *dev)
wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
break;
#endif
#ifdef CONFIG_ARCH_OMAP24XX
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
case METHOD_GPIO_24XX:
wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
......@@ -1467,7 +1570,7 @@ static struct sys_device omap_gpio_device = {
#endif
#ifdef CONFIG_ARCH_OMAP24XX
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
static int workaround_enabled;
......@@ -1483,15 +1586,19 @@ void omap2_gpio_prepare_for_retention(void)
if (!(bank->enabled_non_wakeup_gpios))
continue;
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
#endif
bank->saved_fallingdetect = l1;
bank->saved_risingdetect = l2;
l1 &= ~bank->enabled_non_wakeup_gpios;
l2 &= ~bank->enabled_non_wakeup_gpios;
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
__raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
__raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
#endif
c++;
}
if (!c) {
......@@ -1513,26 +1620,31 @@ void omap2_gpio_resume_after_retention(void)
if (!(bank->enabled_non_wakeup_gpios))
continue;
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
__raw_writel(bank->saved_fallingdetect,
bank->base + OMAP24XX_GPIO_FALLINGDETECT);
__raw_writel(bank->saved_risingdetect,
bank->base + OMAP24XX_GPIO_RISINGDETECT);
#endif
/* Check if any of the non-wakeup interrupt GPIOs have changed
* state. If so, generate an IRQ by software. This is
* horribly racy, but it's the best we can do to work around
* this silicon bug. */
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
#endif
l ^= bank->saved_datain;
l &= bank->non_wakeup_gpios;
if (l) {
u32 old0, old1;
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
__raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
__raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
__raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
__raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
#endif
}
}
......@@ -1561,8 +1673,8 @@ static int __init omap_gpio_sysinit(void)
mpuio_init();
#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX)
if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
if (ret == 0) {
ret = sysdev_class_register(&omap_gpio_sysclass);
if (ret == 0)
......@@ -1624,7 +1736,7 @@ static int dbg_gpio_show(struct seq_file *s, void *unused)
if (bank_is_mpuio(bank))
gpio = OMAP_MPUIO(0);
else if (cpu_is_omap24xx() || cpu_is_omap730())
else if (cpu_class_is_omap2() || cpu_is_omap730())
bankwidth = 32;
for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
......
arch/arm/plat-omap/i2c.c 0 → 100644
View file @ 0eccf60b
/*
* linux/arch/arm/plat-omap/i2c.c
*
* Helper module for board specific I2C bus registration
*
* Copyright (C) 2007 Nokia Corporation.
*
* Contact: Jarkko Nikula <jarkko.nikula@nokia.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <asm/mach-types.h>
#include <asm/arch/mux.h>
#define OMAP_I2C_SIZE 0x3f
#define OMAP1_I2C_BASE 0xfffb3800
#define OMAP2_I2C_BASE1 0x48070000
#define OMAP2_I2C_BASE2 0x48072000
#define OMAP2_I2C_BASE3 0x48060000
static const char name[] = "i2c_omap";
#define I2C_RESOURCE_BUILDER(base, irq) \
{ \
.start = (base), \
.end = (base) + OMAP_I2C_SIZE, \
.flags = IORESOURCE_MEM, \
}, \
{ \
.start = (irq), \
.flags = IORESOURCE_IRQ, \
},
static struct resource i2c_resources[][2] = {
{ I2C_RESOURCE_BUILDER(0, 0) },
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
{ I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE2, INT_24XX_I2C2_IRQ) },
#endif
#if defined(CONFIG_ARCH_OMAP34XX)
{ I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE3, INT_34XX_I2C3_IRQ) },
#endif
};
#define I2C_DEV_BUILDER(bus_id, res, data) \
{ \
.id = (bus_id), \
.name = name, \
.num_resources = ARRAY_SIZE(res), \
.resource = (res), \
.dev = { \
.platform_data = (data), \
}, \
}
static u32 i2c_rate[ARRAY_SIZE(i2c_resources)];
static struct platform_device omap_i2c_devices[] = {
I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_rate[0]),
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_rate[1]),
#endif
#if defined(CONFIG_ARCH_OMAP34XX)
I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_rate[2]),
#endif
};
static void __init omap_i2c_mux_pins(int bus_id)
{
/* TODO: Muxing for OMAP3 */
switch (bus_id) {
case 1:
if (cpu_class_is_omap1()) {
omap_cfg_reg(I2C_SCL);
omap_cfg_reg(I2C_SDA);
} else if (cpu_is_omap24xx()) {
omap_cfg_reg(M19_24XX_I2C1_SCL);
omap_cfg_reg(L15_24XX_I2C1_SDA);
}
break;
case 2:
if (cpu_is_omap24xx()) {
omap_cfg_reg(J15_24XX_I2C2_SCL);
omap_cfg_reg(H19_24XX_I2C2_SDA);
}
break;
}
}
int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
struct i2c_board_info const *info,
unsigned len)
{
int ports, err;
struct platform_device *pdev;
struct resource *res;
resource_size_t base, irq;
if (cpu_class_is_omap1())
ports = 1;
else if (cpu_is_omap24xx())
ports = 2;
else if (cpu_is_omap34xx())
ports = 3;
BUG_ON(bus_id < 1 || bus_id > ports);
if (info) {
err = i2c_register_board_info(bus_id, info, len);
if (err)
return err;
}
pdev = &omap_i2c_devices[bus_id - 1];
*(u32 *)pdev->dev.platform_data = clkrate;
if (bus_id == 1) {
res = pdev->resource;
if (cpu_class_is_omap1()) {
base = OMAP1_I2C_BASE;
irq = INT_I2C;
} else {
base = OMAP2_I2C_BASE1;
irq = INT_24XX_I2C1_IRQ;
}
res[0].start = base;
res[0].end = base + OMAP_I2C_SIZE;
res[1].start = irq;
}
omap_i2c_mux_pins(bus_id);
return platform_device_register(pdev);
}
arch/arm/plat-omap/mcbsp.c
View file @ 0eccf60b
......@@ -201,6 +201,14 @@ static int omap_mcbsp_check(unsigned int id)
static void omap_mcbsp_dsp_request(void)
{
if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
int ret;
ret = omap_dsp_request_mem();
if (ret < 0) {
printk(KERN_ERR "Could not get dsp memory: %i\n", ret);
return;
}
clk_enable(mcbsp_dsp_ck);
clk_enable(mcbsp_api_ck);
......@@ -219,6 +227,7 @@ static void omap_mcbsp_dsp_request(void)
static void omap_mcbsp_dsp_free(void)
{
if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
omap_dsp_release_mem();
clk_disable(mcbsp_dspxor_ck);
clk_disable(mcbsp_dsp_ck);
clk_disable(mcbsp_api_ck);
......@@ -1024,6 +1033,8 @@ EXPORT_SYMBOL(omap_mcbsp_set_io_type);
EXPORT_SYMBOL(omap_mcbsp_free);
EXPORT_SYMBOL(omap_mcbsp_start);
EXPORT_SYMBOL(omap_mcbsp_stop);
EXPORT_SYMBOL(omap_mcbsp_pollread);
EXPORT_SYMBOL(omap_mcbsp_pollwrite);
EXPORT_SYMBOL(omap_mcbsp_xmit_word);
EXPORT_SYMBOL(omap_mcbsp_recv_word);
EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
......
include/asm-arm/arch-omap/board-apollon.h
View file @ 0eccf60b
......@@ -29,6 +29,8 @@
#ifndef __ASM_ARCH_OMAP_APOLLON_H
#define __ASM_ARCH_OMAP_APOLLON_H
extern void apollon_mmc_init(void);
/* Placeholder for APOLLON specific defines */
#define APOLLON_ETHR_GPIO_IRQ 74
......
include/asm-arm/arch-omap/board-h2.h
View file @ 0eccf60b
......@@ -34,5 +34,8 @@
/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
#define OMAP1610_ETHR_START 0x04000300
extern void h2_mmc_init(void);
extern void h2_mmc_slot_cover_handler(void *arg, int state);
#endif /* __ASM_ARCH_OMAP_H2_H */
include/asm-arm/arch-omap/board-h3.h
View file @ 0eccf60b
......@@ -36,5 +36,7 @@
#define NR_IRQS (MAXIRQNUM + 1)
extern void __init h3_mmc_init(void);
extern void h3_mmc_slot_cover_handler(void *arg, int state);
#endif /* __ASM_ARCH_OMAP_H3_H */
include/asm-arm/arch-omap/board-sx1.h
View file @ 0eccf60b
......@@ -41,6 +41,12 @@ int sx1_getkeylight(u8 *keylight);
int sx1_setmmipower(u8 onoff);
int sx1_setusbpower(u8 onoff);
int sx1_setmmcpower(u8 onoff);
int sx1_i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value);
int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value);
/* MMC prototypes */
extern void sx1_mmc_init(void);
extern void sx1_mmc_slot_cover_handler(void *arg, int state);
#endif /* __ASM_ARCH_SX1_I2C_CHIPS_H */
include/asm-arm/arch-omap/common.h
View file @ 0eccf60b
......@@ -27,10 +27,21 @@
#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
#define __ARCH_ARM_MACH_OMAP_COMMON_H
#ifdef CONFIG_I2C_OMAP
#include <linux/i2c.h>
#endif
struct sys_timer;
extern void omap_map_common_io(void);
extern struct sys_timer omap_timer;
extern void omap_serial_init(void);
#ifdef CONFIG_I2C_OMAP
extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
struct i2c_board_info const *info,
unsigned len);
#else
#define omap_register_i2c_bus(a, b, c, d) 0
#endif
#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
include/asm-arm/arch-omap/cpu.h
View file @ 0eccf60b
......@@ -28,7 +28,7 @@
extern unsigned int system_rev;
#define omap2_cpu_rev() ((system_rev >> 8) & 0x0f)
#define omap2_cpu_rev() ((system_rev >> 12) & 0x0f)
/*
* Test if multicore OMAP support is needed
......@@ -61,12 +61,33 @@ extern unsigned int system_rev;
# define OMAP_NAME omap16xx
# endif
#endif
#ifdef CONFIG_ARCH_OMAP24XX
#if (defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX))
# if (defined(OMAP_NAME) || defined(MULTI_OMAP1))
# error "OMAP1 and OMAP2 can't be selected at the same time"
# endif
#endif
#ifdef CONFIG_ARCH_OMAP2420
# ifdef OMAP_NAME
# undef MULTI_OMAP2
# define MULTI_OMAP2
# else
# define OMAP_NAME omap2420
# endif
#endif
#ifdef CONFIG_ARCH_OMAP2430
# ifdef OMAP_NAME
# undef MULTI_OMAP2
# define MULTI_OMAP2
# else
# define OMAP_NAME omap2430
# endif
#endif
#ifdef CONFIG_ARCH_OMAP3430
# ifdef OMAP_NAME
# undef MULTI_OMAP2
# define OMAP_NAME omap24xx
# define MULTI_OMAP2
# else
# define OMAP_NAME omap3430
# endif
#endif
......@@ -79,8 +100,9 @@ extern unsigned int system_rev;
* cpu_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430
* cpu_is_omap242x(): True for OMAP2420, OMAP2422, OMAP2423
* cpu_is_omap243x(): True for OMAP2430
* cpu_is_omap343x(): True for OMAP3430
*/
#define GET_OMAP_CLASS (system_rev & 0xff)
#define GET_OMAP_CLASS ((system_rev >> 24) & 0xff)
#define IS_OMAP_CLASS(class, id) \
static inline int is_omap ##class (void) \
......@@ -100,9 +122,11 @@ IS_OMAP_CLASS(7xx, 0x07)
IS_OMAP_CLASS(15xx, 0x15)
IS_OMAP_CLASS(16xx, 0x16)
IS_OMAP_CLASS(24xx, 0x24)
IS_OMAP_CLASS(34xx, 0x34)
IS_OMAP_SUBCLASS(242x, 0x242)
IS_OMAP_SUBCLASS(243x, 0x243)
IS_OMAP_SUBCLASS(343x, 0x343)
#define cpu_is_omap7xx() 0
#define cpu_is_omap15xx() 0
......@@ -110,6 +134,8 @@ IS_OMAP_SUBCLASS(243x, 0x243)
#define cpu_is_omap24xx() 0
#define cpu_is_omap242x() 0
#define cpu_is_omap243x() 0
#define cpu_is_omap34xx() 0
#define cpu_is_omap343x() 0
#if defined(MULTI_OMAP1)
# if defined(CONFIG_ARCH_OMAP730)
......@@ -137,14 +163,44 @@ IS_OMAP_SUBCLASS(243x, 0x243)
# undef cpu_is_omap16xx
# define cpu_is_omap16xx() 1
# endif
#endif
#if defined(MULTI_OMAP2)
# if defined(CONFIG_ARCH_OMAP24XX)
# undef cpu_is_omap24xx
# undef cpu_is_omap242x
# undef cpu_is_omap243x
# define cpu_is_omap24xx() 1
# define cpu_is_omap24xx() is_omap24xx()
# define cpu_is_omap242x() is_omap242x()
# define cpu_is_omap243x() is_omap243x()
# endif
# if defined(CONFIG_ARCH_OMAP34XX)
# undef cpu_is_omap34xx
# undef cpu_is_omap343x
# define cpu_is_omap34xx() is_omap34xx()
# define cpu_is_omap343x() is_omap343x()
# endif
#else
# if defined(CONFIG_ARCH_OMAP24XX)
# undef cpu_is_omap24xx
# define cpu_is_omap24xx() 1
# endif
# if defined(CONFIG_ARCH_OMAP2420)
# undef cpu_is_omap242x
# define cpu_is_omap242x() 1
# endif
# if defined(CONFIG_ARCH_OMAP2430)
# undef cpu_is_omap243x
# define cpu_is_omap243x() 1
# endif
# if defined(CONFIG_ARCH_OMAP34XX)
# undef cpu_is_omap34xx
# define cpu_is_omap34xx() 1
# endif
# if defined(CONFIG_ARCH_OMAP3430)
# undef cpu_is_omap343x
# define cpu_is_omap343x() 1
# endif
#endif
/*
......@@ -162,6 +218,7 @@ IS_OMAP_SUBCLASS(243x, 0x243)
* cpu_is_omap2422(): True for OMAP2422
* cpu_is_omap2423(): True for OMAP2423
* cpu_is_omap2430(): True for OMAP2430
* cpu_is_omap3430(): True for OMAP3430
*/
#define GET_OMAP_TYPE ((system_rev >> 16) & 0xffff)
......@@ -183,6 +240,7 @@ IS_OMAP_TYPE(2420, 0x2420)
IS_OMAP_TYPE(2422, 0x2422)
IS_OMAP_TYPE(2423, 0x2423)
IS_OMAP_TYPE(2430, 0x2430)
IS_OMAP_TYPE(3430, 0x3430)
#define cpu_is_omap310() 0
#define cpu_is_omap730() 0
......@@ -196,6 +254,7 @@ IS_OMAP_TYPE(2430, 0x2430)
#define cpu_is_omap2422() 0
#define cpu_is_omap2423() 0
#define cpu_is_omap2430() 0
#define cpu_is_omap3430() 0
#if defined(MULTI_OMAP1)
# if defined(CONFIG_ARCH_OMAP730)
......@@ -244,9 +303,65 @@ IS_OMAP_TYPE(2430, 0x2430)
# define cpu_is_omap2430() is_omap2430()
#endif
#if defined(CONFIG_ARCH_OMAP34XX)
# undef cpu_is_omap3430
# define cpu_is_omap3430() is_omap3430()
#endif
/* Macros to detect if we have OMAP1 or OMAP2 */
#define cpu_class_is_omap1() (cpu_is_omap730() || cpu_is_omap15xx() || \
cpu_is_omap16xx())
#define cpu_class_is_omap2() cpu_is_omap24xx()
#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx())
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
/*
* Macros to detect silicon revision of OMAP2/3 processors.
* is_sil_rev_greater_than: true if passed cpu type & its rev is greater.
* is_sil_rev_lesser_than: true if passed cpu type & its rev is lesser.
* is_sil_rev_equal_to: true if passed cpu type & its rev is equal.
* get_sil_rev: return the silicon rev value.
*/
#define get_sil_omap_type(rev) ((rev & 0xffff0000) >> 16)
#define get_sil_revision(rev) ((rev & 0x0000f000) >> 12)
#define is_sil_rev_greater_than(rev) \
((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \
(get_sil_revision(system_rev) > get_sil_revision(rev)))
#define is_sil_rev_less_than(rev) \
((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \
(get_sil_revision(system_rev) < get_sil_revision(rev)))
#define is_sil_rev_equal_to(rev) \
((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \
(get_sil_revision(system_rev) == get_sil_revision(rev)))
#define get_sil_rev() \
get_sil_revision(system_rev)
/* Various silicon macros defined here */
#define OMAP2420_REV_ES1_0 0x24200000
#define OMAP2420_REV_ES2_0 0x24201000
#define OMAP2430_REV_ES1_0 0x24300000
#define OMAP3430_REV_ES1_0 0x34300000
#define OMAP3430_REV_ES2_0 0x34301000
/*
* Macro to detect device type i.e. EMU/HS/TST/GP/BAD
*/
#define DEVICE_TYPE_TEST 0
#define DEVICE_TYPE_EMU 1
#define DEVICE_TYPE_SEC 2
#define DEVICE_TYPE_GP 3
#define DEVICE_TYPE_BAD 4
#define get_device_type() ((system_rev & 0x700) >> 8)
#define is_device_type_test() (get_device_type() == DEVICE_TYPE_TEST)
#define is_device_type_emu() (get_device_type() == DEVICE_TYPE_EMU)
#define is_device_type_sec() (get_device_type() == DEVICE_TYPE_SEC)
#define is_device_type_gp() (get_device_type() == DEVICE_TYPE_GP)
#define is_device_type_bad() (get_device_type() == DEVICE_TYPE_BAD)
#endif
#endif
include/asm-arm/arch-omap/dma.h
View file @ 0eccf60b
......@@ -45,22 +45,28 @@
#define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0)
/* Hardware registers for omap2 */
#define OMAP24XX_DMA_BASE (L4_24XX_BASE + 0x56000)
#define OMAP_DMA4_REVISION (OMAP24XX_DMA_BASE + 0x00)
#define OMAP_DMA4_GCR_REG (OMAP24XX_DMA_BASE + 0x78)
#define OMAP_DMA4_IRQSTATUS_L0 (OMAP24XX_DMA_BASE + 0x08)
#define OMAP_DMA4_IRQSTATUS_L1 (OMAP24XX_DMA_BASE + 0x0c)
#define OMAP_DMA4_IRQSTATUS_L2 (OMAP24XX_DMA_BASE + 0x10)
#define OMAP_DMA4_IRQSTATUS_L3 (OMAP24XX_DMA_BASE + 0x14)
#define OMAP_DMA4_IRQENABLE_L0 (OMAP24XX_DMA_BASE + 0x18)
#define OMAP_DMA4_IRQENABLE_L1 (OMAP24XX_DMA_BASE + 0x1c)
#define OMAP_DMA4_IRQENABLE_L2 (OMAP24XX_DMA_BASE + 0x20)
#define OMAP_DMA4_IRQENABLE_L3 (OMAP24XX_DMA_BASE + 0x24)
#define OMAP_DMA4_SYSSTATUS (OMAP24XX_DMA_BASE + 0x28)
#define OMAP_DMA4_CAPS_0 (OMAP24XX_DMA_BASE + 0x64)
#define OMAP_DMA4_CAPS_2 (OMAP24XX_DMA_BASE + 0x6c)
#define OMAP_DMA4_CAPS_3 (OMAP24XX_DMA_BASE + 0x70)
#define OMAP_DMA4_CAPS_4 (OMAP24XX_DMA_BASE + 0x74)
#if defined(CONFIG_ARCH_OMAP3)
#define OMAP_DMA4_BASE (L4_34XX_BASE + 0x56000)
#else /* CONFIG_ARCH_OMAP2 */
#define OMAP_DMA4_BASE (L4_24XX_BASE + 0x56000)
#endif
#define OMAP_DMA4_REVISION (OMAP_DMA4_BASE + 0x00)
#define OMAP_DMA4_GCR_REG (OMAP_DMA4_BASE + 0x78)
#define OMAP_DMA4_IRQSTATUS_L0 (OMAP_DMA4_BASE + 0x08)
#define OMAP_DMA4_IRQSTATUS_L1 (OMAP_DMA4_BASE + 0x0c)
#define OMAP_DMA4_IRQSTATUS_L2 (OMAP_DMA4_BASE + 0x10)
#define OMAP_DMA4_IRQSTATUS_L3 (OMAP_DMA4_BASE + 0x14)
#define OMAP_DMA4_IRQENABLE_L0 (OMAP_DMA4_BASE + 0x18)
#define OMAP_DMA4_IRQENABLE_L1 (OMAP_DMA4_BASE + 0x1c)
#define OMAP_DMA4_IRQENABLE_L2 (OMAP_DMA4_BASE + 0x20)
#define OMAP_DMA4_IRQENABLE_L3 (OMAP_DMA4_BASE + 0x24)
#define OMAP_DMA4_SYSSTATUS (OMAP_DMA4_BASE + 0x28)
#define OMAP_DMA4_OCP_SYSCONFIG (OMAP_DMA4_BASE + 0x2c)
#define OMAP_DMA4_CAPS_0 (OMAP_DMA4_BASE + 0x64)
#define OMAP_DMA4_CAPS_2 (OMAP_DMA4_BASE + 0x6c)
#define OMAP_DMA4_CAPS_3 (OMAP_DMA4_BASE + 0x70)
#define OMAP_DMA4_CAPS_4 (OMAP_DMA4_BASE + 0x74)
#ifdef CONFIG_ARCH_OMAP1
......@@ -86,19 +92,19 @@
#define OMAP_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
/* Common channel specific registers for omap2 */
#define OMAP_DMA_CCR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x80)
#define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x84)
#define OMAP_DMA_CICR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x88)
#define OMAP_DMA_CSR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x8c)
#define OMAP_DMA_CSDP_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x90)
#define OMAP_DMA_CEN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x94)
#define OMAP_DMA_CFN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x98)
#define OMAP_DMA_CSEI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa4)
#define OMAP_DMA_CSFI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa8)
#define OMAP_DMA_CDEI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xac)
#define OMAP_DMA_CDFI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb0)
#define OMAP_DMA_CSAC_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb4)
#define OMAP_DMA_CDAC_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb8)
#define OMAP_DMA_CCR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x80)
#define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x84)
#define OMAP_DMA_CICR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x88)
#define OMAP_DMA_CSR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x8c)
#define OMAP_DMA_CSDP_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x90)
#define OMAP_DMA_CEN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x94)
#define OMAP_DMA_CFN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x98)
#define OMAP_DMA_CSEI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa4)
#define OMAP_DMA_CSFI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa8)
#define OMAP_DMA_CDEI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xac)
#define OMAP_DMA_CDFI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb0)
#define OMAP_DMA_CSAC_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb4)
#define OMAP_DMA_CDAC_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb8)
#endif
......@@ -113,11 +119,11 @@
#define OMAP1_DMA_LCH_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
/* Channel specific registers only on omap2 */
#define OMAP2_DMA_CSSA_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x9c)
#define OMAP2_DMA_CDSA_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa0)
#define OMAP2_DMA_CCEN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xbc)
#define OMAP2_DMA_CCFN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc0)
#define OMAP2_DMA_COLOR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc4)
#define OMAP2_DMA_CSSA_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x9c)
#define OMAP2_DMA_CDSA_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa0)
#define OMAP2_DMA_CCEN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xbc)
#define OMAP2_DMA_CCFN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc0)
#define OMAP2_DMA_COLOR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc4)
/*----------------------------------------------------------------------------*/
......@@ -297,6 +303,10 @@
#define OMAP_DMA_SYNC_ELEMENT 0x00
#define OMAP_DMA_SYNC_FRAME 0x01
#define OMAP_DMA_SYNC_BLOCK 0x02
#define OMAP_DMA_SYNC_PACKET 0x03
#define OMAP_DMA_SRC_SYNC 0x01
#define OMAP_DMA_DST_SYNC 0x00
#define OMAP_DMA_PORT_EMIFF 0x00
#define OMAP_DMA_PORT_EMIFS 0x01
......@@ -310,6 +320,29 @@
#define OMAP_DMA_AMODE_SINGLE_IDX 0x02
#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03
#define DMA_DEFAULT_FIFO_DEPTH 0x10
#define DMA_DEFAULT_ARB_RATE 0x01
/* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
#define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */
#define DMA_THREAD_RESERVE_ONET (0x01 << 12)
#define DMA_THREAD_RESERVE_TWOT (0x02 << 12)
#define DMA_THREAD_RESERVE_THREET (0x03 << 12)
#define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */
#define DMA_THREAD_FIFO_75 (0x01 << 14)
#define DMA_THREAD_FIFO_25 (0x02 << 14)
#define DMA_THREAD_FIFO_50 (0x03 << 14)
/* Chaining modes*/
#ifndef CONFIG_ARCH_OMAP1
#define OMAP_DMA_STATIC_CHAIN 0x1
#define OMAP_DMA_DYNAMIC_CHAIN 0x2
#define OMAP_DMA_CHAIN_ACTIVE 0x1
#define OMAP_DMA_CHAIN_INACTIVE 0x0
#endif
#define DMA_CH_PRIO_HIGH 0x1
#define DMA_CH_PRIO_LOW 0x0 /* Def */
/* LCD DMA block numbers */
enum {
OMAP_LCD_DMA_B1_TOP,
......@@ -359,6 +392,13 @@ struct omap_dma_channel_params {
int src_or_dst_synch; /* source synch(1) or destination synch(0) */
int ie; /* interrupt enabled */
unsigned char read_prio;/* read priority */
unsigned char write_prio;/* write priority */
#ifndef CONFIG_ARCH_OMAP1
enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
#endif
};
......@@ -409,6 +449,33 @@ extern dma_addr_t omap_get_dma_dst_pos(int lch);
extern int omap_get_dma_src_addr_counter(int lch);
extern void omap_clear_dma(int lch);
extern int omap_dma_running(void);
extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
int tparams);
extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
unsigned char write_prio);
/* Chaining APIs */
#ifndef CONFIG_ARCH_OMAP1
extern int omap_request_dma_chain(int dev_id, const char *dev_name,
void (*callback) (int chain_id, u16 ch_status,
void *data),
int *chain_id, int no_of_chans,
int chain_mode,
struct omap_dma_channel_params params);
extern int omap_free_dma_chain(int chain_id);
extern int omap_dma_chain_a_transfer(int chain_id, int src_start,
int dest_start, int elem_count,
int frame_count, void *callbk_data);
extern int omap_start_dma_chain_transfers(int chain_id);
extern int omap_stop_dma_chain_transfers(int chain_id);
extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi);
extern int omap_get_dma_chain_dst_pos(int chain_id);
extern int omap_get_dma_chain_src_pos(int chain_id);
extern int omap_modify_dma_chain_params(int chain_id,
struct omap_dma_channel_params params);
extern int omap_dma_chain_status(int chain_id);
#endif
/* LCD DMA functions */
extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
......
include/asm-arm/arch-omap/gpio.h
View file @ 0eccf60b
......@@ -62,6 +62,8 @@
#define OMAP_MPUIO_LATCH 0x34
#endif
#define OMAP34XX_NR_GPIOS 6
#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr))
#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES)
......@@ -75,6 +77,8 @@ extern void omap_free_gpio(int gpio);
extern void omap_set_gpio_direction(int gpio, int is_input);
extern void omap_set_gpio_dataout(int gpio, int enable);
extern int omap_get_gpio_datain(int gpio);
extern void omap_set_gpio_debounce(int gpio, int enable);
extern void omap_set_gpio_debounce_time(int gpio, int enable);
/*-------------------------------------------------------------------------*/
......
include/asm-arm/arch-omap/irqs.h
View file @ 0eccf60b
......@@ -263,6 +263,8 @@
#define INT_24XX_GPTIMER10 46
#define INT_24XX_GPTIMER11 47
#define INT_24XX_GPTIMER12 48
#define INT_24XX_I2C1_IRQ 56
#define INT_24XX_I2C2_IRQ 57
#define INT_24XX_MCBSP1_IRQ_TX 59
#define INT_24XX_MCBSP1_IRQ_RX 60
#define INT_24XX_MCBSP2_IRQ_TX 62
......
include/asm-arm/arch-omap/nand.h 0 → 100644
View file @ 0eccf60b
/*
* include/asm-arm/arch-omap/nand.h
*
* Copyright (C) 2006 Micron Technology Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/mtd/partitions.h>
struct omap_nand_platform_data {
unsigned int options;
int cs;
int gpio_irq;
struct mtd_partition *parts;
int nr_parts;
int (*nand_setup)(void __iomem *);
int (*dev_ready)(struct omap_nand_platform_data *);
int dma_channel;
void __iomem *gpmc_cs_baseaddr;
void __iomem *gpmc_baseaddr;
};
include/asm-arm/arch-orion/debug-macro.S
View file @ 0eccf60b
......@@ -8,9 +8,14 @@
* published by the Free Software Foundation.
*/
#include <asm/arch/orion.h>
.macro addruart,rx
mov \rx, #0xf1000000
orr \rx, \rx, #0x00012000
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
ldreq \rx, =ORION_REGS_PHYS_BASE
ldrne \rx, =ORION_REGS_VIRT_BASE
orr \rx, \rx, #0x00012000
.endm
#define UART_SHIFT 2
......
include/asm-arm/arch-orion/entry-macro.S
View file @ 0eccf60b
......@@ -3,8 +3,8 @@
*
* Low-level IRQ helper macros for Orion platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
......
include/asm-arm/arch-orion/hardware.h
View file @ 0eccf60b
......@@ -4,7 +4,6 @@
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __ASM_ARCH_HARDWARE_H__
......@@ -12,13 +11,11 @@
#include "orion.h"
#define PCI_MEMORY_VADDR ORION_PCI_SYS_MEM_BASE
#define PCI_IO_VADDR ORION_PCI_SYS_IO_BASE
#define pcibios_assign_all_busses() 1
#define pcibios_assign_all_busses() 1
#define PCIBIOS_MIN_IO 0x00001000
#define PCIBIOS_MIN_MEM 0x01000000
#define PCIMEM_BASE ORION_PCIE_MEM_PHYS_BASE
#define PCIBIOS_MIN_IO 0x1000
#define PCIBIOS_MIN_MEM 0x01000000
#define PCIMEM_BASE PCI_MEMORY_VADDR /* mem base for VGA */
#endif /* _ASM_ARCH_HARDWARE_H */
#endif
include/asm-arm/arch-orion/orion.h
View file @ 0eccf60b
......@@ -14,32 +14,40 @@
#ifndef __ASM_ARCH_ORION_H__
#define __ASM_ARCH_ORION_H__
/*******************************************************************************
/*****************************************************************************
* Orion Address Map
* Use the same mapping (1:1 virtual:physical) of internal registers and
* PCI system (PCI+PCIE) for all machines.
* Each machine defines the rest of its mapping (e.g. device bus flashes)
******************************************************************************/
#define ORION_REGS_BASE 0xf1000000
*
* virt phys size
* fdd00000 f1000000 1M on-chip peripheral registers
* fde00000 f2000000 1M PCIe I/O space
* fdf00000 f2100000 1M PCI I/O space
* fe000000 f0000000 16M PCIe WA space (Orion-NAS only)
****************************************************************************/
#define ORION_REGS_PHYS_BASE 0xf1000000
#define ORION_REGS_VIRT_BASE 0xfdd00000
#define ORION_REGS_SIZE SZ_1M
#define ORION_PCI_SYS_MEM_BASE 0xe0000000
#define ORION_PCIE_MEM_BASE ORION_PCI_SYS_MEM_BASE
#define ORION_PCIE_MEM_SIZE SZ_128M
#define ORION_PCI_MEM_BASE (ORION_PCIE_MEM_BASE + ORION_PCIE_MEM_SIZE)
#define ORION_PCI_MEM_SIZE SZ_128M
#define ORION_PCI_SYS_IO_BASE 0xf2000000
#define ORION_PCIE_IO_BASE ORION_PCI_SYS_IO_BASE
#define ORION_PCIE_IO_PHYS_BASE 0xf2000000
#define ORION_PCIE_IO_VIRT_BASE 0xfde00000
#define ORION_PCIE_IO_BUS_BASE 0x00000000
#define ORION_PCIE_IO_SIZE SZ_1M
#define ORION_PCIE_IO_REMAP (ORION_PCIE_IO_BASE - ORION_PCI_SYS_IO_BASE)
#define ORION_PCI_IO_BASE (ORION_PCIE_IO_BASE + ORION_PCIE_IO_SIZE)
#define ORION_PCI_IO_PHYS_BASE 0xf2100000
#define ORION_PCI_IO_VIRT_BASE 0xfdf00000
#define ORION_PCI_IO_BUS_BASE 0x00100000
#define ORION_PCI_IO_SIZE SZ_1M
#define ORION_PCI_IO_REMAP (ORION_PCI_IO_BASE - ORION_PCI_SYS_IO_BASE)
/* Relevant only for Orion-NAS */
#define ORION_PCIE_WA_BASE 0xf0000000
#define ORION_PCIE_WA_PHYS_BASE 0xf0000000
#define ORION_PCIE_WA_VIRT_BASE 0xfe000000
#define ORION_PCIE_WA_SIZE SZ_16M
#define ORION_PCIE_MEM_PHYS_BASE 0xe0000000
#define ORION_PCIE_MEM_SIZE SZ_128M
#define ORION_PCI_MEM_PHYS_BASE 0xe8000000
#define ORION_PCI_MEM_SIZE SZ_128M
/*******************************************************************************
* Supported Devices & Revisions
******************************************************************************/
......@@ -57,25 +65,42 @@
/*******************************************************************************
* Orion Registers Map
******************************************************************************/
#define ORION_DDR_REG_BASE (ORION_REGS_BASE | 0x00000)
#define ORION_DEV_BUS_REG_BASE (ORION_REGS_BASE | 0x10000)
#define ORION_BRIDGE_REG_BASE (ORION_REGS_BASE | 0x20000)
#define ORION_PCI_REG_BASE (ORION_REGS_BASE | 0x30000)
#define ORION_PCIE_REG_BASE (ORION_REGS_BASE | 0x40000)
#define ORION_USB0_REG_BASE (ORION_REGS_BASE | 0x50000)
#define ORION_ETH_REG_BASE (ORION_REGS_BASE | 0x70000)
#define ORION_SATA_REG_BASE (ORION_REGS_BASE | 0x80000)
#define ORION_USB1_REG_BASE (ORION_REGS_BASE | 0xa0000)
#define ORION_DDR_REG(x) (ORION_DDR_REG_BASE | (x))
#define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_REG_BASE | (x))
#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_REG_BASE | (x))
#define ORION_PCI_REG(x) (ORION_PCI_REG_BASE | (x))
#define ORION_PCIE_REG(x) (ORION_PCIE_REG_BASE | (x))
#define ORION_USB0_REG(x) (ORION_USB0_REG_BASE | (x))
#define ORION_USB1_REG(x) (ORION_USB1_REG_BASE | (x))
#define ORION_ETH_REG(x) (ORION_ETH_REG_BASE | (x))
#define ORION_SATA_REG(x) (ORION_SATA_REG_BASE | (x))
#define ORION_DDR_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x00000)
#define ORION_DDR_REG(x) (ORION_DDR_VIRT_BASE | (x))
#define ORION_DEV_BUS_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x10000)
#define ORION_DEV_BUS_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x10000)
#define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_VIRT_BASE | (x))
#define I2C_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x1000)
#define UART0_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2000)
#define UART0_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2000)
#define UART1_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2100)
#define UART1_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2100)
#define ORION_BRIDGE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x20000)
#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_VIRT_BASE | (x))
#define ORION_PCI_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x30000)
#define ORION_PCI_REG(x) (ORION_PCI_VIRT_BASE | (x))
#define ORION_PCIE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x40000)
#define ORION_PCIE_REG(x) (ORION_PCIE_VIRT_BASE | (x))
#define ORION_USB0_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x50000)
#define ORION_USB0_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x50000)
#define ORION_USB0_REG(x) (ORION_USB0_VIRT_BASE | (x))
#define ORION_ETH_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x70000)
#define ORION_ETH_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x70000)
#define ORION_ETH_REG(x) (ORION_ETH_VIRT_BASE | (x))
#define ORION_SATA_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x80000)
#define ORION_SATA_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x80000)
#define ORION_SATA_REG(x) (ORION_SATA_VIRT_BASE | (x))
#define ORION_USB1_PHYS_BASE (ORION_REGS_PHYS_BASE | 0xa0000)
#define ORION_USB1_VIRT_BASE (ORION_REGS_VIRT_BASE | 0xa0000)
#define ORION_USB1_REG(x) (ORION_USB1_VIRT_BASE | (x))
/*******************************************************************************
* Device Bus Registers
......@@ -100,9 +125,6 @@
#define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0)
#define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0)
#define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4)
#define I2C_BASE ORION_DEV_BUS_REG(0x1000)
#define UART0_BASE ORION_DEV_BUS_REG(0x2000)
#define UART1_BASE ORION_DEV_BUS_REG(0x2100)
#define GPIO_MAX 32
/***************************************************************************
......
include/asm-arm/arch-orion/uncompress.h
View file @ 0eccf60b
......@@ -10,8 +10,8 @@
#include <asm/arch/orion.h>
#define MV_UART_LSR ((volatile unsigned char *)(UART0_BASE + 0x14))
#define MV_UART_THR ((volatile unsigned char *)(UART0_BASE + 0x0))
#define MV_UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0))
#define MV_UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14))
#define LSR_THRE 0x20
......@@ -27,16 +27,6 @@ static void flush(void)
{
}
static void orion_early_putstr(const char *ptr)
{
char c;
while ((c = *ptr++) != '\0') {
if (c == '\n')
putc('\r');
putc(c);
}
}
/*
* nothing to do
*/
......
include/asm-arm/arch-orion/vmalloc.h
View file @ 0eccf60b
......@@ -2,4 +2,4 @@
* include/asm-arm/arch-orion/vmalloc.h
*/
#define VMALLOC_END 0xf0000000
#define VMALLOC_END 0xfd800000
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