Commit 0edd2d25 authored by Jani Nikula's avatar Jani Nikula

drm/i915: pass dev_priv explicitly to CURBASE

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the CURBASE register macro.
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/e552df69a4e6a3dbd562ba8c442d0219cda3bfd0.1715774156.git.jani.nikula@intel.comSigned-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 93160b2d
...@@ -296,7 +296,7 @@ static void i845_cursor_update_arm(struct intel_plane *plane, ...@@ -296,7 +296,7 @@ static void i845_cursor_update_arm(struct intel_plane *plane,
plane->cursor.size != size || plane->cursor.size != size ||
plane->cursor.cntl != cntl) { plane->cursor.cntl != cntl) {
intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), 0); intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), 0);
intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base); intel_de_write_fw(dev_priv, CURBASE(dev_priv, PIPE_A), base);
intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size); intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size);
intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), cntl); intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), cntl);
...@@ -648,14 +648,14 @@ static void i9xx_cursor_update_arm(struct intel_plane *plane, ...@@ -648,14 +648,14 @@ static void i9xx_cursor_update_arm(struct intel_plane *plane,
fbc_ctl); fbc_ctl);
intel_de_write_fw(dev_priv, CURCNTR(dev_priv, pipe), cntl); intel_de_write_fw(dev_priv, CURCNTR(dev_priv, pipe), cntl);
intel_de_write_fw(dev_priv, CURPOS(pipe), pos); intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
intel_de_write_fw(dev_priv, CURBASE(pipe), base); intel_de_write_fw(dev_priv, CURBASE(dev_priv, pipe), base);
plane->cursor.base = base; plane->cursor.base = base;
plane->cursor.size = fbc_ctl; plane->cursor.size = fbc_ctl;
plane->cursor.cntl = cntl; plane->cursor.cntl = cntl;
} else { } else {
intel_de_write_fw(dev_priv, CURPOS(pipe), pos); intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
intel_de_write_fw(dev_priv, CURBASE(pipe), base); intel_de_write_fw(dev_priv, CURBASE(dev_priv, pipe), base);
} }
} }
......
...@@ -67,7 +67,7 @@ ...@@ -67,7 +67,7 @@
#define _CURBPOS_IVB 0x71088 #define _CURBPOS_IVB 0x71088
#define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR) #define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR)
#define CURBASE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE) #define CURBASE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE)
#define CURPOS(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS) #define CURPOS(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS)
#define CURPOS_ERLY_TPT(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS_ERLY_TPT) #define CURPOS_ERLY_TPT(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS_ERLY_TPT)
#define CURSIZE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE) #define CURSIZE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE)
......
...@@ -373,7 +373,7 @@ int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu, ...@@ -373,7 +373,7 @@ int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,
gvt_dbg_core("alpha_plane=0x%x, alpha_force=0x%x\n", gvt_dbg_core("alpha_plane=0x%x, alpha_force=0x%x\n",
alpha_plane, alpha_force); alpha_plane, alpha_force);
plane->base = vgpu_vreg_t(vgpu, CURBASE(pipe)) & I915_GTT_PAGE_MASK; plane->base = vgpu_vreg_t(vgpu, CURBASE(dev_priv, pipe)) & I915_GTT_PAGE_MASK;
if (!vgpu_gmadr_is_valid(vgpu, plane->base)) if (!vgpu_gmadr_is_valid(vgpu, plane->base))
return -EINVAL; return -EINVAL;
......
...@@ -151,9 +151,9 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) ...@@ -151,9 +151,9 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(CURPOS(PIPE_A)); MMIO_D(CURPOS(PIPE_A));
MMIO_D(CURPOS(PIPE_B)); MMIO_D(CURPOS(PIPE_B));
MMIO_D(CURPOS(PIPE_C)); MMIO_D(CURPOS(PIPE_C));
MMIO_D(CURBASE(PIPE_A)); MMIO_D(CURBASE(dev_priv, PIPE_A));
MMIO_D(CURBASE(PIPE_B)); MMIO_D(CURBASE(dev_priv, PIPE_B));
MMIO_D(CURBASE(PIPE_C)); MMIO_D(CURBASE(dev_priv, PIPE_C));
MMIO_D(CUR_FBC_CTL(PIPE_A)); MMIO_D(CUR_FBC_CTL(PIPE_A));
MMIO_D(CUR_FBC_CTL(PIPE_B)); MMIO_D(CUR_FBC_CTL(PIPE_B));
MMIO_D(CUR_FBC_CTL(PIPE_C)); MMIO_D(CUR_FBC_CTL(PIPE_C));
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment