Commit 0fff1428 authored by Heiko Stuebner's avatar Heiko Stuebner

ARM: dts: rockchip: add rk3188 lcd controller nodes

Add the core display subsystem and vop nodes to rk3188.
Vop0 has a fully dedicated set of pins and only vop1 needs to
do pinctrl to have display output, so also add the necessary
pinctrl entries for it.
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
Reviewed-by Sandy Huang <hjc@rock-chips.com>
parent 5b394b2d
...@@ -56,6 +56,11 @@ cpu@3 { ...@@ -56,6 +56,11 @@ cpu@3 {
}; };
}; };
display-subsystem {
compatible = "rockchip,display-subsystem";
ports = <&vop0_out>, <&vop1_out>;
};
sram: sram@10080000 { sram: sram@10080000 {
compatible = "mmio-sram"; compatible = "mmio-sram";
reg = <0x10080000 0x8000>; reg = <0x10080000 0x8000>;
...@@ -69,6 +74,38 @@ smp-sram@0 { ...@@ -69,6 +74,38 @@ smp-sram@0 {
}; };
}; };
vop0: vop@1010c000 {
compatible = "rockchip,rk3188-vop";
reg = <0x1010c000 0x1000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
reset-names = "axi", "ahb", "dclk";
status = "disabled";
vop0_out: port {
#address-cells = <1>;
#size-cells = <0>;
};
};
vop1: vop@1010e000 {
compatible = "rockchip,rk3188-vop";
reg = <0x1010e000 0x1000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
reset-names = "axi", "ahb", "dclk";
status = "disabled";
vop1_out: port {
#address-cells = <1>;
#size-cells = <0>;
};
};
timer3: timer@2000e000 { timer3: timer@2000e000 {
compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
reg = <0x2000e000 0x20>; reg = <0x2000e000 0x20>;
...@@ -309,6 +346,51 @@ i2c4_xfer: i2c4-xfer { ...@@ -309,6 +346,51 @@ i2c4_xfer: i2c4-xfer {
}; };
}; };
lcdc1 {
lcdc1_dclk: lcdc1-dclk {
rockchip,pins = <2 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
};
lcdc1_den: lcdc1-den {
rockchip,pins = <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
};
lcdc1_hsync: lcdc1-hsync {
rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
};
lcdc1_vsync: lcdc1-vsync {
rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>;
};
lcdc1_rgb24: ldcd1-rgb24 {
rockchip,pins = <2 RK_PA0 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PA1 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PB2 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PC6 RK_FUNC_1 &pcfg_pull_none>,
<2 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
};
};
pwm0 { pwm0 {
pwm0_out: pwm0-out { pwm0_out: pwm0-out {
rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>; rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment