Commit 103c5e1b authored by Manivannan Sadhasivam's avatar Manivannan Sadhasivam Committed by Stephen Boyd

clk: actions: Add gate clock support

Add support for Actions Semi gate clock together with helper
functions to be used in composite clock.
Signed-off-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 3495e295
obj-$(CONFIG_CLK_ACTIONS) += clk-owl.o
clk-owl-y += owl-common.o
clk-owl-y += owl-gate.o
// SPDX-License-Identifier: GPL-2.0+
//
// OWL gate clock driver
//
// Copyright (c) 2014 Actions Semi Inc.
// Author: David Liu <liuwei@actions-semi.com>
//
// Copyright (c) 2018 Linaro Ltd.
// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include "owl-gate.h"
void owl_gate_set(const struct owl_clk_common *common,
const struct owl_gate_hw *gate_hw, bool enable)
{
int set = gate_hw->gate_flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
u32 reg;
set ^= enable;
regmap_read(common->regmap, gate_hw->reg, &reg);
if (set)
reg |= BIT(gate_hw->bit_idx);
else
reg &= ~BIT(gate_hw->bit_idx);
regmap_write(common->regmap, gate_hw->reg, reg);
}
static void owl_gate_disable(struct clk_hw *hw)
{
struct owl_gate *gate = hw_to_owl_gate(hw);
struct owl_clk_common *common = &gate->common;
owl_gate_set(common, &gate->gate_hw, false);
}
static int owl_gate_enable(struct clk_hw *hw)
{
struct owl_gate *gate = hw_to_owl_gate(hw);
struct owl_clk_common *common = &gate->common;
owl_gate_set(common, &gate->gate_hw, true);
return 0;
}
int owl_gate_clk_is_enabled(const struct owl_clk_common *common,
const struct owl_gate_hw *gate_hw)
{
u32 reg;
regmap_read(common->regmap, gate_hw->reg, &reg);
if (gate_hw->gate_flags & CLK_GATE_SET_TO_DISABLE)
reg ^= BIT(gate_hw->bit_idx);
return !!(reg & BIT(gate_hw->bit_idx));
}
static int owl_gate_is_enabled(struct clk_hw *hw)
{
struct owl_gate *gate = hw_to_owl_gate(hw);
struct owl_clk_common *common = &gate->common;
return owl_gate_clk_is_enabled(common, &gate->gate_hw);
}
const struct clk_ops owl_gate_ops = {
.disable = owl_gate_disable,
.enable = owl_gate_enable,
.is_enabled = owl_gate_is_enabled,
};
// SPDX-License-Identifier: GPL-2.0+
//
// OWL gate clock driver
//
// Copyright (c) 2014 Actions Semi Inc.
// Author: David Liu <liuwei@actions-semi.com>
//
// Copyright (c) 2018 Linaro Ltd.
// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
#ifndef _OWL_GATE_H_
#define _OWL_GATE_H_
#include "owl-common.h"
struct owl_gate_hw {
u32 reg;
u8 bit_idx;
u8 gate_flags;
};
struct owl_gate {
struct owl_gate_hw gate_hw;
struct owl_clk_common common;
};
#define OWL_GATE_HW(_reg, _bit_idx, _gate_flags) \
{ \
.reg = _reg, \
.bit_idx = _bit_idx, \
.gate_flags = _gate_flags, \
}
#define OWL_GATE(_struct, _name, _parent, _reg, \
_bit_idx, _gate_flags, _flags) \
struct owl_gate _struct = { \
.gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \
.common = { \
.regmap = NULL, \
.hw.init = CLK_HW_INIT(_name, \
_parent, \
&owl_gate_ops, \
_flags), \
} \
} \
#define OWL_GATE_NO_PARENT(_struct, _name, _reg, \
_bit_idx, _gate_flags, _flags) \
struct owl_gate _struct = { \
.gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \
.common = { \
.regmap = NULL, \
.hw.init = CLK_HW_INIT_NO_PARENT(_name, \
&owl_gate_ops, \
_flags), \
}, \
} \
static inline struct owl_gate *hw_to_owl_gate(const struct clk_hw *hw)
{
struct owl_clk_common *common = hw_to_owl_clk_common(hw);
return container_of(common, struct owl_gate, common);
}
void owl_gate_set(const struct owl_clk_common *common,
const struct owl_gate_hw *gate_hw, bool enable);
int owl_gate_clk_is_enabled(const struct owl_clk_common *common,
const struct owl_gate_hw *gate_hw);
extern const struct clk_ops owl_gate_ops;
#endif /* _OWL_GATE_H_ */
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