Commit 1045d065 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Simon Horman

ARM: shmobile: r8a7794 dtsi: Change to using clock-indices

With the addition of clock-indices in commit 8e33f91a ("clk:
shmobile: clk-mstp: change to using clock-indices"), we can change the
DTSes to use the generic property instead of the deprecated
vendor-specific property.
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: default avatarKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent cb0bf851
...@@ -455,7 +455,7 @@ mstp0_clks: mstp0_clks@e6150130 { ...@@ -455,7 +455,7 @@ mstp0_clks: mstp0_clks@e6150130 {
reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
clocks = <&mp_clk>; clocks = <&mp_clk>;
#clock-cells = <1>; #clock-cells = <1>;
renesas,clock-indices = <R8A7794_CLK_MSIOF0>; clock-indices = <R8A7794_CLK_MSIOF0>;
clock-output-names = "msiof0"; clock-output-names = "msiof0";
}; };
mstp1_clks: mstp1_clks@e6150134 { mstp1_clks: mstp1_clks@e6150134 {
...@@ -465,7 +465,7 @@ mstp1_clks: mstp1_clks@e6150134 { ...@@ -465,7 +465,7 @@ mstp1_clks: mstp1_clks@e6150134 {
<&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
<&zs_clk>, <&zs_clk>; <&zs_clk>, <&zs_clk>;
#clock-cells = <1>; #clock-cells = <1>;
renesas,clock-indices = < clock-indices = <
R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
...@@ -481,7 +481,7 @@ mstp2_clks: mstp2_clks@e6150138 { ...@@ -481,7 +481,7 @@ mstp2_clks: mstp2_clks@e6150138 {
clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
<&mp_clk>, <&mp_clk>, <&mp_clk>; <&mp_clk>, <&mp_clk>, <&mp_clk>;
#clock-cells = <1>; #clock-cells = <1>;
renesas,clock-indices = < clock-indices = <
R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0
R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1
R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2
...@@ -495,7 +495,7 @@ mstp3_clks: mstp3_clks@e615013c { ...@@ -495,7 +495,7 @@ mstp3_clks: mstp3_clks@e615013c {
reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
clocks = <&rclk_clk>; clocks = <&rclk_clk>;
#clock-cells = <1>; #clock-cells = <1>;
renesas,clock-indices = < clock-indices = <
R8A7794_CLK_CMT1 R8A7794_CLK_CMT1
>; >;
clock-output-names = clock-output-names =
...@@ -507,7 +507,7 @@ mstp7_clks: mstp7_clks@e615014c { ...@@ -507,7 +507,7 @@ mstp7_clks: mstp7_clks@e615014c {
clocks = <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, clocks = <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
<&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>; <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
#clock-cells = <1>; #clock-cells = <1>;
renesas,clock-indices = < clock-indices = <
R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5
R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0
R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1
...@@ -522,7 +522,7 @@ mstp8_clks: mstp8_clks@e6150990 { ...@@ -522,7 +522,7 @@ mstp8_clks: mstp8_clks@e6150990 {
reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
clocks = <&zg_clk>, <&zg_clk>, <&p_clk>; clocks = <&zg_clk>, <&zg_clk>, <&p_clk>;
#clock-cells = <1>; #clock-cells = <1>;
renesas,clock-indices = < clock-indices = <
R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER
>; >;
clock-output-names = clock-output-names =
...@@ -533,7 +533,7 @@ mstp11_clks: mstp11_clks@e615099c { ...@@ -533,7 +533,7 @@ mstp11_clks: mstp11_clks@e615099c {
reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
#clock-cells = <1>; #clock-cells = <1>;
renesas,clock-indices = < clock-indices = <
R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5
>; >;
clock-output-names = "scifa3", "scifa4", "scifa5"; clock-output-names = "scifa3", "scifa4", "scifa5";
......
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