Commit 1075735e authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher

drm/amd/display: Fix 300Hz Freesync bug

Needed to reprogram vblank_start in dml properly in order to get the
correct dlg params to program VTG.
Signed-off-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Reviewed-by: default avatarMartin Leung <Martin.Leung@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 93a8955b
...@@ -287,7 +287,6 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc, ...@@ -287,7 +287,6 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc,
struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
if (pipe->stream == stream && pipe->stream_res.tg) { if (pipe->stream == stream && pipe->stream_res.tg) {
pipe->stream->adjust = *adjust;
dc->hwss.set_drr(&pipe, dc->hwss.set_drr(&pipe,
1, 1,
adjust->v_total_min, adjust->v_total_min,
......
...@@ -1883,12 +1883,14 @@ int dcn20_populate_dml_pipes_from_context( ...@@ -1883,12 +1883,14 @@ int dcn20_populate_dml_pipes_from_context(
for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing; struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
unsigned int v_total; unsigned int v_total;
unsigned int front_porch;
int output_bpc; int output_bpc;
if (!res_ctx->pipe_ctx[i].stream) if (!res_ctx->pipe_ctx[i].stream)
continue; continue;
v_total = timing->v_total; v_total = timing->v_total;
front_porch = timing->v_front_porch;
/* todo: /* todo:
pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0; pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;
pipes[pipe_cnt].pipe.src.dcc = 0; pipes[pipe_cnt].pipe.src.dcc = 0;
...@@ -1915,7 +1917,7 @@ int dcn20_populate_dml_pipes_from_context( ...@@ -1915,7 +1917,7 @@ int dcn20_populate_dml_pipes_from_context(
- timing->h_addressable - timing->h_addressable
- timing->h_border_left - timing->h_border_left
- timing->h_border_right; - timing->h_border_right;
pipes[pipe_cnt].pipe.dest.vblank_start = v_total - timing->v_front_porch; pipes[pipe_cnt].pipe.dest.vblank_start = v_total - front_porch;
pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
- timing->v_addressable - timing->v_addressable
- timing->v_border_top - timing->v_border_top
......
...@@ -812,11 +812,12 @@ void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync, ...@@ -812,11 +812,12 @@ void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
2 * in_out_vrr->min_refresh_in_uhz) 2 * in_out_vrr->min_refresh_in_uhz)
in_out_vrr->btr.btr_enabled = false; in_out_vrr->btr.btr_enabled = false;
in_out_vrr->fixed.fixed_active = false;
in_out_vrr->btr.btr_active = false; in_out_vrr->btr.btr_active = false;
in_out_vrr->btr.inserted_duration_in_us = 0; in_out_vrr->btr.inserted_duration_in_us = 0;
in_out_vrr->btr.frames_to_insert = 0; in_out_vrr->btr.frames_to_insert = 0;
in_out_vrr->btr.frame_counter = 0; in_out_vrr->btr.frame_counter = 0;
in_out_vrr->fixed.fixed_active = false;
in_out_vrr->fixed.target_refresh_in_uhz = 0;
in_out_vrr->btr.mid_point_in_us = in_out_vrr->btr.mid_point_in_us =
(in_out_vrr->min_duration_in_us + (in_out_vrr->min_duration_in_us +
......
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