Commit 10b00466 authored by Anish Bhatt's avatar Anish Bhatt Committed by David S. Miller

cxgb4: IEEE fixes for DCBx state machine

* Changes required due to 16eecd9b ("dcbnl : Fix misleading
  dcb_app->priority explanation")
* Driver was previously not aware of what DCBx version was negotiated by
  firmware, this could lead to DCB app table  in kernel or in firmware being
  populated wrong  since IEEE/CEE used different formats made clear by above
  mentioned commit
* Driver was missing a couple of state transitions that could be caused
  by other drivers that use chelsio hardware, resulting in incorrect behaviour
  (the change that addresses this also flips the state machine to switch on
   state instead of transition, hope this is okay in current window)
* Prio queue info & tsa is no longer thrown away

v2: Print DCBx state transition messages only when debug is enabled
Signed-off-by: default avatarAnish Bhatt <anish@chelsio.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent a1f7d81b
...@@ -522,6 +522,9 @@ struct sge_txq { ...@@ -522,6 +522,9 @@ struct sge_txq {
struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */ struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
struct sge_txq q; struct sge_txq q;
struct netdev_queue *txq; /* associated netdev TX queue */ struct netdev_queue *txq; /* associated netdev TX queue */
#ifdef CONFIG_CHELSIO_T4_DCB
u8 dcb_prio; /* DCB Priority bound to queue */
#endif
unsigned long tso; /* # of TSO requests */ unsigned long tso; /* # of TSO requests */
unsigned long tx_cso; /* # of Tx checksum offloads */ unsigned long tx_cso; /* # of Tx checksum offloads */
unsigned long vlan_ins; /* # of Tx VLAN insertions */ unsigned long vlan_ins; /* # of Tx VLAN insertions */
......
...@@ -63,6 +63,13 @@ ...@@ -63,6 +63,13 @@
#define INIT_PORT_DCB_WRITE_CMD(__pcmd, __port) \ #define INIT_PORT_DCB_WRITE_CMD(__pcmd, __port) \
INIT_PORT_DCB_CMD(__pcmd, __port, EXEC, FW_PORT_ACTION_L2_DCB_CFG) INIT_PORT_DCB_CMD(__pcmd, __port, EXEC, FW_PORT_ACTION_L2_DCB_CFG)
#define IEEE_FAUX_SYNC(__dev, __dcb) \
do { \
if ((__dcb)->dcb_version == FW_PORT_DCB_VER_IEEE) \
cxgb4_dcb_state_fsm((__dev), \
CXGB4_DCB_STATE_FW_ALLSYNCED); \
} while (0)
/* States we can be in for a port's Data Center Bridging. /* States we can be in for a port's Data Center Bridging.
*/ */
enum cxgb4_dcb_state { enum cxgb4_dcb_state {
...@@ -108,11 +115,13 @@ struct port_dcb_info { ...@@ -108,11 +115,13 @@ struct port_dcb_info {
* Native Endian format). * Native Endian format).
*/ */
u32 pgid; /* Priority Group[0..7] */ u32 pgid; /* Priority Group[0..7] */
u8 dcb_version; /* Running DCBx version */
u8 pfcen; /* Priority Flow Control[0..7] */ u8 pfcen; /* Priority Flow Control[0..7] */
u8 pg_num_tcs_supported; /* max PG Traffic Classes */ u8 pg_num_tcs_supported; /* max PG Traffic Classes */
u8 pfc_num_tcs_supported; /* max PFC Traffic Classes */ u8 pfc_num_tcs_supported; /* max PFC Traffic Classes */
u8 pgrate[8]; /* Priority Group Rate[0..7] */ u8 pgrate[8]; /* Priority Group Rate[0..7] */
u8 priorate[8]; /* Priority Rate[0..7] */ u8 priorate[8]; /* Priority Rate[0..7] */
u8 tsa[8]; /* TSA Algorithm[0..7] */
struct app_priority { /* Application Information */ struct app_priority { /* Application Information */
u8 user_prio_map; /* Priority Map bitfield */ u8 user_prio_map; /* Priority Map bitfield */
u8 sel_field; /* Protocol ID interpretation */ u8 sel_field; /* Protocol ID interpretation */
...@@ -121,6 +130,7 @@ struct port_dcb_info { ...@@ -121,6 +130,7 @@ struct port_dcb_info {
}; };
void cxgb4_dcb_state_init(struct net_device *); void cxgb4_dcb_state_init(struct net_device *);
void cxgb4_dcb_version_init(struct net_device *);
void cxgb4_dcb_state_fsm(struct net_device *, enum cxgb4_dcb_state_input); void cxgb4_dcb_state_fsm(struct net_device *, enum cxgb4_dcb_state_input);
void cxgb4_dcb_handle_fw_update(struct adapter *, const struct fw_port_cmd *); void cxgb4_dcb_handle_fw_update(struct adapter *, const struct fw_port_cmd *);
void cxgb4_dcb_set_caps(struct adapter *, const struct fw_port_cmd *); void cxgb4_dcb_set_caps(struct adapter *, const struct fw_port_cmd *);
......
...@@ -522,6 +522,8 @@ static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable) ...@@ -522,6 +522,8 @@ static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
dev_err(adap->pdev_dev, dev_err(adap->pdev_dev,
"Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n", "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
enable ? "set" : "unset", pi->port_id, i, -err); enable ? "set" : "unset", pi->port_id, i, -err);
else
txq->dcb_prio = value;
} }
} }
#endif /* CONFIG_CHELSIO_T4_DCB */ #endif /* CONFIG_CHELSIO_T4_DCB */
......
...@@ -1629,6 +1629,14 @@ enum fw_port_l2cfg_ctlbf { ...@@ -1629,6 +1629,14 @@ enum fw_port_l2cfg_ctlbf {
FW_PORT_L2_CTLBF_TXIPG = 0x20 FW_PORT_L2_CTLBF_TXIPG = 0x20
}; };
enum fw_port_dcb_versions {
FW_PORT_DCB_VER_UNKNOWN,
FW_PORT_DCB_VER_CEE1D0,
FW_PORT_DCB_VER_CEE1D01,
FW_PORT_DCB_VER_IEEE,
FW_PORT_DCB_VER_AUTO = 7
};
enum fw_port_dcb_cfg { enum fw_port_dcb_cfg {
FW_PORT_DCB_CFG_PG = 0x01, FW_PORT_DCB_CFG_PG = 0x01,
FW_PORT_DCB_CFG_PFC = 0x02, FW_PORT_DCB_CFG_PFC = 0x02,
...@@ -1709,6 +1717,7 @@ struct fw_port_cmd { ...@@ -1709,6 +1717,7 @@ struct fw_port_cmd {
__u8 r10_lo[5]; __u8 r10_lo[5];
__u8 num_tcs_supported; __u8 num_tcs_supported;
__u8 pgrate[8]; __u8 pgrate[8];
__u8 tsa[8];
} pgrate; } pgrate;
struct fw_port_dcb_priorate { struct fw_port_dcb_priorate {
__u8 type; __u8 type;
...@@ -1735,7 +1744,7 @@ struct fw_port_cmd { ...@@ -1735,7 +1744,7 @@ struct fw_port_cmd {
struct fw_port_dcb_control { struct fw_port_dcb_control {
__u8 type; __u8 type;
__u8 all_syncd_pkd; __u8 all_syncd_pkd;
__be16 pfc_state_to_app_state; __be16 dcb_version_to_app_state;
__be32 r11; __be32 r11;
__be64 r12; __be64 r12;
} control; } control;
...@@ -1778,6 +1787,7 @@ struct fw_port_cmd { ...@@ -1778,6 +1787,7 @@ struct fw_port_cmd {
#define FW_PORT_CMD_DCBXDIS (1U << 7) #define FW_PORT_CMD_DCBXDIS (1U << 7)
#define FW_PORT_CMD_APPLY (1U << 7) #define FW_PORT_CMD_APPLY (1U << 7)
#define FW_PORT_CMD_ALL_SYNCD (1U << 7) #define FW_PORT_CMD_ALL_SYNCD (1U << 7)
#define FW_PORT_CMD_DCB_VERSION_GET(x) (((x) >> 8) & 0xf)
#define FW_PORT_CMD_PPPEN(x) ((x) << 31) #define FW_PORT_CMD_PPPEN(x) ((x) << 31)
#define FW_PORT_CMD_TPSRC(x) ((x) << 28) #define FW_PORT_CMD_TPSRC(x) ((x) << 28)
......
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