staging: rtl8188eu: remove cut_mask field from wl_pwr_cfg

We're no longer matching power transitions and commands against a
power cut version mask.

The cut_mask field from struct wl_pwr_cfg can be removed. It was set to
PWR_CUT_ALL_MSK for all remaining commands.
Signed-off-by: Martin Kaiser <martin@kaiser.cx>
Link: https://lore.kernel.org/r/20210718173610.894-10-martin@kaiser.cxSigned-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

drivers/staging/rtl8188eu/include/pwrseq.h

@@ -34,21 +34,21 @@
 	 * },
 	 * comment here
 	 */								\
-	{0x0006, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
+	{0x0006, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
 	/* wait till 0x04[17] = 1    power ready*/	\
-	{0x0002, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0) | BIT(1), 0}, \
+	{0x0002, PWR_CMD_WRITE, BIT(0) | BIT(1), 0}, \
 	/* 0x02[1:0] = 0	reset BB*/				\
-	{0x0026, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
+	{0x0026, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
 	/*0x24[23] = 2b'01 schmit trigger */				\
-	{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), 0}, \
+	{0x0005, PWR_CMD_WRITE, BIT(7), 0}, \
 	/* 0x04[15] = 0 disable HWPDN (control by DRV)*/		\
-	{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, \
+	{0x0005, PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, \
 	/*0x04[12:11] = 2b'00 disable WL suspend*/			\
-	{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
+	{0x0005, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
 	/*0x04[8] = 1 polling until return 0*/				\
-	{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(0), 0}, \
+	{0x0005, PWR_CMD_POLLING, BIT(0), 0}, \
 	/*wait till 0x04[8] = 0*/					\
-	{0x0023, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \
+	{0x0023, PWR_CMD_WRITE, BIT(4), 0}, \
 	/*LDO normal mode*/
 
 #define RTL8188E_TRANS_ACT_TO_CARDEMU					\
@@ -57,13 +57,13 @@
 	 * },
 	 * comments here
 	 */								\
-	{0x001F, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0}, \
+	{0x001F, PWR_CMD_WRITE, 0xFF, 0}, \
 	/*0x1F[7:0] = 0 turn off RF*/					\
-	{0x0023, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
+	{0x0023, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
 	/*LDO Sleep mode*/						\
-	{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
+	{0x0005, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
 	/*0x04[9] = 1 turn off MAC by HW state machine*/		\
-	{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(1), 0}, \
+	{0x0005, PWR_CMD_POLLING, BIT(1), 0}, \
 	/*wait till 0x04[9] = 0 polling until return 0 to disable*/
 
 #define RTL8188E_TRANS_CARDEMU_TO_CARDDIS				\
@@ -72,15 +72,15 @@
 	 * value },
 	 * comments here
 	 */								\
-	{0x0026, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
+	{0x0026, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
 	/*0x24[23] = 2b'01 schmit trigger */				\
-	{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \
+	{0x0005, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \
 	/*0x04[12:11] = 2b'01 enable WL suspend*/			\
-	{0x0007, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0}, \
+	{0x0007, PWR_CMD_WRITE, 0xFF, 0}, \
 	/* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\
-	{0x0041, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \
+	{0x0041, PWR_CMD_WRITE, BIT(4), 0}, \
 	/*Clear SIC_EN register 0x40[12] = 1'b0 */			\
-	{0xfe10, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
+	{0xfe10, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
 	/*Set USB suspend enable local register  0xfe10[4]=1 */
 
 /* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */
@@ -90,24 +90,24 @@
 	 * value },
 	 * comments here
 	 */								\
-	{0x0522, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
-	{0x05F8, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \
+	{0x0522, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
+	{0x05F8, PWR_CMD_POLLING, 0xFF, 0}, \
 	/*Should be zero if no packet is transmitting*/			\
-	{0x05F9, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \
+	{0x05F9, PWR_CMD_POLLING, 0xFF, 0}, \
 	/*Should be zero if no packet is transmitting*/			\
-	{0x05FA, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \
+	{0x05FA, PWR_CMD_POLLING, 0xFF, 0}, \
 	/*Should be zero if no packet is transmitting*/			\
-	{0x05FB, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \
+	{0x05FB, PWR_CMD_POLLING, 0xFF, 0}, \
 	/*Should be zero if no packet is transmitting*/			\
-	{0x0002, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0), 0}, \
+	{0x0002, PWR_CMD_WRITE, BIT(0), 0}, \
 	/*CCK and OFDM are disabled,and clock are gated*/		\
-	{0x0002, PWR_CUT_ALL_MSK, PWR_CMD_DELAY, 0,	PWRSEQ_DELAY_US}, \
+	{0x0002, PWR_CMD_DELAY, 0,	PWRSEQ_DELAY_US}, \
 	/*Delay 1us*/ \
-	{0x0100, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0x3F}, \
+	{0x0100, PWR_CMD_WRITE, 0xFF, 0x3F}, \
 	/*Reset MAC TRX*/ \
-	{0x0101, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(1), 0}, \
+	{0x0101, PWR_CMD_WRITE, BIT(1), 0}, \
 	/*check if removed later*/\
-	{0x0553, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(5), BIT(5)}, \
+	{0x0553, PWR_CMD_WRITE, BIT(5), BIT(5)}, \
 	/*Respond TxOK to scheduler*/
 
 #define RTL8188E_TRANS_END						\
@@ -116,7 +116,7 @@
 	 * value },
 	 * comments here
 	 */								\
-	{0xFFFF, PWR_CUT_ALL_MSK, PWR_CMD_END, 0, 0},
+	{0xFFFF, PWR_CMD_END, 0, 0},
 
 extern struct wl_pwr_cfg rtl8188E_power_on_flow
 		[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS];

drivers/staging/rtl8188eu/include/pwrseqcmd.h

@@ -33,7 +33,6 @@ enum pwrseq_cmd_delat_unit {
 
 struct wl_pwr_cfg {
 	u16 offset;
-	u8 cut_msk;
 	u8 cmd:4;
 	u8 msk;
 	u8 value;