Commit 12f2df72 authored by Huang Rui's avatar Huang Rui Committed by Alex Deucher

drm/amdgpu: fix vram type and bandwidth error for DDR5 and DDR4

This patch is to update atomfirmware parser for the memory type and
bandwidth of DDR5 and DDR4.
Signed-off-by: default avatarHuang Rui <ray.huang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 04eb6e77
...@@ -112,6 +112,7 @@ int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev) ...@@ -112,6 +112,7 @@ int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
union igp_info { union igp_info {
struct atom_integrated_system_info_v1_11 v11; struct atom_integrated_system_info_v1_11 v11;
struct atom_integrated_system_info_v1_12 v12; struct atom_integrated_system_info_v1_12 v12;
struct atom_integrated_system_info_v2_1 v21;
}; };
union umc_info { union umc_info {
...@@ -209,9 +210,14 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev, ...@@ -209,9 +210,14 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
if (adev->flags & AMD_IS_APU) { if (adev->flags & AMD_IS_APU) {
igp_info = (union igp_info *) igp_info = (union igp_info *)
(mode_info->atom_context->bios + data_offset); (mode_info->atom_context->bios + data_offset);
switch (frev) {
case 1:
switch (crev) { switch (crev) {
case 11: case 11:
case 12:
mem_channel_number = igp_info->v11.umachannelnumber; mem_channel_number = igp_info->v11.umachannelnumber;
if (!mem_channel_number)
mem_channel_number = 1;
/* channel width is 64 */ /* channel width is 64 */
if (vram_width) if (vram_width)
*vram_width = mem_channel_number * 64; *vram_width = mem_channel_number * 64;
...@@ -219,18 +225,31 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev, ...@@ -219,18 +225,31 @@ amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev,
if (vram_type) if (vram_type)
*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
break; break;
case 12: default:
mem_channel_number = igp_info->v12.umachannelnumber; return -EINVAL;
}
break;
case 2:
switch (crev) {
case 1:
case 2:
mem_channel_number = igp_info->v21.umachannelnumber;
if (!mem_channel_number)
mem_channel_number = 1;
/* channel width is 64 */ /* channel width is 64 */
if (vram_width) if (vram_width)
*vram_width = mem_channel_number * 64; *vram_width = mem_channel_number * 64;
mem_type = igp_info->v12.memorytype; mem_type = igp_info->v21.memorytype;
if (vram_type) if (vram_type)
*vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type);
break; break;
default: default:
return -EINVAL; return -EINVAL;
} }
break;
default:
return -EINVAL;
}
} else { } else {
vram_info = (union vram_info *) vram_info = (union vram_info *)
(mode_info->atom_context->bios + data_offset); (mode_info->atom_context->bios + data_offset);
......
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