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Commit 1351512f authored by Shawn Guo's avatar Shawn Guo Committed by Bjorn Andersson
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arm64: dts: qcom: Correct QMP PHY child node name 

Many child nodes of QMP PHY are named without following bindings schema
and causing dtbs_check warnings like below.

phy@1c06000: 'lane@1c06800' does not match any of the regexes: '^phy@[0-9a-f]+$'
        arch/arm64/boot/dts/qcom/msm8998-asus-novago-tp370ql.dt.yaml
        arch/arm64/boot/dts/qcom/msm8998-hp-envy-x2.dt.yaml
        arch/arm64/boot/dts/qcom/msm8998-lenovo-miix-630.dt.yaml
        arch/arm64/boot/dts/qcom/msm8998-mtp.dt.yaml
        arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dt.yaml
        arch/arm64/boot/dts/qcom/msm8998-oneplus-dumpling.dt.yaml

Correct them to fix the warnings.
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210929034253.24570-5-shawn.guo@linaro.org
parent 82d61e19
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Showing with 25 additions and 25 deletions
arch/arm64/boot/dts/qcom/ipq6018.dtsi
View file @ 1351512f
......@@ -401,7 +401,7 @@ pcie_phy: phy@84000 {
reset-names = "phy",
"common";
pcie_phy0: lane@84200 {
pcie_phy0: phy@84200 {
reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */
<0x0 0x84400 0x0 0x200>, /* Serdes Rx */
<0x0 0x84800 0x0 0x4f4>; /* PCS: Lane0, COM, PCIE */
......
arch/arm64/boot/dts/qcom/ipq8074.dtsi
View file @ 1351512f
......@@ -105,7 +105,7 @@ ssphy_1: phy@58000 {
reset-names = "phy","common";
status = "disabled";
usb1_ssphy: lane@58200 {
usb1_ssphy: phy@58200 {
reg = <0x00058200 0x130>, /* Tx */
<0x00058400 0x200>, /* Rx */
<0x00058800 0x1f8>, /* PCS */
......@@ -148,7 +148,7 @@ ssphy_0: phy@78000 {
reset-names = "phy","common";
status = "disabled";
usb0_ssphy: lane@78200 {
usb0_ssphy: phy@78200 {
reg = <0x00078200 0x130>, /* Tx */
<0x00078400 0x200>, /* Rx */
<0x00078800 0x1f8>, /* PCS */
......
arch/arm64/boot/dts/qcom/msm8996.dtsi
View file @ 1351512f
......@@ -597,7 +597,7 @@ pcie_phy: phy@34000 {
reset-names = "phy", "common", "cfg";
status = "disabled";
pciephy_0: lane@35000 {
pciephy_0: phy@35000 {
reg = <0x00035000 0x130>,
<0x00035200 0x200>,
<0x00035400 0x1dc>;
......@@ -611,7 +611,7 @@ pciephy_0: lane@35000 {
reset-names = "lane0";
};
pciephy_1: lane@36000 {
pciephy_1: phy@36000 {
reg = <0x00036000 0x130>,
<0x00036200 0x200>,
<0x00036400 0x1dc>;
......@@ -624,7 +624,7 @@ pciephy_1: lane@36000 {
reset-names = "lane1";
};
pciephy_2: lane@37000 {
pciephy_2: phy@37000 {
reg = <0x00037000 0x130>,
<0x00037200 0x200>,
<0x00037400 0x1dc>;
......@@ -1779,7 +1779,7 @@ ufsphy: phy@627000 {
reset-names = "ufsphy";
status = "disabled";
ufsphy_lane: lanes@627400 {
ufsphy_lane: phy@627400 {
reg = <0x627400 0x12c>,
<0x627600 0x200>,
<0x627c00 0x1b4>;
......@@ -2633,7 +2633,7 @@ usb3phy: phy@7410000 {
reset-names = "phy", "common";
status = "disabled";
ssusb_phy_0: lane@7410200 {
ssusb_phy_0: phy@7410200 {
reg = <0x07410200 0x200>,
<0x07410400 0x130>,
<0x07410600 0x1a8>;
......
arch/arm64/boot/dts/qcom/msm8998.dtsi
View file @ 1351512f
......@@ -998,7 +998,7 @@ pcie_phy: phy@1c06000 {
vdda-phy-supply = <&vreg_l1a_0p875>;
vdda-pll-supply = <&vreg_l2a_1p2>;
pciephy: lane@1c06800 {
pciephy: phy@1c06800 {
reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
#phy-cells = <0>;
......@@ -1070,7 +1070,7 @@ ufsphy: phy@1da7000 {
reset-names = "ufsphy";
resets = <&ufshc 0>;
ufsphy_lanes: lanes@1da7400 {
ufsphy_lanes: phy@1da7400 {
reg = <0x01da7400 0x128>,
<0x01da7600 0x1fc>,
<0x01da7c00 0x1dc>,
......@@ -2104,7 +2104,7 @@ usb3phy: phy@c010000 {
<&gcc GCC_USB3PHY_PHY_BCR>;
reset-names = "phy", "common";
usb1_ssphy: lane@c010200 {
usb1_ssphy: phy@c010200 {
reg = <0xc010200 0x128>,
<0xc010400 0x200>,
<0xc010c00 0x20c>,
......
arch/arm64/boot/dts/qcom/sdm845.dtsi
View file @ 1351512f
......@@ -2060,7 +2060,7 @@ pcie0_phy: phy@1c06000 {
status = "disabled";
pcie0_lane: lanes@1c06200 {
pcie0_lane: phy@1c06200 {
reg = <0 0x01c06200 0 0x128>,
<0 0x01c06400 0 0x1fc>,
<0 0x01c06800 0 0x218>,
......@@ -2170,7 +2170,7 @@ pcie1_phy: phy@1c0a000 {
status = "disabled";
pcie1_lane: lanes@1c06200 {
pcie1_lane: phy@1c06200 {
reg = <0 0x01c0a800 0 0x800>,
<0 0x01c0a800 0 0x800>,
<0 0x01c0b800 0 0x400>;
......@@ -2298,7 +2298,7 @@ ufs_mem_phy: phy@1d87000 {
reset-names = "ufsphy";
status = "disabled";
ufs_mem_phy_lanes: lanes@1d87400 {
ufs_mem_phy_lanes: phy@1d87400 {
reg = <0 0x01d87400 0 0x108>,
<0 0x01d87600 0 0x1e0>,
<0 0x01d87c00 0 0x1dc>,
......@@ -3723,7 +3723,7 @@ usb_1_qmpphy: phy@88e9000 {
<&gcc GCC_USB3_PHY_PRIM_BCR>;
reset-names = "phy", "common";
usb_1_ssphy: lanes@88e9200 {
usb_1_ssphy: phy@88e9200 {
reg = <0 0x088e9200 0 0x128>,
<0 0x088e9400 0 0x200>,
<0 0x088e9c00 0 0x218>,
......@@ -3756,7 +3756,7 @@ usb_2_qmpphy: phy@88eb000 {
<&gcc GCC_USB3_PHY_SEC_BCR>;
reset-names = "phy", "common";
usb_2_ssphy: lane@88eb200 {
usb_2_ssphy: phy@88eb200 {
reg = <0 0x088eb200 0 0x128>,
<0 0x088eb400 0 0x1fc>,
<0 0x088eb800 0 0x218>,
......
arch/arm64/boot/dts/qcom/sm8150.dtsi
View file @ 1351512f
......@@ -1691,7 +1691,7 @@ ufs_mem_phy: phy@1d87000 {
reset-names = "ufsphy";
status = "disabled";
ufs_mem_phy_lanes: lanes@1d87400 {
ufs_mem_phy_lanes: phy@1d87400 {
reg = <0 0x01d87400 0 0x108>,
<0 0x01d87600 0 0x1e0>,
<0 0x01d87c00 0 0x1dc>,
......@@ -3104,7 +3104,7 @@ usb_1_qmpphy: phy@88e9000 {
<&gcc GCC_USB3_PHY_PRIM_BCR>;
reset-names = "phy", "common";
usb_1_ssphy: lanes@88e9200 {
usb_1_ssphy: phy@88e9200 {
reg = <0 0x088e9200 0 0x200>,
<0 0x088e9400 0 0x200>,
<0 0x088e9c00 0 0x218>,
......@@ -3137,7 +3137,7 @@ usb_2_qmpphy: phy@88eb000 {
<&gcc GCC_USB3_PHY_SEC_BCR>;
reset-names = "phy", "common";
usb_2_ssphy: lane@88eb200 {
usb_2_ssphy: phy@88eb200 {
reg = <0 0x088eb200 0 0x200>,
<0 0x088eb400 0 0x200>,
<0 0x088eb800 0 0x800>,
......
arch/arm64/boot/dts/qcom/sm8250.dtsi
View file @ 1351512f
......@@ -1455,7 +1455,7 @@ pcie0_phy: phy@1c06000 {
status = "disabled";
pcie0_lane: lanes@1c06200 {
pcie0_lane: phy@1c06200 {
reg = <0 0x1c06200 0 0x170>, /* tx */
<0 0x1c06400 0 0x200>, /* rx */
<0 0x1c06800 0 0x1f0>, /* pcs */
......@@ -1559,7 +1559,7 @@ pcie1_phy: phy@1c0e000 {
status = "disabled";
pcie1_lane: lanes@1c0e200 {
pcie1_lane: phy@1c0e200 {
reg = <0 0x1c0e200 0 0x170>, /* tx0 */
<0 0x1c0e400 0 0x200>, /* rx0 */
<0 0x1c0ea00 0 0x1f0>, /* pcs */
......@@ -1665,7 +1665,7 @@ pcie2_phy: phy@1c16000 {
status = "disabled";
pcie2_lane: lanes@1c16200 {
pcie2_lane: phy@1c16200 {
reg = <0 0x1c16200 0 0x170>, /* tx0 */
<0 0x1c16400 0 0x200>, /* rx0 */
<0 0x1c16a00 0 0x1f0>, /* pcs */
......@@ -1742,7 +1742,7 @@ ufs_mem_phy: phy@1d87000 {
reset-names = "ufsphy";
status = "disabled";
ufs_mem_phy_lanes: lanes@1d87400 {
ufs_mem_phy_lanes: phy@1d87400 {
reg = <0 0x01d87400 0 0x108>,
<0 0x01d87600 0 0x1e0>,
<0 0x01d87c00 0 0x1dc>,
......@@ -2323,7 +2323,7 @@ usb_2_qmpphy: phy@88eb000 {
<&gcc GCC_USB3_PHY_SEC_BCR>;
reset-names = "phy", "common";
usb_2_ssphy: lanes@88eb200 {
usb_2_ssphy: phy@88eb200 {
reg = <0 0x088eb200 0 0x200>,
<0 0x088eb400 0 0x200>,
<0 0x088eb800 0 0x800>;
......
arch/arm64/boot/dts/qcom/sm8350.dtsi
View file @ 1351512f
......@@ -1084,7 +1084,7 @@ ufs_mem_phy: phy@1d87000 {
reset-names = "ufsphy";
status = "disabled";
ufs_mem_phy_lanes: lanes@1d87400 {
ufs_mem_phy_lanes: phy@1d87400 {
reg = <0 0x01d87400 0 0x108>,
<0 0x01d87600 0 0x1e0>,
<0 0x01d87c00 0 0x1dc>,
......
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