Commit 16ea975e authored by Rob Clark's avatar Rob Clark

drm/tilcdc: add TI LCD Controller DRM driver (v4)

A simple DRM/KMS driver for the TI LCD Controller found in various
smaller TI parts (AM33xx, OMAPL138, etc).  This driver uses the
CMA helpers.  Currently only the TFP410 DVI encoder is supported
(tested with beaglebone + DVI cape).  There are also various LCD
displays, for which support can be added (as I get hw to test on),
and an external i2c HDMI encoder found on some boards.

The display controller supports a single CRTC.  And the encoder+
connector are split out into sub-devices.  Depending on which LCD
or external encoder is actually present, the appropriate output
module(s) will be loaded.

v1: original
v2: fix fb refcnting and few other cleanups
v3: get +/- vsync/hsync from timings rather than panel-info, add
    option DT max-bandwidth field so driver doesn't attempt to
    pick a display mode with too high memory bandwidth, and other
    small cleanups
v4: remove some unneeded stuff from panel-info struct, properly
    set high bits for hfp/hsw/hbp for rev 2, add DT bindings docs
Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Tested-by: default avatarKoen Kooi <koen@dominion.thruhere.net>
parent b3d3de80
Device-Tree bindings for tilcdc DRM TFP410 output driver
Required properties:
- compatible: value should be "ti,tilcdc,tfp410".
- i2c: the phandle for the i2c device to use for DDC
Recommended properties:
- pinctrl-names, pinctrl-0: the pincontrol settings to configure
muxing properly for pins that connect to TFP410 device
- powerdn-gpio: the powerdown GPIO, pulled low to power down the
TFP410 device (for DPMS_OFF)
Example:
dvicape {
compatible = "ti,tilcdc,tfp410";
i2c = <&i2c2>;
pinctrl-names = "default";
pinctrl-0 = <&bone_dvi_cape_dvi_00A1_pins>;
powerdn-gpio = <&gpio2 31 0>;
};
Device-Tree bindings for tilcdc DRM driver
Required properties:
- compatible: value should be "ti,am33xx-tilcdc".
- interrupts: the interrupt number
- reg: base address and size of the LCDC device
Recommended properties:
- interrupt-parent: the phandle for the interrupt controller that
services interrupts for this device.
- ti,hwmods: Name of the hwmod associated to the LCDC
Example:
fb: fb@4830e000 {
compatible = "ti,am33xx-tilcdc";
reg = <0x4830e000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <36>;
ti,hwmods = "lcdc";
};
...@@ -215,3 +215,5 @@ source "drivers/gpu/drm/cirrus/Kconfig" ...@@ -215,3 +215,5 @@ source "drivers/gpu/drm/cirrus/Kconfig"
source "drivers/gpu/drm/shmobile/Kconfig" source "drivers/gpu/drm/shmobile/Kconfig"
source "drivers/gpu/drm/tegra/Kconfig" source "drivers/gpu/drm/tegra/Kconfig"
source "drivers/gpu/drm/tilcdc/Kconfig"
...@@ -50,4 +50,5 @@ obj-$(CONFIG_DRM_UDL) += udl/ ...@@ -50,4 +50,5 @@ obj-$(CONFIG_DRM_UDL) += udl/
obj-$(CONFIG_DRM_AST) += ast/ obj-$(CONFIG_DRM_AST) += ast/
obj-$(CONFIG_DRM_SHMOBILE) +=shmobile/ obj-$(CONFIG_DRM_SHMOBILE) +=shmobile/
obj-$(CONFIG_DRM_TEGRA) += tegra/ obj-$(CONFIG_DRM_TEGRA) += tegra/
obj-$(CONFIG_DRM_TILCDC) += tilcdc/
obj-y += i2c/ obj-y += i2c/
config DRM_TILCDC
tristate "DRM Support for TI LCDC Display Controller"
depends on DRM && OF
select DRM_KMS_HELPER
select DRM_KMS_CMA_HELPER
select DRM_GEM_CMA_HELPER
help
Choose this option if you have an TI SoC with LCDC display
controller, for example AM33xx in beagle-bone, DA8xx, or
OMAP-L1xx. This driver replaces the FB_DA8XX fbdev driver.
ccflags-y := -Iinclude/drm -Werror
tilcdc-y := \
tilcdc_crtc.o \
tilcdc_tfp410.o \
tilcdc_drv.o
obj-$(CONFIG_DRM_TILCDC) += tilcdc.o
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/*
* Copyright (C) 2012 Texas Instruments
* Author: Rob Clark <robdclark@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __TILCDC_DRV_H__
#define __TILCDC_DRV_H__
#include <linux/clk.h>
#include <linux/cpufreq.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/list.h>
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_fb_cma_helper.h>
struct tilcdc_drm_private {
void __iomem *mmio;
struct clk *disp_clk; /* display dpll */
struct clk *clk; /* functional clock */
int rev; /* IP revision */
/* don't attempt resolutions w/ higher W * H * Hz: */
uint32_t max_bandwidth;
/* register contents saved across suspend/resume: */
u32 saved_register[12];
#ifdef CONFIG_CPU_FREQ
struct notifier_block freq_transition;
unsigned int lcd_fck_rate;
#endif
struct workqueue_struct *wq;
struct drm_fbdev_cma *fbdev;
struct drm_crtc *crtc;
unsigned int num_encoders;
struct drm_encoder *encoders[8];
unsigned int num_connectors;
struct drm_connector *connectors[8];
};
/* Sub-module for display. Since we don't know at compile time what panels
* or display adapter(s) might be present (for ex, off chip dvi/tfp410,
* hdmi encoder, various lcd panels), the connector/encoder(s) are split into
* separate drivers. If they are probed and found to be present, they
* register themselves with tilcdc_register_module().
*/
struct tilcdc_module;
struct tilcdc_module_ops {
/* create appropriate encoders/connectors: */
int (*modeset_init)(struct tilcdc_module *mod, struct drm_device *dev);
void (*destroy)(struct tilcdc_module *mod);
#ifdef CONFIG_DEBUG_FS
/* create debugfs nodes (can be NULL): */
int (*debugfs_init)(struct tilcdc_module *mod, struct drm_minor *minor);
/* cleanup debugfs nodes (can be NULL): */
void (*debugfs_cleanup)(struct tilcdc_module *mod, struct drm_minor *minor);
#endif
};
struct tilcdc_module {
const char *name;
struct list_head list;
const struct tilcdc_module_ops *funcs;
};
void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
const struct tilcdc_module_ops *funcs);
void tilcdc_module_cleanup(struct tilcdc_module *mod);
/* Panel config that needs to be set in the crtc, but is not coming from
* the mode timings. The display module is expected to call
* tilcdc_crtc_set_panel_info() to set this during modeset.
*/
struct tilcdc_panel_info {
/* AC Bias Pin Frequency */
uint32_t ac_bias;
/* AC Bias Pin Transitions per Interrupt */
uint32_t ac_bias_intrpt;
/* DMA burst size */
uint32_t dma_burst_sz;
/* Bits per pixel */
uint32_t bpp;
/* FIFO DMA Request Delay */
uint32_t fdd;
/* TFT Alternative Signal Mapping (Only for active) */
bool tft_alt_mode;
/* Invert pixel clock */
bool invert_pxl_clk;
/* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
uint32_t sync_edge;
/* Horizontal and Vertical Sync: Control: 0=ignore */
uint32_t sync_ctrl;
/* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
uint32_t raster_order;
/* DMA FIFO threshold */
uint32_t fifo_th;
};
#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev);
void tilcdc_crtc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file);
irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc);
void tilcdc_crtc_update_clk(struct drm_crtc *crtc);
void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
const struct tilcdc_panel_info *info);
int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode);
int tilcdc_crtc_max_width(struct drm_crtc *crtc);
#endif /* __TILCDC_DRV_H__ */
/*
* Copyright (C) 2012 Texas Instruments
* Author: Rob Clark <robdclark@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __TILCDC_REGS_H__
#define __TILCDC_REGS_H__
/* LCDC register definitions, based on da8xx-fb */
#include <linux/bitops.h>
#include "tilcdc_drv.h"
/* LCDC Status Register */
#define LCDC_END_OF_FRAME1 BIT(9)
#define LCDC_END_OF_FRAME0 BIT(8)
#define LCDC_PL_LOAD_DONE BIT(6)
#define LCDC_FIFO_UNDERFLOW BIT(5)
#define LCDC_SYNC_LOST BIT(2)
#define LCDC_FRAME_DONE BIT(0)
/* LCDC DMA Control Register */
#define LCDC_DMA_BURST_SIZE(x) ((x) << 4)
#define LCDC_DMA_BURST_1 0x0
#define LCDC_DMA_BURST_2 0x1
#define LCDC_DMA_BURST_4 0x2
#define LCDC_DMA_BURST_8 0x3
#define LCDC_DMA_BURST_16 0x4
#define LCDC_V1_END_OF_FRAME_INT_ENA BIT(2)
#define LCDC_V2_END_OF_FRAME0_INT_ENA BIT(8)
#define LCDC_V2_END_OF_FRAME1_INT_ENA BIT(9)
#define LCDC_DUAL_FRAME_BUFFER_ENABLE BIT(0)
/* LCDC Control Register */
#define LCDC_CLK_DIVISOR(x) ((x) << 8)
#define LCDC_RASTER_MODE 0x01
/* LCDC Raster Control Register */
#define LCDC_PALETTE_LOAD_MODE(x) ((x) << 20)
#define PALETTE_AND_DATA 0x00
#define PALETTE_ONLY 0x01
#define DATA_ONLY 0x02
#define LCDC_MONO_8BIT_MODE BIT(9)
#define LCDC_RASTER_ORDER BIT(8)
#define LCDC_TFT_MODE BIT(7)
#define LCDC_V1_UNDERFLOW_INT_ENA BIT(6)
#define LCDC_V2_UNDERFLOW_INT_ENA BIT(5)
#define LCDC_V1_PL_INT_ENA BIT(4)
#define LCDC_V2_PL_INT_ENA BIT(6)
#define LCDC_MONOCHROME_MODE BIT(1)
#define LCDC_RASTER_ENABLE BIT(0)
#define LCDC_TFT_ALT_ENABLE BIT(23)
#define LCDC_STN_565_ENABLE BIT(24)
#define LCDC_V2_DMA_CLK_EN BIT(2)
#define LCDC_V2_LIDD_CLK_EN BIT(1)
#define LCDC_V2_CORE_CLK_EN BIT(0)
#define LCDC_V2_LPP_B10 26
#define LCDC_V2_TFT_24BPP_MODE BIT(25)
#define LCDC_V2_TFT_24BPP_UNPACK BIT(26)
/* LCDC Raster Timing 2 Register */
#define LCDC_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
#define LCDC_AC_BIAS_FREQUENCY(x) ((x) << 8)
#define LCDC_SYNC_CTRL BIT(25)
#define LCDC_SYNC_EDGE BIT(24)
#define LCDC_INVERT_PIXEL_CLOCK BIT(22)
#define LCDC_INVERT_HSYNC BIT(21)
#define LCDC_INVERT_VSYNC BIT(20)
/* LCDC Block */
#define LCDC_PID_REG 0x0
#define LCDC_CTRL_REG 0x4
#define LCDC_STAT_REG 0x8
#define LCDC_RASTER_CTRL_REG 0x28
#define LCDC_RASTER_TIMING_0_REG 0x2c
#define LCDC_RASTER_TIMING_1_REG 0x30
#define LCDC_RASTER_TIMING_2_REG 0x34
#define LCDC_DMA_CTRL_REG 0x40
#define LCDC_DMA_FB_BASE_ADDR_0_REG 0x44
#define LCDC_DMA_FB_CEILING_ADDR_0_REG 0x48
#define LCDC_DMA_FB_BASE_ADDR_1_REG 0x4c
#define LCDC_DMA_FB_CEILING_ADDR_1_REG 0x50
/* Interrupt Registers available only in Version 2 */
#define LCDC_RAW_STAT_REG 0x58
#define LCDC_MASKED_STAT_REG 0x5c
#define LCDC_INT_ENABLE_SET_REG 0x60
#define LCDC_INT_ENABLE_CLR_REG 0x64
#define LCDC_END_OF_INT_IND_REG 0x68
/* Clock registers available only on Version 2 */
#define LCDC_CLK_ENABLE_REG 0x6c
#define LCDC_CLK_RESET_REG 0x70
#define LCDC_CLK_MAIN_RESET BIT(3)
/*
* Helpers:
*/
static inline void tilcdc_write(struct drm_device *dev, u32 reg, u32 data)
{
struct tilcdc_drm_private *priv = dev->dev_private;
iowrite32(data, priv->mmio + reg);
}
static inline u32 tilcdc_read(struct drm_device *dev, u32 reg)
{
struct tilcdc_drm_private *priv = dev->dev_private;
return ioread32(priv->mmio + reg);
}
static inline void tilcdc_set(struct drm_device *dev, u32 reg, u32 mask)
{
tilcdc_write(dev, reg, tilcdc_read(dev, reg) | mask);
}
static inline void tilcdc_clear(struct drm_device *dev, u32 reg, u32 mask)
{
tilcdc_write(dev, reg, tilcdc_read(dev, reg) & ~mask);
}
/* the register to read/clear irqstatus differs between v1 and v2 of the IP */
static inline u32 tilcdc_irqstatus_reg(struct drm_device *dev)
{
struct tilcdc_drm_private *priv = dev->dev_private;
return (priv->rev == 2) ? LCDC_MASKED_STAT_REG : LCDC_STAT_REG;
}
static inline u32 tilcdc_read_irqstatus(struct drm_device *dev)
{
return tilcdc_read(dev, tilcdc_irqstatus_reg(dev));
}
static inline void tilcdc_clear_irqstatus(struct drm_device *dev, u32 mask)
{
tilcdc_write(dev, tilcdc_irqstatus_reg(dev), mask);
}
#endif /* __TILCDC_REGS_H__ */
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/*
* Copyright (C) 2012 Texas Instruments
* Author: Rob Clark <robdclark@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __TILCDC_TFP410_H__
#define __TILCDC_TFP410_H__
/* sub-module for tfp410 dvi adaptor */
int tilcdc_tfp410_init(void);
void tilcdc_tfp410_fini(void);
#endif /* __TILCDC_TFP410_H__ */
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