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Commit 171d429a authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'renesas-arm64-dt-for-v4.18' of... 

Merge tag 'renesas-arm64-dt-for-v4.18' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/late

Renesas ARM64 Based SoC DT Updates for v4.18

* Cleanups:
  - Correct whitespace
  - sort subnodes of the root and soc nodes
* R-Car M3-N (r8a77965) SoC
  - Describe MSIOF SPI, PWM, SDHI and I2C devices in DT
  - Add thermal support
* R-Car H3 (r8a7795) and R-Car M3-W (r8a7796) SoCs
  - Decrease temperature hysteresis
* R-Car H3 (r8a7795), M3-W (r8a7796) and M3-N (r8a77965) SoCs
  - Add address properties to rcar_sound port nodes
* R-Car H3 (r8a7795), M3-W (r8a7796) V3M (r8a77970) and D3 (r8a77995) SoCs
  - Enable IPMMU devices
* R-Car M3-N (r8a77965) and V3H (r8a77980) SoCs
  - Use sysc binding macros
  - Describe USB2 and USB3 devices in DT
* R-Car V3M (r8a77970) SoC
  - Add SMP Support
  - Correct IPMMU DS1 bit number
* R-Car V3H (r8a77980) SoC
  - Use CPG clock binding macros
* R-Car V3H (r8a77980) and V3M (r8a77970) SoCs
  - Disable EtherAVB
* R-Car D3 (r8a77995) SoC
  - Describe VIN4 in DT

* Ebisu board with R-Car E3 (r8a77990) SoC
  - Initial support
* Salvator-XS boards with R-Car H3 (r8a7795) SoC
  - Enable USB2.0 channel 3
* Salvator-X and Salvator-XS boards with M3-N (r8a77965) SoC
  - Enable DU
* Salvator-X and Salvator-XS boards with
  R-Car H3 (r8a7795), M3-W (r8a7796) and M3-N (r8a77965) SoCs
  - Enable nable VIN, CSI-2 and ADV7482
  - Add PMIC DDR Backup Power config
  - Add EEPROM
  - Enable HDMI Sound
* Salvator-X and Salvator-XS boards with
  R-Car H3 (r8a7795), M3-W (r8a7796) and M3-N (r8a77965) SoCs, and
  Draak board with R-Car D3 (r8a77995) SoC
  - Consistently name EtherAVB mdio pin group
* Ebisu board with R-Car E3 (r8a77990) SoC
  - Initial support: Memory, Main crystal, Serial console
  - Enable Ethernet
  - Revise PSCI node
  - Revise cache controller node
* V3HSK board with R-Car V3H (r8a77980) SoC
  - Initial board device tree
  - Enable PFC support and use for EtherAVB
* V3MSK board with R-Car V3M (r8a77970) SoC
  - Add DU/LVDS/HDMI support
  - Enable PFC for EtherAVB
* Condor board with R-Car V3H (r8a77980) SoC
  - Enable eMMC
  - Enable PFC support and use for EtherAVB and SCIF0
* Eagle board with R-Car V3M (r8a77970) SoC
  - Enable HDMI output
* Eagle board with R-Car V3M (r8a77970) SoC and
  Condor board with R-Car V3H (r8a77980) SoC
  - Enable CAN-FD

* tag 'renesas-arm64-dt-for-v4.18' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (102 commits)
  arm64: dts: renesas: salvator-common: Add ADV7482 support
  arm64: dts: renesas: salvator-common: enable VIN
  arm64: dts: renesas: r8a77970: add VIN and CSI-2 nodes
  arm64: dts: renesas: r8a77965: add VIN and CSI-2 nodes
  arm64: dts: renesas: r8a7796: add VIN and CSI-2 nodes
  arm64: dts: renesas: r8a7795-es1: add CSI-2 node
  arm64: dts: renesas: r8a7795: add VIN and CSI-2 nodes
  arm64: dts: renesas: r8a77965: add I2C support
  arm64: dts: renesas: r8a77990: ebisu: Enable EthernetAVB
  arm64: dts: renesas: r8a77990: Add EthernetAVB device nodes
  arm64: dts: renesas: r8a77990: Add GPIO device nodes
  arm64: dts: renesas: r8a77990: Add PFC device node
  arm64: dts: renesas: initial V3HSK board device tree
  arm64: dts: renesas: r8a77980: disable EtherAVB
  arm64: dts: renesas: r8a77970: disable EtherAVB
  arm64: dts: renesas: r8a77995: Add VIN4
  arm64: dts: renesas: r8a77980: add resets property to CAN-FD node
  arm64: dts: renesas: r8a77970: Add Cortex-A53 PMU node
  arm64: dts: renesas: r8a77970: Add secondary CA53 CPU core
  arm64: dts: renesas: r8a77965: Add SDHI device nodes
  ...
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents ae709bf8 908001d7
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arch/arm64/Kconfig.platforms
View file @ 171d429a
...@@ -208,6 +208,12 @@ config ARCH_R8A77980 ...@@ -208,6 +208,12 @@ config ARCH_R8A77980
help help
This enables support for the Renesas R-Car V3H SoC. This enables support for the Renesas R-Car V3H SoC.
config ARCH_R8A77990
bool "Renesas R-Car E3 SoC Platform"
depends on ARCH_RENESAS
help
This enables support for the Renesas R-Car E3 SoC.
config ARCH_R8A77995 config ARCH_R8A77995
bool "Renesas R-Car D3 SoC Platform" bool "Renesas R-Car D3 SoC Platform"
depends on ARCH_RENESAS depends on ARCH_RENESAS
......
arch/arm64/boot/dts/renesas/Makefile
View file @ 171d429a
...@@ -9,5 +9,6 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb ...@@ -9,5 +9,6 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb
dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb r8a77980-v3hsk.dtb
dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb
dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
View file @ 171d429a
...@@ -56,6 +56,12 @@ &ehci2 { ...@@ -56,6 +56,12 @@ &ehci2 {
status = "okay"; status = "okay";
}; };
&sound_card {
dais = <&rsnd_port0 /* ak4613 */
&rsnd_port1 /* HDMI0 */
&rsnd_port2>; /* HDMI1 */
};
&hdmi0 { &hdmi0 {
status = "okay"; status = "okay";
...@@ -66,6 +72,12 @@ rcar_dw_hdmi0_out: endpoint { ...@@ -66,6 +72,12 @@ rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>; remote-endpoint = <&hdmi0_con>;
}; };
}; };
port@2 {
reg = <2>;
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint1>;
};
};
}; };
}; };
...@@ -83,6 +95,12 @@ rcar_dw_hdmi1_out: endpoint { ...@@ -83,6 +95,12 @@ rcar_dw_hdmi1_out: endpoint {
remote-endpoint = <&hdmi1_con>; remote-endpoint = <&hdmi1_con>;
}; };
}; };
port@2 {
reg = <2>;
dw_hdmi1_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint2>;
};
};
}; };
}; };
...@@ -94,6 +112,34 @@ &ohci2 { ...@@ -94,6 +112,34 @@ &ohci2 {
status = "okay"; status = "okay";
}; };
&rcar_sound {
ports {
/* rsnd_port0 is on salvator-common */
rsnd_port1: port@1 {
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint1>;
frame-master = <&rsnd_endpoint1>;
playback = <&ssi2>;
};
};
rsnd_port2: port@2 {
rsnd_endpoint2: endpoint {
remote-endpoint = <&dw_hdmi1_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint2>;
frame-master = <&rsnd_endpoint2>;
playback = <&ssi3>;
};
};
};
};
&pfc { &pfc {
usb2_pins: usb2 { usb2_pins: usb2 {
groups = "usb2"; groups = "usb2";
......
arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
View file @ 171d429a
...@@ -39,7 +39,6 @@ ipmmu_sy: mmu@e7730000 { ...@@ -39,7 +39,6 @@ ipmmu_sy: mmu@e7730000 {
reg = <0 0xe7730000 0 0x1000>; reg = <0 0xe7730000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 8>; renesas,ipmmu-main = <&ipmmu_mm 8>;
#iommu-cells = <1>; #iommu-cells = <1>;
status = "disabled";
}; };
/delete-node/ usb-phy@ee0e0200; /delete-node/ usb-phy@ee0e0200;
...@@ -108,6 +107,61 @@ fdp1@fe948000 { ...@@ -108,6 +107,61 @@ fdp1@fe948000 {
resets = <&cpg 117>; resets = <&cpg 117>;
renesas,fcp = <&fcpf2>; renesas,fcp = <&fcpf2>;
}; };
csi21: csi2@fea90000 {
compatible = "renesas,r8a7795-csi2";
reg = <0 0xfea90000 0 0x10000>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 713>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 713>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
csi21vin0: endpoint@0 {
reg = <0>;
remote-endpoint = <&vin0csi21>;
};
csi21vin1: endpoint@1 {
reg = <1>;
remote-endpoint = <&vin1csi21>;
};
csi21vin2: endpoint@2 {
reg = <2>;
remote-endpoint = <&vin2csi21>;
};
csi21vin3: endpoint@3 {
reg = <3>;
remote-endpoint = <&vin3csi21>;
};
csi21vin4: endpoint@4 {
reg = <4>;
remote-endpoint = <&vin4csi21>;
};
csi21vin5: endpoint@5 {
reg = <5>;
remote-endpoint = <&vin5csi21>;
};
csi21vin6: endpoint@6 {
reg = <6>;
remote-endpoint = <&vin6csi21>;
};
csi21vin7: endpoint@7 {
reg = <7>;
remote-endpoint = <&vin7csi21>;
};
};
};
};
}; };
&gpio1 { &gpio1 {
...@@ -175,3 +229,91 @@ &fcpvd2 { ...@@ -175,3 +229,91 @@ &fcpvd2 {
&du { &du {
vsps = <&vspd0 &vspd1 &vspd2 &vspd3>; vsps = <&vspd0 &vspd1 &vspd2 &vspd3>;
}; };
&vin0 {
ports {
port@1 {
vin0csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin0>;
};
};
};
};
&vin1 {
ports {
port@1 {
vin1csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin1>;
};
};
};
};
&vin2 {
ports {
port@1 {
vin2csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin2>;
};
};
};
};
&vin3 {
ports {
port@1 {
vin3csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin3>;
};
};
};
};
&vin4 {
ports {
port@1 {
vin4csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin4>;
};
};
};
};
&vin5 {
ports {
port@1 {
vin5csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin5>;
};
};
};
};
&vin6 {
ports {
port@1 {
vin6csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin6>;
};
};
};
};
&vin7 {
ports {
port@1 {
vin7csi21: endpoint@1 {
reg = <1>;
remote-endpoint= <&csi21vin7>;
};
};
};
};
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
View file @ 171d429a
...@@ -56,6 +56,12 @@ &ehci2 { ...@@ -56,6 +56,12 @@ &ehci2 {
status = "okay"; status = "okay";
}; };
&sound_card {
dais = <&rsnd_port0 /* ak4613 */
&rsnd_port1 /* HDMI0 */
&rsnd_port2>; /* HDMI1 */
};
&hdmi0 { &hdmi0 {
status = "okay"; status = "okay";
...@@ -66,6 +72,12 @@ rcar_dw_hdmi0_out: endpoint { ...@@ -66,6 +72,12 @@ rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>; remote-endpoint = <&hdmi0_con>;
}; };
}; };
port@2 {
reg = <2>;
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint1>;
};
};
}; };
}; };
...@@ -83,6 +95,12 @@ rcar_dw_hdmi1_out: endpoint { ...@@ -83,6 +95,12 @@ rcar_dw_hdmi1_out: endpoint {
remote-endpoint = <&hdmi1_con>; remote-endpoint = <&hdmi1_con>;
}; };
}; };
port@2 {
reg = <2>;
dw_hdmi1_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint2>;
};
};
}; };
}; };
...@@ -94,6 +112,34 @@ &ohci2 { ...@@ -94,6 +112,34 @@ &ohci2 {
status = "okay"; status = "okay";
}; };
&rcar_sound {
ports {
/* rsnd_port0 is on salvator-common */
rsnd_port1: port@1 {
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint1>;
frame-master = <&rsnd_endpoint1>;
playback = <&ssi2>;
};
};
rsnd_port2: port@2 {
rsnd_endpoint2: endpoint {
remote-endpoint = <&dw_hdmi1_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint2>;
frame-master = <&rsnd_endpoint2>;
playback = <&ssi3>;
};
};
};
};
&pfc { &pfc {
usb2_pins: usb2 { usb2_pins: usb2 {
groups = "usb2"; groups = "usb2";
......
arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
View file @ 171d429a
...@@ -56,6 +56,22 @@ &ehci2 { ...@@ -56,6 +56,22 @@ &ehci2 {
status = "okay"; status = "okay";
}; };
&ehci3 {
dr_mode = "otg";
status = "okay";
};
&hsusb3 {
dr_mode = "otg";
status = "okay";
};
&sound_card {
dais = <&rsnd_port0 /* ak4613 */
&rsnd_port1 /* HDMI0 */
&rsnd_port2>; /* HDMI1 */
};
&hdmi0 { &hdmi0 {
status = "okay"; status = "okay";
...@@ -66,6 +82,12 @@ rcar_dw_hdmi0_out: endpoint { ...@@ -66,6 +82,12 @@ rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>; remote-endpoint = <&hdmi0_con>;
}; };
}; };
port@2 {
reg = <2>;
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint1>;
};
};
}; };
}; };
...@@ -83,6 +105,12 @@ rcar_dw_hdmi1_out: endpoint { ...@@ -83,6 +105,12 @@ rcar_dw_hdmi1_out: endpoint {
remote-endpoint = <&hdmi1_con>; remote-endpoint = <&hdmi1_con>;
}; };
}; };
port@2 {
reg = <2>;
dw_hdmi1_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint2>;
};
};
}; };
}; };
...@@ -94,11 +122,61 @@ &ohci2 { ...@@ -94,11 +122,61 @@ &ohci2 {
status = "okay"; status = "okay";
}; };
&ohci3 {
dr_mode = "otg";
status = "okay";
};
&rcar_sound {
ports {
/* rsnd_port0 is on salvator-common */
rsnd_port1: port@1 {
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint1>;
frame-master = <&rsnd_endpoint1>;
playback = <&ssi2>;
};
};
rsnd_port2: port@2 {
rsnd_endpoint2: endpoint {
remote-endpoint = <&dw_hdmi1_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint2>;
frame-master = <&rsnd_endpoint2>;
playback = <&ssi3>;
};
};
};
};
&pfc { &pfc {
usb2_pins: usb2 { usb2_pins: usb2 {
groups = "usb2"; groups = "usb2";
function = "usb2"; function = "usb2";
}; };
/*
* - On Salvator-X[S], GP6_3[01] are connected to ADV7482 as irq pins
* (when SW31 is the default setting on Salvator-XS).
* - If SW31 is the default setting, you cannot use USB2.0 ch3 on
* r8a7795 with Salvator-XS.
* Hence the SW31 setting must be changed like 2) below.
* 1) Default setting of SW31: ON-ON-OFF-OFF-OFF-OFF:
* - Connect GP6_3[01] to ADV7842.
* 2) Changed setting of SW31: OFF-OFF-ON-ON-ON-ON:
* - Connect GP6_3[01] to BD082065 (USB2.0 ch3's host power).
* - Connect GP6_{04,21} to ADV7842.
*/
usb2_ch3_pins: usb2_ch3 {
groups = "usb2_ch3";
function = "usb2_ch3";
};
}; };
&usb2_phy2 { &usb2_phy2 {
...@@ -107,3 +185,10 @@ &usb2_phy2 { ...@@ -107,3 +185,10 @@ &usb2_phy2 {
status = "okay"; status = "okay";
}; };
&usb2_phy3 {
pinctrl-0 = <&usb2_ch3_pins>;
pinctrl-names = "default";
status = "okay";
};
arch/arm64/boot/dts/renesas/r8a7795.dtsi
View file @ 171d429a
...@@ -30,6 +30,91 @@ aliases { ...@@ -30,6 +30,91 @@ aliases {
i2c7 = &i2c_dvfs; i2c7 = &i2c_dvfs;
}; };
/*
* The external audio clocks are configured as 0 Hz fixed frequency
* clocks by default.
* Boards that provide audio clocks should override them.
*/
audio_clk_a: audio_clk_a {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
audio_clk_b: audio_clk_b {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
audio_clk_c: audio_clk_c {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
cluster0_opp: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <830000>;
clock-latency-ns = <300000>;
opp-suspend;
};
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <900000>;
clock-latency-ns = <300000>;
turbo-mode;
};
opp-1700000000 {
opp-hz = /bits/ 64 <1700000000>;
opp-microvolt = <960000>;
clock-latency-ns = <300000>;
turbo-mode;
};
};
cluster1_opp: opp_table1 {
compatible = "operating-points-v2";
opp-shared;
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
};
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
...@@ -47,7 +132,7 @@ a57_0: cpu@0 { ...@@ -47,7 +132,7 @@ a57_0: cpu@0 {
}; };
a57_1: cpu@1 { a57_1: cpu@1 {
compatible = "arm,cortex-a57","arm,armv8"; compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x1>; reg = <0x1>;
device_type = "cpu"; device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA57_CPU1>; power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
...@@ -59,7 +144,7 @@ a57_1: cpu@1 { ...@@ -59,7 +144,7 @@ a57_1: cpu@1 {
}; };
a57_2: cpu@2 { a57_2: cpu@2 {
compatible = "arm,cortex-a57","arm,armv8"; compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x2>; reg = <0x2>;
device_type = "cpu"; device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA57_CPU2>; power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
...@@ -71,7 +156,7 @@ a57_2: cpu@2 { ...@@ -71,7 +156,7 @@ a57_2: cpu@2 {
}; };
a57_3: cpu@3 { a57_3: cpu@3 {
compatible = "arm,cortex-a57","arm,armv8"; compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x3>; reg = <0x3>;
device_type = "cpu"; device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA57_CPU3>; power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
...@@ -94,7 +179,7 @@ a53_0: cpu@100 { ...@@ -94,7 +179,7 @@ a53_0: cpu@100 {
}; };
a53_1: cpu@101 { a53_1: cpu@101 {
compatible = "arm,cortex-a53","arm,armv8"; compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x101>; reg = <0x101>;
device_type = "cpu"; device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA53_CPU1>; power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
...@@ -105,7 +190,7 @@ a53_1: cpu@101 { ...@@ -105,7 +190,7 @@ a53_1: cpu@101 {
}; };
a53_2: cpu@102 { a53_2: cpu@102 {
compatible = "arm,cortex-a53","arm,armv8"; compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x102>; reg = <0x102>;
device_type = "cpu"; device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA53_CPU2>; power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
...@@ -116,7 +201,7 @@ a53_2: cpu@102 { ...@@ -116,7 +201,7 @@ a53_2: cpu@102 {
}; };
a53_3: cpu@103 { a53_3: cpu@103 {
compatible = "arm,cortex-a53","arm,armv8"; compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x103>; reg = <0x103>;
device_type = "cpu"; device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA53_CPU3>; power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
...@@ -155,91 +240,6 @@ extalr_clk: extalr { ...@@ -155,91 +240,6 @@ extalr_clk: extalr {
clock-frequency = <0>; clock-frequency = <0>;
}; };
/*
* The external audio clocks are configured as 0 Hz fixed frequency
* clocks by default.
* Boards that provide audio clocks should override them.
*/
audio_clk_a: audio_clk_a {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
audio_clk_b: audio_clk_b {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
audio_clk_c: audio_clk_c {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
cluster0_opp: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <830000>;
clock-latency-ns = <300000>;
opp-suspend;
};
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <900000>;
clock-latency-ns = <300000>;
turbo-mode;
};
opp-1700000000 {
opp-hz = /bits/ 64 <1700000000>;
opp-microvolt = <960000>;
clock-latency-ns = <300000>;
turbo-mode;
};
};
cluster1_opp: opp_table1 {
compatible = "operating-points-v2";
opp-shared;
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
};
/* External PCIe clock - can be overridden by the board */ /* External PCIe clock - can be overridden by the board */
pcie_bus_clk: pcie_bus { pcie_bus_clk: pcie_bus {
compatible = "fixed-clock"; compatible = "fixed-clock";
...@@ -247,18 +247,6 @@ pcie_bus_clk: pcie_bus { ...@@ -247,18 +247,6 @@ pcie_bus_clk: pcie_bus {
clock-frequency = <0>; clock-frequency = <0>;
}; };
pmu_a57 {
compatible = "arm,cortex-a57-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a57_0>,
<&a57_1>,
<&a57_2>,
<&a57_3>;
};
pmu_a53 { pmu_a53 {
compatible = "arm,cortex-a53-pmu"; compatible = "arm,cortex-a53-pmu";
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
...@@ -271,6 +259,18 @@ pmu_a53 { ...@@ -271,6 +259,18 @@ pmu_a53 {
<&a53_3>; <&a53_3>;
}; };
pmu_a57 {
compatible = "arm,cortex-a57-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a57_0>,
<&a57_1>,
<&a57_2>,
<&a57_3>;
};
psci { psci {
compatible = "arm,psci-1.0", "arm,psci-0.2"; compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc"; method = "smc";
...@@ -291,23 +291,6 @@ soc: soc { ...@@ -291,23 +291,6 @@ soc: soc {
#size-cells = <2>; #size-cells = <2>;
ranges; ranges;
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xf1010000 0 0x1000>,
<0x0 0xf1020000 0 0x20000>,
<0x0 0xf1040000 0 0x20000>,
<0x0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 408>;
};
wdt0: watchdog@e6020000 { wdt0: watchdog@e6020000 {
compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>; reg = <0 0xe6020000 0 0x0c>;
...@@ -437,6 +420,11 @@ gpio7: gpio@e6055800 { ...@@ -437,6 +420,11 @@ gpio7: gpio@e6055800 {
resets = <&cpg 905>; resets = <&cpg 905>;
}; };
pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a7795";
reg = <0 0xe6060000 0 0x50c>;
};
cpg: clock-controller@e6150000 { cpg: clock-controller@e6150000 {
compatible = "renesas,r8a7795-cpg-mssr"; compatible = "renesas,r8a7795-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>; reg = <0 0xe6150000 0 0x1000>;
...@@ -452,20 +440,25 @@ rst: reset-controller@e6160000 { ...@@ -452,20 +440,25 @@ rst: reset-controller@e6160000 {
reg = <0 0xe6160000 0 0x0200>; reg = <0 0xe6160000 0 0x0200>;
}; };
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
};
sysc: system-controller@e6180000 { sysc: system-controller@e6180000 {
compatible = "renesas,r8a7795-sysc"; compatible = "renesas,r8a7795-sysc";
reg = <0 0xe6180000 0 0x0400>; reg = <0 0xe6180000 0 0x0400>;
#power-domain-cells = <1>; #power-domain-cells = <1>;
}; };
pfc: pin-controller@e6060000 { tsc: thermal@e6198000 {
compatible = "renesas,pfc-r8a7795"; compatible = "renesas,r8a7795-thermal";
reg = <0 0xe6060000 0 0x50c>; reg = <0 0xe6198000 0 0x100>,
<0 0xe61a0000 0 0x100>,
<0 0xe61a8000 0 0x100>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 522>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 522>;
#thermal-sensor-cells = <1>;
status = "okay";
}; };
intc_ex: interrupt-controller@e61c0000 { intc_ex: interrupt-controller@e61c0000 {
...@@ -484,153 +477,326 @@ GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH ...@@ -484,153 +477,326 @@ GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
resets = <&cpg 407>; resets = <&cpg 407>;
}; };
ipmmu_vi0: mmu@febd0000 { i2c0: i2c@e6500000 {
compatible = "renesas,ipmmu-r8a7795"; #address-cells = <1>;
reg = <0 0xfebd0000 0 0x1000>; #size-cells = <0>;
renesas,ipmmu-main = <&ipmmu_mm 14>; compatible = "renesas,i2c-r8a7795",
"renesas,rcar-gen3-i2c";
reg = <0 0xe6500000 0 0x40>;
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 931>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>; resets = <&cpg 931>;
}; dmas = <&dmac1 0x91>, <&dmac1 0x90>,
<&dmac2 0x91>, <&dmac2 0x90>;
ipmmu_vi1: mmu@febe0000 { dma-names = "tx", "rx", "tx", "rx";
compatible = "renesas,ipmmu-r8a7795"; i2c-scl-internal-delay-ns = <110>;
reg = <0 0xfebe0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 15>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
status = "disabled"; status = "disabled";
}; };
ipmmu_vp0: mmu@fe990000 { i2c1: i2c@e6508000 {
compatible = "renesas,ipmmu-r8a7795"; #address-cells = <1>;
reg = <0 0xfe990000 0 0x1000>; #size-cells = <0>;
renesas,ipmmu-main = <&ipmmu_mm 16>; compatible = "renesas,i2c-r8a7795",
power-domains = <&sysc R8A7795_PD_A3VP>; "renesas,rcar-gen3-i2c";
#iommu-cells = <1>; reg = <0 0xe6508000 0 0x40>;
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 930>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 930>;
dmas = <&dmac1 0x93>, <&dmac1 0x92>,
<&dmac2 0x93>, <&dmac2 0x92>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled"; status = "disabled";
}; };
ipmmu_vp1: mmu@fe980000 { i2c2: i2c@e6510000 {
compatible = "renesas,ipmmu-r8a7795"; #address-cells = <1>;
reg = <0 0xfe980000 0 0x1000>; #size-cells = <0>;
renesas,ipmmu-main = <&ipmmu_mm 17>; compatible = "renesas,i2c-r8a7795",
power-domains = <&sysc R8A7795_PD_A3VP>; "renesas,rcar-gen3-i2c";
#iommu-cells = <1>; reg = <0 0xe6510000 0 0x40>;
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 929>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 929>;
dmas = <&dmac1 0x95>, <&dmac1 0x94>,
<&dmac2 0x95>, <&dmac2 0x94>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
}; };
ipmmu_vc0: mmu@fe6b0000 { i2c3: i2c@e66d0000 {
compatible = "renesas,ipmmu-r8a7795"; #address-cells = <1>;
reg = <0 0xfe6b0000 0 0x1000>; #size-cells = <0>;
renesas,ipmmu-main = <&ipmmu_mm 12>; compatible = "renesas,i2c-r8a7795",
power-domains = <&sysc R8A7795_PD_A3VC>; "renesas,rcar-gen3-i2c";
#iommu-cells = <1>; reg = <0 0xe66d0000 0 0x40>;
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 928>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 928>;
dmas = <&dmac0 0x97>, <&dmac0 0x96>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
status = "disabled"; status = "disabled";
}; };
ipmmu_vc1: mmu@fe6f0000 { i2c4: i2c@e66d8000 {
compatible = "renesas,ipmmu-r8a7795"; #address-cells = <1>;
reg = <0 0xfe6f0000 0 0x1000>; #size-cells = <0>;
renesas,ipmmu-main = <&ipmmu_mm 13>; compatible = "renesas,i2c-r8a7795",
power-domains = <&sysc R8A7795_PD_A3VC>; "renesas,rcar-gen3-i2c";
#iommu-cells = <1>; reg = <0 0xe66d8000 0 0x40>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 927>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 927>;
dmas = <&dmac0 0x99>, <&dmac0 0x98>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
status = "disabled"; status = "disabled";
}; };
ipmmu_pv0: mmu@fd800000 { i2c5: i2c@e66e0000 {
compatible = "renesas,ipmmu-r8a7795"; #address-cells = <1>;
reg = <0 0xfd800000 0 0x1000>; #size-cells = <0>;
renesas,ipmmu-main = <&ipmmu_mm 6>; compatible = "renesas,i2c-r8a7795",
"renesas,rcar-gen3-i2c";
reg = <0 0xe66e0000 0 0x40>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 919>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>; resets = <&cpg 919>;
dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
status = "disabled"; status = "disabled";
}; };
ipmmu_pv1: mmu@fd950000 { i2c6: i2c@e66e8000 {
compatible = "renesas,ipmmu-r8a7795"; #address-cells = <1>;
reg = <0 0xfd950000 0 0x1000>; #size-cells = <0>;
renesas,ipmmu-main = <&ipmmu_mm 7>; compatible = "renesas,i2c-r8a7795",
"renesas,rcar-gen3-i2c";
reg = <0 0xe66e8000 0 0x40>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 918>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>; resets = <&cpg 918>;
dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled"; status = "disabled";
}; };
ipmmu_pv2: mmu@fd960000 { i2c_dvfs: i2c@e60b0000 {
compatible = "renesas,ipmmu-r8a7795"; #address-cells = <1>;
reg = <0 0xfd960000 0 0x1000>; #size-cells = <0>;
renesas,ipmmu-main = <&ipmmu_mm 8>; compatible = "renesas,iic-r8a7795",
"renesas,rcar-gen3-iic",
"renesas,rmobile-iic";
reg = <0 0xe60b0000 0 0x425>;
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 926>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>; resets = <&cpg 926>;
dmas = <&dmac0 0x11>, <&dmac0 0x10>;
dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
}; };
ipmmu_pv3: mmu@fd970000 { hscif0: serial@e6540000 {
compatible = "renesas,ipmmu-r8a7795"; compatible = "renesas,hscif-r8a7795",
reg = <0 0xfd970000 0 0x1000>; "renesas,rcar-gen3-hscif",
renesas,ipmmu-main = <&ipmmu_mm 9>; "renesas,hscif";
reg = <0 0xe6540000 0 96>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 520>,
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x31>, <&dmac1 0x30>,
<&dmac2 0x31>, <&dmac2 0x30>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>; resets = <&cpg 520>;
status = "disabled"; status = "disabled";
}; };
ipmmu_ir: mmu@ff8b0000 { hscif1: serial@e6550000 {
compatible = "renesas,ipmmu-r8a7795"; compatible = "renesas,hscif-r8a7795",
reg = <0 0xff8b0000 0 0x1000>; "renesas,rcar-gen3-hscif",
renesas,ipmmu-main = <&ipmmu_mm 3>; "renesas,hscif";
power-domains = <&sysc R8A7795_PD_A3IR>; reg = <0 0xe6550000 0 96>;
#iommu-cells = <1>; interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 519>,
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x33>, <&dmac1 0x32>,
<&dmac2 0x33>, <&dmac2 0x32>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 519>;
status = "disabled"; status = "disabled";
}; };
ipmmu_hc: mmu@e6570000 { hscif2: serial@e6560000 {
compatible = "renesas,ipmmu-r8a7795"; compatible = "renesas,hscif-r8a7795",
reg = <0 0xe6570000 0 0x1000>; "renesas,rcar-gen3-hscif",
renesas,ipmmu-main = <&ipmmu_mm 2>; "renesas,hscif";
reg = <0 0xe6560000 0 96>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 518>,
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x35>, <&dmac1 0x34>,
<&dmac2 0x35>, <&dmac2 0x34>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>; resets = <&cpg 518>;
status = "disabled"; status = "disabled";
}; };
ipmmu_rt: mmu@ffc80000 { hscif3: serial@e66a0000 {
compatible = "renesas,ipmmu-r8a7795"; compatible = "renesas,hscif-r8a7795",
reg = <0 0xffc80000 0 0x1000>; "renesas,rcar-gen3-hscif",
renesas,ipmmu-main = <&ipmmu_mm 10>; "renesas,hscif";
reg = <0 0xe66a0000 0 96>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 517>,
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x37>, <&dmac0 0x36>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>; resets = <&cpg 517>;
status = "disabled"; status = "disabled";
}; };
ipmmu_mp0: mmu@ec670000 { hscif4: serial@e66b0000 {
compatible = "renesas,ipmmu-r8a7795"; compatible = "renesas,hscif-r8a7795",
reg = <0 0xec670000 0 0x1000>; "renesas,rcar-gen3-hscif",
renesas,ipmmu-main = <&ipmmu_mm 4>; "renesas,hscif";
reg = <0 0xe66b0000 0 96>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 516>,
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x39>, <&dmac0 0x38>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>; resets = <&cpg 516>;
status = "disabled"; status = "disabled";
}; };
ipmmu_ds0: mmu@e6740000 { hsusb: usb@e6590000 {
compatible = "renesas,ipmmu-r8a7795"; compatible = "renesas,usbhs-r8a7795",
reg = <0 0xe6740000 0 0x1000>; "renesas,rcar-gen3-usbhs";
renesas,ipmmu-main = <&ipmmu_mm 0>; reg = <0 0xe6590000 0 0x100>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 704>;
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
<&usb_dmac1 0>, <&usb_dmac1 1>;
dma-names = "ch0", "ch1", "ch2", "ch3";
renesas,buswait = <11>;
phys = <&usb2_phy0>;
phy-names = "usb";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>; resets = <&cpg 704>;
status = "disabled";
}; };
ipmmu_ds1: mmu@e7740000 { hsusb3: usb@e659c000 {
compatible = "renesas,ipmmu-r8a7795"; compatible = "renesas,usbhs-r8a7795",
reg = <0 0xe7740000 0 0x1000>; "renesas,rcar-gen3-usbhs";
renesas,ipmmu-main = <&ipmmu_mm 1>; reg = <0 0xe659c000 0 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 705>;
dmas = <&usb_dmac2 0>, <&usb_dmac2 1>,
<&usb_dmac3 0>, <&usb_dmac3 1>;
dma-names = "ch0", "ch1", "ch2", "ch3";
renesas,buswait = <11>;
phys = <&usb2_phy3>;
phy-names = "usb";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>; resets = <&cpg 705>;
status = "disabled";
}; };
ipmmu_mm: mmu@e67b0000 { usb_dmac0: dma-controller@e65a0000 {
compatible = "renesas,ipmmu-r8a7795"; compatible = "renesas,r8a7795-usb-dmac",
reg = <0 0xe67b0000 0 0x1000>; "renesas,usb-dmac";
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, reg = <0 0xe65a0000 0 0x100>;
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 330>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>; resets = <&cpg 330>;
#dma-cells = <1>;
dma-channels = <2>;
};
usb_dmac1: dma-controller@e65b0000 {
compatible = "renesas,r8a7795-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65b0000 0 0x100>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 331>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 331>;
#dma-cells = <1>;
dma-channels = <2>;
};
usb_dmac2: dma-controller@e6460000 {
compatible = "renesas,r8a7795-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe6460000 0 0x100>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 326>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 326>;
#dma-cells = <1>;
dma-channels = <2>;
};
usb_dmac3: dma-controller@e6470000 {
compatible = "renesas,r8a7795-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe6470000 0 0x100>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 329>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 329>;
#dma-cells = <1>;
dma-channels = <2>;
};
usb3_phy0: usb-phy@e65ee000 {
compatible = "renesas,r8a7795-usb3-phy",
"renesas,rcar-gen3-usb3-phy";
reg = <0 0xe65ee000 0 0x90>;
clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
<&usb_extal_clk>;
clock-names = "usb3-if", "usb3s_clk", "usb_extal";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 328>;
#phy-cells = <0>;
status = "disabled";
}; };
dmac0: dma-controller@e6700000 { dmac0: dma-controller@e6700000 {
...@@ -759,155 +925,208 @@ GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH ...@@ -759,155 +925,208 @@ GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
<&ipmmu_ds1 30>, <&ipmmu_ds1 31>; <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
}; };
audma0: dma-controller@ec700000 { ipmmu_ds0: mmu@e6740000 {
compatible = "renesas,dmac-r8a7795", compatible = "renesas,ipmmu-r8a7795";
"renesas,rcar-dmac"; reg = <0 0xe6740000 0 0x1000>;
reg = <0 0xec700000 0 0x10000>; renesas,ipmmu-main = <&ipmmu_mm 0>;
interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 502>;
clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 502>; #iommu-cells = <1>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>,
<&ipmmu_mp0 2>, <&ipmmu_mp0 3>,
<&ipmmu_mp0 4>, <&ipmmu_mp0 5>,
<&ipmmu_mp0 6>, <&ipmmu_mp0 7>,
<&ipmmu_mp0 8>, <&ipmmu_mp0 9>,
<&ipmmu_mp0 10>, <&ipmmu_mp0 11>,
<&ipmmu_mp0 12>, <&ipmmu_mp0 13>,
<&ipmmu_mp0 14>, <&ipmmu_mp0 15>;
}; };
audma1: dma-controller@ec720000 { ipmmu_ds1: mmu@e7740000 {
compatible = "renesas,dmac-r8a7795", compatible = "renesas,ipmmu-r8a7795";
"renesas,rcar-dmac"; reg = <0 0xe7740000 0 0x1000>;
reg = <0 0xec720000 0 0x10000>; renesas,ipmmu-main = <&ipmmu_mm 1>;
interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 501>;
clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 501>; #iommu-cells = <1>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>,
<&ipmmu_mp0 18>, <&ipmmu_mp0 19>,
<&ipmmu_mp0 20>, <&ipmmu_mp0 21>,
<&ipmmu_mp0 22>, <&ipmmu_mp0 23>,
<&ipmmu_mp0 24>, <&ipmmu_mp0 25>,
<&ipmmu_mp0 26>, <&ipmmu_mp0 27>,
<&ipmmu_mp0 28>, <&ipmmu_mp0 29>,
<&ipmmu_mp0 30>, <&ipmmu_mp0 31>;
}; };
avb: ethernet@e6800000 { ipmmu_hc: mmu@e6570000 {
compatible = "renesas,etheravb-r8a7795", compatible = "renesas,ipmmu-r8a7795";
"renesas,etheravb-rcar-gen3"; reg = <0 0xe6570000 0 0x1000>;
reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; renesas,ipmmu-main = <&ipmmu_mm 2>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15",
"ch16", "ch17", "ch18", "ch19",
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 812>; #iommu-cells = <1>;
phy-mode = "rgmii";
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
}; };
can0: can@e6c30000 { ipmmu_ir: mmu@ff8b0000 {
compatible = "renesas,can-r8a7795", compatible = "renesas,ipmmu-r8a7795";
"renesas,rcar-gen3-can"; reg = <0 0xff8b0000 0 0x1000>;
reg = <0 0xe6c30000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 3>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&sysc R8A7795_PD_A3IR>;
clocks = <&cpg CPG_MOD 916>, #iommu-cells = <1>;
<&cpg CPG_CORE R8A7795_CLK_CANFD>, };
<&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk"; ipmmu_mm: mmu@e67b0000 {
assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; compatible = "renesas,ipmmu-r8a7795";
assigned-clock-rates = <40000000>; reg = <0 0xe67b0000 0 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 916>; #iommu-cells = <1>;
status = "disabled";
}; };
can1: can@e6c38000 { ipmmu_mp0: mmu@ec670000 {
compatible = "renesas,can-r8a7795", compatible = "renesas,ipmmu-r8a7795";
"renesas,rcar-gen3-can"; reg = <0 0xec670000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 4>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_pv0: mmu@fd800000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfd800000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 6>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_pv1: mmu@fd950000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfd950000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 7>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_pv2: mmu@fd960000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfd960000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 8>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_pv3: mmu@fd970000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfd970000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 9>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_rt: mmu@ffc80000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xffc80000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 10>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_vc0: mmu@fe6b0000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfe6b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 12>;
power-domains = <&sysc R8A7795_PD_A3VC>;
#iommu-cells = <1>;
};
ipmmu_vc1: mmu@fe6f0000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfe6f0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 13>;
power-domains = <&sysc R8A7795_PD_A3VC>;
#iommu-cells = <1>;
};
ipmmu_vi0: mmu@febd0000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfebd0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 14>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_vi1: mmu@febe0000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfebe0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 15>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_vp0: mmu@fe990000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfe990000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 16>;
power-domains = <&sysc R8A7795_PD_A3VP>;
#iommu-cells = <1>;
};
ipmmu_vp1: mmu@fe980000 {
compatible = "renesas,ipmmu-r8a7795";
reg = <0 0xfe980000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 17>;
power-domains = <&sysc R8A7795_PD_A3VP>;
#iommu-cells = <1>;
};
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a7795",
"renesas,etheravb-rcar-gen3";
reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15",
"ch16", "ch17", "ch18", "ch19",
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
can0: can@e6c30000 {
compatible = "renesas,can-r8a7795",
"renesas,rcar-gen3-can";
reg = <0 0xe6c30000 0 0x1000>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 916>,
<&cpg CPG_CORE R8A7795_CLK_CANFD>,
<&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 916>;
status = "disabled";
};
can1: can@e6c38000 {
compatible = "renesas,can-r8a7795",
"renesas,rcar-gen3-can";
reg = <0 0xe6c38000 0 0x1000>; reg = <0 0xe6c38000 0 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 915>, clocks = <&cpg CPG_MOD 915>,
...@@ -946,211 +1165,173 @@ channel1 { ...@@ -946,211 +1165,173 @@ channel1 {
}; };
}; };
drif00: rif@e6f40000 { pwm0: pwm@e6e30000 {
compatible = "renesas,r8a7795-drif", compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
"renesas,rcar-gen3-drif"; reg = <0 0xe6e30000 0 0x8>;
reg = <0 0xe6f40000 0 0x64>; clocks = <&cpg CPG_MOD 523>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 515>;
clock-names = "fck";
dmas = <&dmac1 0x20>, <&dmac2 0x20>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 515>; resets = <&cpg 523>;
renesas,bonding = <&drif01>; #pwm-cells = <2>;
status = "disabled"; status = "disabled";
}; };
drif01: rif@e6f50000 { pwm1: pwm@e6e31000 {
compatible = "renesas,r8a7795-drif", compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
"renesas,rcar-gen3-drif"; reg = <0 0xe6e31000 0 0x8>;
reg = <0 0xe6f50000 0 0x64>; clocks = <&cpg CPG_MOD 523>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 514>;
clock-names = "fck";
dmas = <&dmac1 0x22>, <&dmac2 0x22>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 514>; resets = <&cpg 523>;
renesas,bonding = <&drif00>; #pwm-cells = <2>;
status = "disabled"; status = "disabled";
}; };
drif10: rif@e6f60000 { pwm2: pwm@e6e32000 {
compatible = "renesas,r8a7795-drif", compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
"renesas,rcar-gen3-drif"; reg = <0 0xe6e32000 0 0x8>;
reg = <0 0xe6f60000 0 0x64>; clocks = <&cpg CPG_MOD 523>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 513>;
clock-names = "fck";
dmas = <&dmac1 0x24>, <&dmac2 0x24>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 513>; resets = <&cpg 523>;
renesas,bonding = <&drif11>; #pwm-cells = <2>;
status = "disabled"; status = "disabled";
}; };
drif11: rif@e6f70000 { pwm3: pwm@e6e33000 {
compatible = "renesas,r8a7795-drif", compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
"renesas,rcar-gen3-drif"; reg = <0 0xe6e33000 0 0x8>;
reg = <0 0xe6f70000 0 0x64>; clocks = <&cpg CPG_MOD 523>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 512>;
clock-names = "fck";
dmas = <&dmac1 0x26>, <&dmac2 0x26>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 512>; resets = <&cpg 523>;
renesas,bonding = <&drif10>; #pwm-cells = <2>;
status = "disabled"; status = "disabled";
}; };
drif20: rif@e6f80000 { pwm4: pwm@e6e34000 {
compatible = "renesas,r8a7795-drif", compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
"renesas,rcar-gen3-drif"; reg = <0 0xe6e34000 0 0x8>;
reg = <0 0xe6f80000 0 0x64>; clocks = <&cpg CPG_MOD 523>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 511>;
clock-names = "fck";
dmas = <&dmac1 0x28>, <&dmac2 0x28>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 511>; resets = <&cpg 523>;
renesas,bonding = <&drif21>; #pwm-cells = <2>;
status = "disabled"; status = "disabled";
}; };
drif21: rif@e6f90000 { pwm5: pwm@e6e35000 {
compatible = "renesas,r8a7795-drif", compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
"renesas,rcar-gen3-drif"; reg = <0 0xe6e35000 0 0x8>;
reg = <0 0xe6f90000 0 0x64>; clocks = <&cpg CPG_MOD 523>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
clocks = <&cpg CPG_MOD 510>; resets = <&cpg 523>;
clock-names = "fck"; #pwm-cells = <2>;
dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 510>;
renesas,bonding = <&drif20>;
status = "disabled"; status = "disabled";
}; };
drif30: rif@e6fa0000 { pwm6: pwm@e6e36000 {
compatible = "renesas,r8a7795-drif", compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";
"renesas,rcar-gen3-drif"; reg = <0 0xe6e36000 0 0x8>;
reg = <0 0xe6fa0000 0 0x64>; clocks = <&cpg CPG_MOD 523>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 509>;
clock-names = "fck";
dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 509>; resets = <&cpg 523>;
renesas,bonding = <&drif31>; #pwm-cells = <2>;
status = "disabled"; status = "disabled";
}; };
drif31: rif@e6fb0000 { scif0: serial@e6e60000 {
compatible = "renesas,r8a7795-drif", compatible = "renesas,scif-r8a7795",
"renesas,rcar-gen3-drif"; "renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6fb0000 0 0x64>; reg = <0 0xe6e60000 0 64>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 508>; clocks = <&cpg CPG_MOD 207>,
clock-names = "fck"; <&cpg CPG_CORE R8A7795_CLK_S3D1>,
dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; <&scif_clk>;
dma-names = "rx", "rx"; clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x51>, <&dmac1 0x50>,
<&dmac2 0x51>, <&dmac2 0x50>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 508>; resets = <&cpg 207>;
renesas,bonding = <&drif30>;
status = "disabled"; status = "disabled";
}; };
hscif0: serial@e6540000 { scif1: serial@e6e68000 {
compatible = "renesas,hscif-r8a7795", compatible = "renesas,scif-r8a7795",
"renesas,rcar-gen3-hscif", "renesas,rcar-gen3-scif", "renesas,scif";
"renesas,hscif"; reg = <0 0xe6e68000 0 64>;
reg = <0 0xe6540000 0 96>; interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 206>,
clocks = <&cpg CPG_MOD 520>,
<&cpg CPG_CORE R8A7795_CLK_S3D1>, <&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>; <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x31>, <&dmac1 0x30>, dmas = <&dmac1 0x53>, <&dmac1 0x52>,
<&dmac2 0x31>, <&dmac2 0x30>; <&dmac2 0x53>, <&dmac2 0x52>;
dma-names = "tx", "rx", "tx", "rx"; dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 520>; resets = <&cpg 206>;
status = "disabled"; status = "disabled";
}; };
hscif1: serial@e6550000 { scif2: serial@e6e88000 {
compatible = "renesas,hscif-r8a7795", compatible = "renesas,scif-r8a7795",
"renesas,rcar-gen3-hscif", "renesas,rcar-gen3-scif", "renesas,scif";
"renesas,hscif"; reg = <0 0xe6e88000 0 64>;
reg = <0 0xe6550000 0 96>; interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 310>,
clocks = <&cpg CPG_MOD 519>,
<&cpg CPG_CORE R8A7795_CLK_S3D1>, <&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>; <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x33>, <&dmac1 0x32>, dmas = <&dmac1 0x13>, <&dmac1 0x12>,
<&dmac2 0x33>, <&dmac2 0x32>; <&dmac2 0x13>, <&dmac2 0x12>;
dma-names = "tx", "rx", "tx", "rx"; dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 519>; resets = <&cpg 310>;
status = "disabled"; status = "disabled";
}; };
hscif2: serial@e6560000 { scif3: serial@e6c50000 {
compatible = "renesas,hscif-r8a7795", compatible = "renesas,scif-r8a7795",
"renesas,rcar-gen3-hscif", "renesas,rcar-gen3-scif", "renesas,scif";
"renesas,hscif"; reg = <0 0xe6c50000 0 64>;
reg = <0 0xe6560000 0 96>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 204>,
clocks = <&cpg CPG_MOD 518>,
<&cpg CPG_CORE R8A7795_CLK_S3D1>, <&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>; <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x35>, <&dmac1 0x34>, dmas = <&dmac0 0x57>, <&dmac0 0x56>;
<&dmac2 0x35>, <&dmac2 0x34>; dma-names = "tx", "rx";
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 518>; resets = <&cpg 204>;
status = "disabled"; status = "disabled";
}; };
hscif3: serial@e66a0000 { scif4: serial@e6c40000 {
compatible = "renesas,hscif-r8a7795", compatible = "renesas,scif-r8a7795",
"renesas,rcar-gen3-hscif", "renesas,rcar-gen3-scif", "renesas,scif";
"renesas,hscif"; reg = <0 0xe6c40000 0 64>;
reg = <0 0xe66a0000 0 96>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 203>,
clocks = <&cpg CPG_MOD 517>,
<&cpg CPG_CORE R8A7795_CLK_S3D1>, <&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>; <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x37>, <&dmac0 0x36>; dmas = <&dmac0 0x59>, <&dmac0 0x58>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 517>; resets = <&cpg 203>;
status = "disabled"; status = "disabled";
}; };
hscif4: serial@e66b0000 { scif5: serial@e6f30000 {
compatible = "renesas,hscif-r8a7795", compatible = "renesas,scif-r8a7795",
"renesas,rcar-gen3-hscif", "renesas,rcar-gen3-scif", "renesas,scif";
"renesas,hscif"; reg = <0 0xe6f30000 0 64>;
reg = <0 0xe66b0000 0 96>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 202>,
clocks = <&cpg CPG_MOD 516>,
<&cpg CPG_CORE R8A7795_CLK_S3D1>, <&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>; <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x39>, <&dmac0 0x38>; dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
dma-names = "tx", "rx"; <&dmac2 0x5b>, <&dmac2 0x5a>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 516>; resets = <&cpg 202>;
status = "disabled"; status = "disabled";
}; };
...@@ -1216,304 +1397,379 @@ msiof3: spi@e6c10000 { ...@@ -1216,304 +1397,379 @@ msiof3: spi@e6c10000 {
status = "disabled"; status = "disabled";
}; };
scif0: serial@e6e60000 { vin0: video@e6ef0000 {
compatible = "renesas,scif-r8a7795", compatible = "renesas,vin-r8a7795";
"renesas,rcar-gen3-scif", "renesas,scif"; reg = <0 0xe6ef0000 0 0x1000>;
reg = <0 0xe6e60000 0 64>; interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 811>;
clocks = <&cpg CPG_MOD 207>,
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x51>, <&dmac1 0x50>,
<&dmac2 0x51>, <&dmac2 0x50>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 207>; resets = <&cpg 811>;
renesas,id = <0>;
status = "disabled"; status = "disabled";
};
scif1: serial@e6e68000 { ports {
compatible = "renesas,scif-r8a7795", #address-cells = <1>;
"renesas,rcar-gen3-scif", "renesas,scif"; #size-cells = <0>;
reg = <0 0xe6e68000 0 64>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 206>,
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x53>, <&dmac1 0x52>,
<&dmac2 0x53>, <&dmac2 0x52>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 206>;
status = "disabled";
};
scif2: serial@e6e88000 { port@1 {
compatible = "renesas,scif-r8a7795", #address-cells = <1>;
"renesas,rcar-gen3-scif", "renesas,scif"; #size-cells = <0>;
reg = <0 0xe6e88000 0 64>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 310>,
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x13>, <&dmac1 0x12>,
<&dmac2 0x13>, <&dmac2 0x12>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 310>;
status = "disabled";
};
scif3: serial@e6c50000 { reg = <1>;
compatible = "renesas,scif-r8a7795",
"renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6c50000 0 64>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 204>,
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x57>, <&dmac0 0x56>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 204>;
status = "disabled";
};
scif4: serial@e6c40000 { vin0csi20: endpoint@0 {
compatible = "renesas,scif-r8a7795", reg = <0>;
"renesas,rcar-gen3-scif", "renesas,scif"; remote-endpoint= <&csi20vin0>;
reg = <0 0xe6c40000 0 64>; };
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; vin0csi40: endpoint@2 {
clocks = <&cpg CPG_MOD 203>, reg = <2>;
<&cpg CPG_CORE R8A7795_CLK_S3D1>, remote-endpoint= <&csi40vin0>;
<&scif_clk>; };
clock-names = "fck", "brg_int", "scif_clk"; };
dmas = <&dmac0 0x59>, <&dmac0 0x58>; };
dma-names = "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 203>;
status = "disabled";
}; };
scif5: serial@e6f30000 { vin1: video@e6ef1000 {
compatible = "renesas,scif-r8a7795", compatible = "renesas,vin-r8a7795";
"renesas,rcar-gen3-scif", "renesas,scif"; reg = <0 0xe6ef1000 0 0x1000>;
reg = <0 0xe6f30000 0 64>; interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 810>;
clocks = <&cpg CPG_MOD 202>,
<&cpg CPG_CORE R8A7795_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
<&dmac2 0x5b>, <&dmac2 0x5a>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 202>; resets = <&cpg 810>;
renesas,id = <1>;
status = "disabled"; status = "disabled";
};
i2c_dvfs: i2c@e60b0000 { ports {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "renesas,iic-r8a7795",
"renesas,rcar-gen3-iic", port@1 {
"renesas,rmobile-iic"; #address-cells = <1>;
reg = <0 0xe60b0000 0 0x425>; #size-cells = <0>;
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 926>; reg = <1>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 926>; vin1csi20: endpoint@0 {
dmas = <&dmac0 0x11>, <&dmac0 0x10>; reg = <0>;
dma-names = "tx", "rx"; remote-endpoint= <&csi20vin1>;
status = "disabled"; };
vin1csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin1>;
};
};
};
}; };
i2c0: i2c@e6500000 { vin2: video@e6ef2000 {
#address-cells = <1>; compatible = "renesas,vin-r8a7795";
#size-cells = <0>; reg = <0 0xe6ef2000 0 0x1000>;
compatible = "renesas,i2c-r8a7795", interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
"renesas,rcar-gen3-i2c"; clocks = <&cpg CPG_MOD 809>;
reg = <0 0xe6500000 0 0x40>;
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 931>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 931>; resets = <&cpg 809>;
dmas = <&dmac1 0x91>, <&dmac1 0x90>, renesas,id = <2>;
<&dmac2 0x91>, <&dmac2 0x90>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
status = "disabled"; status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin2csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin2>;
};
vin2csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin2>;
};
};
};
}; };
i2c1: i2c@e6508000 { vin3: video@e6ef3000 {
#address-cells = <1>; compatible = "renesas,vin-r8a7795";
#size-cells = <0>; reg = <0 0xe6ef3000 0 0x1000>;
compatible = "renesas,i2c-r8a7795", interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
"renesas,rcar-gen3-i2c"; clocks = <&cpg CPG_MOD 808>;
reg = <0 0xe6508000 0 0x40>;
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 930>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 930>; resets = <&cpg 808>;
dmas = <&dmac1 0x93>, <&dmac1 0x92>, renesas,id = <3>;
<&dmac2 0x93>, <&dmac2 0x92>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled"; status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin3csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin3>;
};
vin3csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin3>;
};
};
};
}; };
i2c2: i2c@e6510000 { vin4: video@e6ef4000 {
#address-cells = <1>; compatible = "renesas,vin-r8a7795";
#size-cells = <0>; reg = <0 0xe6ef4000 0 0x1000>;
compatible = "renesas,i2c-r8a7795", interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
"renesas,rcar-gen3-i2c"; clocks = <&cpg CPG_MOD 807>;
reg = <0 0xe6510000 0 0x40>;
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 929>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 929>; resets = <&cpg 807>;
dmas = <&dmac1 0x95>, <&dmac1 0x94>, renesas,id = <4>;
<&dmac2 0x95>, <&dmac2 0x94>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled"; status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin4csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin4>;
};
vin4csi41: endpoint@3 {
reg = <3>;
remote-endpoint= <&csi41vin4>;
};
};
};
}; };
i2c3: i2c@e66d0000 { vin5: video@e6ef5000 {
#address-cells = <1>; compatible = "renesas,vin-r8a7795";
#size-cells = <0>; reg = <0 0xe6ef5000 0 0x1000>;
compatible = "renesas,i2c-r8a7795", interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
"renesas,rcar-gen3-i2c"; clocks = <&cpg CPG_MOD 806>;
reg = <0 0xe66d0000 0 0x40>;
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 928>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 928>; resets = <&cpg 806>;
dmas = <&dmac0 0x97>, <&dmac0 0x96>; renesas,id = <5>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
status = "disabled"; status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin5csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin5>;
};
vin5csi41: endpoint@3 {
reg = <3>;
remote-endpoint= <&csi41vin5>;
};
};
};
}; };
i2c4: i2c@e66d8000 { vin6: video@e6ef6000 {
#address-cells = <1>; compatible = "renesas,vin-r8a7795";
#size-cells = <0>; reg = <0 0xe6ef6000 0 0x1000>;
compatible = "renesas,i2c-r8a7795", interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
"renesas,rcar-gen3-i2c"; clocks = <&cpg CPG_MOD 805>;
reg = <0 0xe66d8000 0 0x40>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 927>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 927>; resets = <&cpg 805>;
dmas = <&dmac0 0x99>, <&dmac0 0x98>; renesas,id = <6>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
status = "disabled"; status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin6csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin6>;
};
vin6csi41: endpoint@3 {
reg = <3>;
remote-endpoint= <&csi41vin6>;
};
};
};
}; };
i2c5: i2c@e66e0000 { vin7: video@e6ef7000 {
#address-cells = <1>; compatible = "renesas,vin-r8a7795";
#size-cells = <0>; reg = <0 0xe6ef7000 0 0x1000>;
compatible = "renesas,i2c-r8a7795", interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
"renesas,rcar-gen3-i2c"; clocks = <&cpg CPG_MOD 804>;
reg = <0 0xe66e0000 0 0x40>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 919>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 919>; resets = <&cpg 804>;
dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; renesas,id = <7>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
status = "disabled"; status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin7csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin7>;
};
vin7csi41: endpoint@3 {
reg = <3>;
remote-endpoint= <&csi41vin7>;
};
};
};
}; };
i2c6: i2c@e66e8000 { drif00: rif@e6f40000 {
#address-cells = <1>; compatible = "renesas,r8a7795-drif",
#size-cells = <0>; "renesas,rcar-gen3-drif";
compatible = "renesas,i2c-r8a7795", reg = <0 0xe6f40000 0 0x64>;
"renesas,rcar-gen3-i2c"; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0xe66e8000 0 0x40>; clocks = <&cpg CPG_MOD 515>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; clock-names = "fck";
clocks = <&cpg CPG_MOD 918>; dmas = <&dmac1 0x20>, <&dmac2 0x20>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 918>; resets = <&cpg 515>;
dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; renesas,bonding = <&drif01>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled"; status = "disabled";
}; };
pwm0: pwm@e6e30000 { drif01: rif@e6f50000 {
compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; compatible = "renesas,r8a7795-drif",
reg = <0 0xe6e30000 0 0x8>; "renesas,rcar-gen3-drif";
clocks = <&cpg CPG_MOD 523>; reg = <0 0xe6f50000 0 0x64>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 514>;
clock-names = "fck";
dmas = <&dmac1 0x22>, <&dmac2 0x22>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 523>; resets = <&cpg 514>;
#pwm-cells = <2>; renesas,bonding = <&drif00>;
status = "disabled"; status = "disabled";
}; };
pwm1: pwm@e6e31000 { drif10: rif@e6f60000 {
compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; compatible = "renesas,r8a7795-drif",
reg = <0 0xe6e31000 0 0x8>; "renesas,rcar-gen3-drif";
clocks = <&cpg CPG_MOD 523>; reg = <0 0xe6f60000 0 0x64>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 513>;
clock-names = "fck";
dmas = <&dmac1 0x24>, <&dmac2 0x24>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 523>; resets = <&cpg 513>;
#pwm-cells = <2>; renesas,bonding = <&drif11>;
status = "disabled"; status = "disabled";
}; };
pwm2: pwm@e6e32000 { drif11: rif@e6f70000 {
compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; compatible = "renesas,r8a7795-drif",
reg = <0 0xe6e32000 0 0x8>; "renesas,rcar-gen3-drif";
clocks = <&cpg CPG_MOD 523>; reg = <0 0xe6f70000 0 0x64>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 512>;
clock-names = "fck";
dmas = <&dmac1 0x26>, <&dmac2 0x26>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 523>; resets = <&cpg 512>;
#pwm-cells = <2>; renesas,bonding = <&drif10>;
status = "disabled"; status = "disabled";
}; };
pwm3: pwm@e6e33000 { drif20: rif@e6f80000 {
compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; compatible = "renesas,r8a7795-drif",
reg = <0 0xe6e33000 0 0x8>; "renesas,rcar-gen3-drif";
clocks = <&cpg CPG_MOD 523>; reg = <0 0xe6f80000 0 0x64>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 511>;
clock-names = "fck";
dmas = <&dmac1 0x28>, <&dmac2 0x28>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 523>; resets = <&cpg 511>;
#pwm-cells = <2>; renesas,bonding = <&drif21>;
status = "disabled"; status = "disabled";
}; };
pwm4: pwm@e6e34000 { drif21: rif@e6f90000 {
compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; compatible = "renesas,r8a7795-drif",
reg = <0 0xe6e34000 0 0x8>; "renesas,rcar-gen3-drif";
clocks = <&cpg CPG_MOD 523>; reg = <0 0xe6f90000 0 0x64>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 510>;
clock-names = "fck";
dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 523>; resets = <&cpg 510>;
#pwm-cells = <2>; renesas,bonding = <&drif20>;
status = "disabled"; status = "disabled";
}; };
pwm5: pwm@e6e35000 { drif30: rif@e6fa0000 {
compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; compatible = "renesas,r8a7795-drif",
reg = <0 0xe6e35000 0 0x8>; "renesas,rcar-gen3-drif";
clocks = <&cpg CPG_MOD 523>; reg = <0 0xe6fa0000 0 0x64>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 509>;
clock-names = "fck";
dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 523>; resets = <&cpg 509>;
#pwm-cells = <2>; renesas,bonding = <&drif31>;
status = "disabled"; status = "disabled";
}; };
pwm6: pwm@e6e36000 { drif31: rif@e6fb0000 {
compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; compatible = "renesas,r8a7795-drif",
reg = <0 0xe6e36000 0 0x8>; "renesas,rcar-gen3-drif";
clocks = <&cpg CPG_MOD 523>; reg = <0 0xe6fb0000 0 0x64>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 508>;
clock-names = "fck";
dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 523>; resets = <&cpg 508>;
#pwm-cells = <2>; renesas,bonding = <&drif30>;
status = "disabled"; status = "disabled";
}; };
...@@ -1711,201 +1967,172 @@ ssi9: ssi-9 { ...@@ -1711,201 +1967,172 @@ ssi9: ssi-9 {
dma-names = "rx", "tx", "rxu", "txu"; dma-names = "rx", "tx", "rxu", "txu";
}; };
}; };
};
sata: sata@ee300000 {
compatible = "renesas,sata-r8a7795",
"renesas,rcar-gen3-sata";
reg = <0 0xee300000 0 0x200000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 815>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 815>;
status = "disabled";
iommus = <&ipmmu_hc 2>;
};
usb3_phy0: usb-phy@e65ee000 {
compatible = "renesas,r8a7795-usb3-phy",
"renesas,rcar-gen3-usb3-phy";
reg = <0 0xe65ee000 0 0x90>;
clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
<&usb_extal_clk>;
clock-names = "usb3-if", "usb3s_clk", "usb_extal";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 328>;
#phy-cells = <0>;
status = "disabled";
};
xhci0: usb@ee000000 {
compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci";
reg = <0 0xee000000 0 0xc00>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 328>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 328>;
status = "disabled";
};
usb3_peri0: usb@ee020000 {
compatible = "renesas,r8a7795-usb3-peri",
"renesas,rcar-gen3-usb3-peri";
reg = <0 0xee020000 0 0x400>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 328>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 328>;
status = "disabled";
};
usb_dmac0: dma-controller@e65a0000 {
compatible = "renesas,r8a7795-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65a0000 0 0x100>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 330>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 330>;
#dma-cells = <1>;
dma-channels = <2>;
};
usb_dmac1: dma-controller@e65b0000 { ports {
compatible = "renesas,r8a7795-usb-dmac", #address-cells = <1>;
"renesas,usb-dmac"; #size-cells = <0>;
reg = <0 0xe65b0000 0 0x100>; port@0 {
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH reg = <0>;
GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; };
interrupt-names = "ch0", "ch1"; port@1 {
clocks = <&cpg CPG_MOD 331>; reg = <1>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; };
resets = <&cpg 331>; port@2 {
#dma-cells = <1>; reg = <2>;
dma-channels = <2>; };
};
}; };
usb_dmac2: dma-controller@e6460000 { audma0: dma-controller@ec700000 {
compatible = "renesas,r8a7795-usb-dmac", compatible = "renesas,dmac-r8a7795",
"renesas,usb-dmac"; "renesas,rcar-dmac";
reg = <0 0xe6460000 0 0x100>; reg = <0 0xec700000 0 0x10000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
interrupt-names = "ch0", "ch1"; GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
clocks = <&cpg CPG_MOD 326>; GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 502>;
clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 326>; resets = <&cpg 502>;
#dma-cells = <1>; #dma-cells = <1>;
dma-channels = <2>; dma-channels = <16>;
iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>,
<&ipmmu_mp0 2>, <&ipmmu_mp0 3>,
<&ipmmu_mp0 4>, <&ipmmu_mp0 5>,
<&ipmmu_mp0 6>, <&ipmmu_mp0 7>,
<&ipmmu_mp0 8>, <&ipmmu_mp0 9>,
<&ipmmu_mp0 10>, <&ipmmu_mp0 11>,
<&ipmmu_mp0 12>, <&ipmmu_mp0 13>,
<&ipmmu_mp0 14>, <&ipmmu_mp0 15>;
}; };
usb_dmac3: dma-controller@e6470000 { audma1: dma-controller@ec720000 {
compatible = "renesas,r8a7795-usb-dmac", compatible = "renesas,dmac-r8a7795",
"renesas,usb-dmac"; "renesas,rcar-dmac";
reg = <0 0xe6470000 0 0x100>; reg = <0 0xec720000 0 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
interrupt-names = "ch0", "ch1"; GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
clocks = <&cpg CPG_MOD 329>; GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 501>;
clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 329>; resets = <&cpg 501>;
#dma-cells = <1>; #dma-cells = <1>;
dma-channels = <2>; dma-channels = <16>;
}; iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>,
<&ipmmu_mp0 18>, <&ipmmu_mp0 19>,
sdhi0: sd@ee100000 { <&ipmmu_mp0 20>, <&ipmmu_mp0 21>,
compatible = "renesas,sdhi-r8a7795", <&ipmmu_mp0 22>, <&ipmmu_mp0 23>,
"renesas,rcar-gen3-sdhi"; <&ipmmu_mp0 24>, <&ipmmu_mp0 25>,
reg = <0 0xee100000 0 0x2000>; <&ipmmu_mp0 26>, <&ipmmu_mp0 27>,
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; <&ipmmu_mp0 28>, <&ipmmu_mp0 29>,
clocks = <&cpg CPG_MOD 314>; <&ipmmu_mp0 30>, <&ipmmu_mp0 31>;
max-frequency = <200000000>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 314>;
status = "disabled";
};
sdhi1: sd@ee120000 {
compatible = "renesas,sdhi-r8a7795",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 313>;
max-frequency = <200000000>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 313>;
status = "disabled";
}; };
sdhi2: sd@ee140000 { xhci0: usb@ee000000 {
compatible = "renesas,sdhi-r8a7795", compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci";
"renesas,rcar-gen3-sdhi"; reg = <0 0xee000000 0 0xc00>;
reg = <0 0xee140000 0 0x2000>; interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 328>;
clocks = <&cpg CPG_MOD 312>;
max-frequency = <200000000>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 312>; resets = <&cpg 328>;
status = "disabled"; status = "disabled";
}; };
sdhi3: sd@ee160000 { usb3_peri0: usb@ee020000 {
compatible = "renesas,sdhi-r8a7795", compatible = "renesas,r8a7795-usb3-peri",
"renesas,rcar-gen3-sdhi"; "renesas,rcar-gen3-usb3-peri";
reg = <0 0xee160000 0 0x2000>; reg = <0 0xee020000 0 0x400>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>; clocks = <&cpg CPG_MOD 328>;
max-frequency = <200000000>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 311>; resets = <&cpg 328>;
status = "disabled"; status = "disabled";
}; };
usb2_phy0: usb-phy@ee080200 { ohci0: usb@ee080000 {
compatible = "renesas,usb2-phy-r8a7795", compatible = "generic-ohci";
"renesas,rcar-gen3-usb2-phy"; reg = <0 0xee080000 0 0x100>;
reg = <0 0xee080200 0 0x700>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>; clocks = <&cpg CPG_MOD 703>;
phys = <&usb2_phy0>;
phy-names = "usb";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 703>; resets = <&cpg 703>;
#phy-cells = <0>;
status = "disabled"; status = "disabled";
}; };
usb2_phy1: usb-phy@ee0a0200 { ohci1: usb@ee0a0000 {
compatible = "renesas,usb2-phy-r8a7795", compatible = "generic-ohci";
"renesas,rcar-gen3-usb2-phy"; reg = <0 0xee0a0000 0 0x100>;
reg = <0 0xee0a0200 0 0x700>; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 702>; clocks = <&cpg CPG_MOD 702>;
phys = <&usb2_phy1>;
phy-names = "usb";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 702>; resets = <&cpg 702>;
#phy-cells = <0>;
status = "disabled"; status = "disabled";
}; };
usb2_phy2: usb-phy@ee0c0200 { ohci2: usb@ee0c0000 {
compatible = "renesas,usb2-phy-r8a7795", compatible = "generic-ohci";
"renesas,rcar-gen3-usb2-phy"; reg = <0 0xee0c0000 0 0x100>;
reg = <0 0xee0c0200 0 0x700>; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 701>; clocks = <&cpg CPG_MOD 701>;
phys = <&usb2_phy2>;
phy-names = "usb";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 701>; resets = <&cpg 701>;
#phy-cells = <0>;
status = "disabled"; status = "disabled";
}; };
usb2_phy3: usb-phy@ee0e0200 { ohci3: usb@ee0e0000 {
compatible = "renesas,usb2-phy-r8a7795", compatible = "generic-ohci";
"renesas,rcar-gen3-usb2-phy"; reg = <0 0xee0e0000 0 0x100>;
reg = <0 0xee0e0200 0 0x700>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 700>; clocks = <&cpg CPG_MOD 700>;
phys = <&usb2_phy3>;
phy-names = "usb";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 700>; resets = <&cpg 700>;
#phy-cells = <0>;
status = "disabled"; status = "disabled";
}; };
...@@ -1961,88 +2188,129 @@ ehci3: usb@ee0e0100 { ...@@ -1961,88 +2188,129 @@ ehci3: usb@ee0e0100 {
status = "disabled"; status = "disabled";
}; };
ohci0: usb@ee080000 { usb2_phy0: usb-phy@ee080200 {
compatible = "generic-ohci"; compatible = "renesas,usb2-phy-r8a7795",
reg = <0 0xee080000 0 0x100>; "renesas,rcar-gen3-usb2-phy";
reg = <0 0xee080200 0 0x700>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>; clocks = <&cpg CPG_MOD 703>;
phys = <&usb2_phy0>;
phy-names = "usb";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 703>; resets = <&cpg 703>;
#phy-cells = <0>;
status = "disabled"; status = "disabled";
}; };
ohci1: usb@ee0a0000 { usb2_phy1: usb-phy@ee0a0200 {
compatible = "generic-ohci"; compatible = "renesas,usb2-phy-r8a7795",
reg = <0 0xee0a0000 0 0x100>; "renesas,rcar-gen3-usb2-phy";
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; reg = <0 0xee0a0200 0 0x700>;
clocks = <&cpg CPG_MOD 702>; clocks = <&cpg CPG_MOD 702>;
phys = <&usb2_phy1>;
phy-names = "usb";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 702>; resets = <&cpg 702>;
#phy-cells = <0>;
status = "disabled"; status = "disabled";
}; };
ohci2: usb@ee0c0000 { usb2_phy2: usb-phy@ee0c0200 {
compatible = "generic-ohci"; compatible = "renesas,usb2-phy-r8a7795",
reg = <0 0xee0c0000 0 0x100>; "renesas,rcar-gen3-usb2-phy";
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; reg = <0 0xee0c0200 0 0x700>;
clocks = <&cpg CPG_MOD 701>; clocks = <&cpg CPG_MOD 701>;
phys = <&usb2_phy2>;
phy-names = "usb";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 701>; resets = <&cpg 701>;
#phy-cells = <0>;
status = "disabled"; status = "disabled";
}; };
ohci3: usb@ee0e0000 { usb2_phy3: usb-phy@ee0e0200 {
compatible = "generic-ohci"; compatible = "renesas,usb2-phy-r8a7795",
reg = <0 0xee0e0000 0 0x100>; "renesas,rcar-gen3-usb2-phy";
reg = <0 0xee0e0200 0 0x700>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 700>; clocks = <&cpg CPG_MOD 700>;
phys = <&usb2_phy3>;
phy-names = "usb";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 700>; resets = <&cpg 700>;
#phy-cells = <0>;
status = "disabled"; status = "disabled";
}; };
hsusb: usb@e6590000 { sdhi0: sd@ee100000 {
compatible = "renesas,usbhs-r8a7795", compatible = "renesas,sdhi-r8a7795",
"renesas,rcar-gen3-usbhs"; "renesas,rcar-gen3-sdhi";
reg = <0 0xe6590000 0 0x100>; reg = <0 0xee100000 0 0x2000>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 704>; clocks = <&cpg CPG_MOD 314>;
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, max-frequency = <200000000>;
<&usb_dmac1 0>, <&usb_dmac1 1>;
dma-names = "ch0", "ch1", "ch2", "ch3";
renesas,buswait = <11>;
phys = <&usb2_phy0>;
phy-names = "usb";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 704>; resets = <&cpg 314>;
status = "disabled"; status = "disabled";
}; };
hsusb3: usb@e659c000 { sdhi1: sd@ee120000 {
compatible = "renesas,usbhs-r8a7795", compatible = "renesas,sdhi-r8a7795",
"renesas,rcar-gen3-usbhs"; "renesas,rcar-gen3-sdhi";
reg = <0 0xe659c000 0 0x100>; reg = <0 0xee120000 0 0x2000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 705>; clocks = <&cpg CPG_MOD 313>;
dmas = <&usb_dmac2 0>, <&usb_dmac2 1>, max-frequency = <200000000>;
<&usb_dmac3 0>, <&usb_dmac3 1>;
dma-names = "ch0", "ch1", "ch2", "ch3";
renesas,buswait = <11>;
phys = <&usb2_phy3>;
phy-names = "usb";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 705>; resets = <&cpg 313>;
status = "disabled"; status = "disabled";
}; };
sdhi2: sd@ee140000 {
compatible = "renesas,sdhi-r8a7795",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
max-frequency = <200000000>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 312>;
status = "disabled";
};
sdhi3: sd@ee160000 {
compatible = "renesas,sdhi-r8a7795",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
max-frequency = <200000000>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 311>;
status = "disabled";
};
sata: sata@ee300000 {
compatible = "renesas,sata-r8a7795",
"renesas,rcar-gen3-sata";
reg = <0 0xee300000 0 0x200000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 815>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 815>;
status = "disabled";
iommus = <&ipmmu_hc 2>;
};
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xf1010000 0 0x1000>,
<0x0 0xf1020000 0 0x20000>,
<0x0 0xf1040000 0 0x20000>,
<0x0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 408>;
};
pciec0: pcie@fe000000 { pciec0: pcie@fe000000 {
compatible = "renesas,pcie-r8a7795", compatible = "renesas,pcie-r8a7795",
"renesas,pcie-rcar-gen3"; "renesas,pcie-rcar-gen3";
...@@ -2133,28 +2401,28 @@ imr-lx4@fe890000 { ...@@ -2133,28 +2401,28 @@ imr-lx4@fe890000 {
reg = <0 0xfe890000 0 0x2000>; reg = <0 0xfe890000 0 0x2000>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 820>; clocks = <&cpg CPG_MOD 820>;
power-domains = <&sysc R8A7795_PD_A3VC>; power-domains = <&sysc R8A7795_PD_A3VC>;
resets = <&cpg 820>; resets = <&cpg 820>;
}; };
vspbc: vsp@fe920000 {
compatible = "renesas,vsp2";
reg = <0 0xfe920000 0 0x8000>;
interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 624>;
power-domains = <&sysc R8A7795_PD_A3VP>;
resets = <&cpg 624>;
renesas,fcp = <&fcpvb1>; fdp1@fe940000 {
compatible = "renesas,fdp1";
reg = <0 0xfe940000 0 0x2400>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 119>;
power-domains = <&sysc R8A7795_PD_A3VP>;
resets = <&cpg 119>;
renesas,fcp = <&fcpf0>;
}; };
fcpvb1: fcp@fe92f000 { fdp1@fe944000 {
compatible = "renesas,fcpv"; compatible = "renesas,fdp1";
reg = <0 0xfe92f000 0 0x200>; reg = <0 0xfe944000 0 0x2400>;
clocks = <&cpg CPG_MOD 606>; interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 118>;
power-domains = <&sysc R8A7795_PD_A3VP>; power-domains = <&sysc R8A7795_PD_A3VP>;
resets = <&cpg 606>; resets = <&cpg 118>;
iommus = <&ipmmu_vp1 7>; renesas,fcp = <&fcpf1>;
}; };
fcpf0: fcp@fe950000 { fcpf0: fcp@fe950000 {
...@@ -2175,17 +2443,6 @@ fcpf1: fcp@fe951000 { ...@@ -2175,17 +2443,6 @@ fcpf1: fcp@fe951000 {
iommus = <&ipmmu_vp1 1>; iommus = <&ipmmu_vp1 1>;
}; };
vspbd: vsp@fe960000 {
compatible = "renesas,vsp2";
reg = <0 0xfe960000 0 0x8000>;
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 626>;
power-domains = <&sysc R8A7795_PD_A3VP>;
resets = <&cpg 626>;
renesas,fcp = <&fcpvb0>;
};
fcpvb0: fcp@fe96f000 { fcpvb0: fcp@fe96f000 {
compatible = "renesas,fcpv"; compatible = "renesas,fcpv";
reg = <0 0xfe96f000 0 0x200>; reg = <0 0xfe96f000 0 0x200>;
...@@ -2195,15 +2452,13 @@ fcpvb0: fcp@fe96f000 { ...@@ -2195,15 +2452,13 @@ fcpvb0: fcp@fe96f000 {
iommus = <&ipmmu_vp0 5>; iommus = <&ipmmu_vp0 5>;
}; };
vspi0: vsp@fe9a0000 { fcpvb1: fcp@fe92f000 {
compatible = "renesas,vsp2"; compatible = "renesas,fcpv";
reg = <0 0xfe9a0000 0 0x8000>; reg = <0 0xfe92f000 0 0x200>;
interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 606>;
clocks = <&cpg CPG_MOD 631>;
power-domains = <&sysc R8A7795_PD_A3VP>; power-domains = <&sysc R8A7795_PD_A3VP>;
resets = <&cpg 631>; resets = <&cpg 606>;
iommus = <&ipmmu_vp1 7>;
renesas,fcp = <&fcpvi0>;
}; };
fcpvi0: fcp@fe9af000 { fcpvi0: fcp@fe9af000 {
...@@ -2215,17 +2470,6 @@ fcpvi0: fcp@fe9af000 { ...@@ -2215,17 +2470,6 @@ fcpvi0: fcp@fe9af000 {
iommus = <&ipmmu_vp0 8>; iommus = <&ipmmu_vp0 8>;
}; };
vspi1: vsp@fe9b0000 {
compatible = "renesas,vsp2";
reg = <0 0xfe9b0000 0 0x8000>;
interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 630>;
power-domains = <&sysc R8A7795_PD_A3VP>;
resets = <&cpg 630>;
renesas,fcp = <&fcpvi1>;
};
fcpvi1: fcp@fe9bf000 { fcpvi1: fcp@fe9bf000 {
compatible = "renesas,fcpv"; compatible = "renesas,fcpv";
reg = <0 0xfe9bf000 0 0x200>; reg = <0 0xfe9bf000 0 0x200>;
...@@ -2235,6 +2479,55 @@ fcpvi1: fcp@fe9bf000 { ...@@ -2235,6 +2479,55 @@ fcpvi1: fcp@fe9bf000 {
iommus = <&ipmmu_vp1 9>; iommus = <&ipmmu_vp1 9>;
}; };
fcpvd0: fcp@fea27000 {
compatible = "renesas,fcpv";
reg = <0 0xfea27000 0 0x200>;
clocks = <&cpg CPG_MOD 603>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 603>;
iommus = <&ipmmu_vi0 8>;
};
fcpvd1: fcp@fea2f000 {
compatible = "renesas,fcpv";
reg = <0 0xfea2f000 0 0x200>;
clocks = <&cpg CPG_MOD 602>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 602>;
iommus = <&ipmmu_vi0 9>;
};
fcpvd2: fcp@fea37000 {
compatible = "renesas,fcpv";
reg = <0 0xfea37000 0 0x200>;
clocks = <&cpg CPG_MOD 601>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 601>;
iommus = <&ipmmu_vi1 10>;
};
vspbd: vsp@fe960000 {
compatible = "renesas,vsp2";
reg = <0 0xfe960000 0 0x8000>;
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 626>;
power-domains = <&sysc R8A7795_PD_A3VP>;
resets = <&cpg 626>;
renesas,fcp = <&fcpvb0>;
};
vspbc: vsp@fe920000 {
compatible = "renesas,vsp2";
reg = <0 0xfe920000 0 0x8000>;
interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 624>;
power-domains = <&sysc R8A7795_PD_A3VP>;
resets = <&cpg 624>;
renesas,fcp = <&fcpvb1>;
};
vspd0: vsp@fea20000 { vspd0: vsp@fea20000 {
compatible = "renesas,vsp2"; compatible = "renesas,vsp2";
reg = <0 0xfea20000 0 0x8000>; reg = <0 0xfea20000 0 0x8000>;
...@@ -2246,15 +2539,6 @@ vspd0: vsp@fea20000 { ...@@ -2246,15 +2539,6 @@ vspd0: vsp@fea20000 {
renesas,fcp = <&fcpvd0>; renesas,fcp = <&fcpvd0>;
}; };
fcpvd0: fcp@fea27000 {
compatible = "renesas,fcpv";
reg = <0 0xfea27000 0 0x200>;
clocks = <&cpg CPG_MOD 603>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 603>;
iommus = <&ipmmu_vi0 8>;
};
vspd1: vsp@fea28000 { vspd1: vsp@fea28000 {
compatible = "renesas,vsp2"; compatible = "renesas,vsp2";
reg = <0 0xfea28000 0 0x8000>; reg = <0 0xfea28000 0 0x8000>;
...@@ -2266,15 +2550,6 @@ vspd1: vsp@fea28000 { ...@@ -2266,15 +2550,6 @@ vspd1: vsp@fea28000 {
renesas,fcp = <&fcpvd1>; renesas,fcp = <&fcpvd1>;
}; };
fcpvd1: fcp@fea2f000 {
compatible = "renesas,fcpv";
reg = <0 0xfea2f000 0 0x200>;
clocks = <&cpg CPG_MOD 602>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 602>;
iommus = <&ipmmu_vi0 9>;
};
vspd2: vsp@fea30000 { vspd2: vsp@fea30000 {
compatible = "renesas,vsp2"; compatible = "renesas,vsp2";
reg = <0 0xfea30000 0 0x8000>; reg = <0 0xfea30000 0 0x8000>;
...@@ -2286,33 +2561,159 @@ vspd2: vsp@fea30000 { ...@@ -2286,33 +2561,159 @@ vspd2: vsp@fea30000 {
renesas,fcp = <&fcpvd2>; renesas,fcp = <&fcpvd2>;
}; };
fcpvd2: fcp@fea37000 { vspi0: vsp@fe9a0000 {
compatible = "renesas,fcpv"; compatible = "renesas,vsp2";
reg = <0 0xfea37000 0 0x200>; reg = <0 0xfe9a0000 0 0x8000>;
clocks = <&cpg CPG_MOD 601>; interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; clocks = <&cpg CPG_MOD 631>;
resets = <&cpg 601>; power-domains = <&sysc R8A7795_PD_A3VP>;
iommus = <&ipmmu_vi1 10>; resets = <&cpg 631>;
renesas,fcp = <&fcpvi0>;
}; };
fdp1@fe940000 { vspi1: vsp@fe9b0000 {
compatible = "renesas,fdp1"; compatible = "renesas,vsp2";
reg = <0 0xfe940000 0 0x2400>; reg = <0 0xfe9b0000 0 0x8000>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 119>; clocks = <&cpg CPG_MOD 630>;
power-domains = <&sysc R8A7795_PD_A3VP>; power-domains = <&sysc R8A7795_PD_A3VP>;
resets = <&cpg 119>; resets = <&cpg 630>;
renesas,fcp = <&fcpf0>;
renesas,fcp = <&fcpvi1>;
}; };
fdp1@fe944000 { csi20: csi2@fea80000 {
compatible = "renesas,fdp1"; compatible = "renesas,r8a7795-csi2";
reg = <0 0xfe944000 0 0x2400>; reg = <0 0xfea80000 0 0x10000>;
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 118>; clocks = <&cpg CPG_MOD 714>;
power-domains = <&sysc R8A7795_PD_A3VP>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 118>; resets = <&cpg 714>;
renesas,fcp = <&fcpf1>; status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
csi20vin0: endpoint@0 {
reg = <0>;
remote-endpoint = <&vin0csi20>;
};
csi20vin1: endpoint@1 {
reg = <1>;
remote-endpoint = <&vin1csi20>;
};
csi20vin2: endpoint@2 {
reg = <2>;
remote-endpoint = <&vin2csi20>;
};
csi20vin3: endpoint@3 {
reg = <3>;
remote-endpoint = <&vin3csi20>;
};
csi20vin4: endpoint@4 {
reg = <4>;
remote-endpoint = <&vin4csi20>;
};
csi20vin5: endpoint@5 {
reg = <5>;
remote-endpoint = <&vin5csi20>;
};
csi20vin6: endpoint@6 {
reg = <6>;
remote-endpoint = <&vin6csi20>;
};
csi20vin7: endpoint@7 {
reg = <7>;
remote-endpoint = <&vin7csi20>;
};
};
};
};
csi40: csi2@feaa0000 {
compatible = "renesas,r8a7795-csi2";
reg = <0 0xfeaa0000 0 0x10000>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 716>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 716>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
csi40vin0: endpoint@0 {
reg = <0>;
remote-endpoint = <&vin0csi40>;
};
csi40vin1: endpoint@1 {
reg = <1>;
remote-endpoint = <&vin1csi40>;
};
csi40vin2: endpoint@2 {
reg = <2>;
remote-endpoint = <&vin2csi40>;
};
csi40vin3: endpoint@3 {
reg = <3>;
remote-endpoint = <&vin3csi40>;
};
};
};
};
csi41: csi2@feab0000 {
compatible = "renesas,r8a7795-csi2";
reg = <0 0xfeab0000 0 0x10000>;
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 715>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 715>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
csi41vin4: endpoint@0 {
reg = <0>;
remote-endpoint = <&vin4csi41>;
};
csi41vin5: endpoint@1 {
reg = <1>;
remote-endpoint = <&vin5csi41>;
};
csi41vin6: endpoint@2 {
reg = <2>;
remote-endpoint = <&vin6csi41>;
};
csi41vin7: endpoint@3 {
reg = <3>;
remote-endpoint = <&vin7csi41>;
};
};
};
}; };
hdmi0: hdmi@fead0000 { hdmi0: hdmi@fead0000 {
...@@ -2337,6 +2738,10 @@ dw_hdmi0_in: endpoint { ...@@ -2337,6 +2738,10 @@ dw_hdmi0_in: endpoint {
port@1 { port@1 {
reg = <1>; reg = <1>;
}; };
port@2 {
/* HDMI sound */
reg = <2>;
};
}; };
}; };
...@@ -2362,6 +2767,10 @@ dw_hdmi1_in: endpoint { ...@@ -2362,6 +2767,10 @@ dw_hdmi1_in: endpoint {
port@1 { port@1 {
reg = <1>; reg = <1>;
}; };
port@2 {
/* HDMI sound */
reg = <2>;
};
}; };
}; };
...@@ -2412,38 +2821,12 @@ du_out_lvds0: endpoint { ...@@ -2412,38 +2821,12 @@ du_out_lvds0: endpoint {
}; };
}; };
tsc: thermal@e6198000 { prr: chipid@fff00044 {
compatible = "renesas,r8a7795-thermal"; compatible = "renesas,prr";
reg = <0 0xe6198000 0 0x100>, reg = <0 0xfff00044 0 4>;
<0 0xe61a0000 0 0x100>,
<0 0xe61a8000 0 0x100>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 522>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 522>;
#thermal-sensor-cells = <1>;
status = "okay";
}; };
}; };
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(8) |
IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(8) |
IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(8) |
IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(8) |
IRQ_TYPE_LEVEL_LOW)>;
};
thermal-zones { thermal-zones {
sensor_thermal1: sensor-thermal1 { sensor_thermal1: sensor-thermal1 {
polling-delay-passive = <250>; polling-delay-passive = <250>;
...@@ -2453,12 +2836,12 @@ sensor_thermal1: sensor-thermal1 { ...@@ -2453,12 +2836,12 @@ sensor_thermal1: sensor-thermal1 {
trips { trips {
sensor1_passive: sensor1-passive { sensor1_passive: sensor1-passive {
temperature = <95000>; temperature = <95000>;
hysteresis = <2000>; hysteresis = <1000>;
type = "passive"; type = "passive";
}; };
sensor1_crit: sensor1-crit { sensor1_crit: sensor1-crit {
temperature = <120000>; temperature = <120000>;
hysteresis = <2000>; hysteresis = <1000>;
type = "critical"; type = "critical";
}; };
}; };
...@@ -2479,12 +2862,12 @@ sensor_thermal2: sensor-thermal2 { ...@@ -2479,12 +2862,12 @@ sensor_thermal2: sensor-thermal2 {
trips { trips {
sensor2_passive: sensor2-passive { sensor2_passive: sensor2-passive {
temperature = <95000>; temperature = <95000>;
hysteresis = <2000>; hysteresis = <1000>;
type = "passive"; type = "passive";
}; };
sensor2_crit: sensor2-crit { sensor2_crit: sensor2-crit {
temperature = <120000>; temperature = <120000>;
hysteresis = <2000>; hysteresis = <1000>;
type = "critical"; type = "critical";
}; };
}; };
...@@ -2505,12 +2888,12 @@ sensor_thermal3: sensor-thermal3 { ...@@ -2505,12 +2888,12 @@ sensor_thermal3: sensor-thermal3 {
trips { trips {
sensor3_passive: sensor3-passive { sensor3_passive: sensor3-passive {
temperature = <95000>; temperature = <95000>;
hysteresis = <2000>; hysteresis = <1000>;
type = "passive"; type = "passive";
}; };
sensor3_crit: sensor3-crit { sensor3_crit: sensor3-crit {
temperature = <120000>; temperature = <120000>;
hysteresis = <2000>; hysteresis = <1000>;
type = "critical"; type = "critical";
}; };
}; };
...@@ -2524,6 +2907,14 @@ map0 { ...@@ -2524,6 +2907,14 @@ map0 {
}; };
}; };
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
/* External USB clocks - can be overridden by the board */ /* External USB clocks - can be overridden by the board */
usb3s0_clk: usb3s0 { usb3s0_clk: usb3s0 {
compatible = "fixed-clock"; compatible = "fixed-clock";
......
arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
View file @ 171d429a
...@@ -40,6 +40,11 @@ &du { ...@@ -40,6 +40,11 @@ &du {
"dclkin.0", "dclkin.1", "dclkin.2"; "dclkin.0", "dclkin.1", "dclkin.2";
}; };
&sound_card {
dais = <&rsnd_port0 /* ak4613 */
&rsnd_port1>; /* HDMI0 */
};
&hdmi0 { &hdmi0 {
status = "okay"; status = "okay";
...@@ -50,9 +55,32 @@ rcar_dw_hdmi0_out: endpoint { ...@@ -50,9 +55,32 @@ rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>; remote-endpoint = <&hdmi0_con>;
}; };
}; };
port@2 {
reg = <2>;
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint1>;
};
};
}; };
}; };
&hdmi0_con { &hdmi0_con {
remote-endpoint = <&rcar_dw_hdmi0_out>; remote-endpoint = <&rcar_dw_hdmi0_out>;
}; };
&rcar_sound {
ports {
/* rsnd_port0 is on salvator-common */
rsnd_port1: port@1 {
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint1>;
frame-master = <&rsnd_endpoint1>;
playback = <&ssi2>;
};
};
};
};
arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts
View file @ 171d429a
...@@ -40,6 +40,11 @@ &du { ...@@ -40,6 +40,11 @@ &du {
"dclkin.0", "dclkin.1", "dclkin.2"; "dclkin.0", "dclkin.1", "dclkin.2";
}; };
&sound_card {
dais = <&rsnd_port0 /* ak4613 */
&rsnd_port1>; /* HDMI0 */
};
&hdmi0 { &hdmi0 {
status = "okay"; status = "okay";
...@@ -50,9 +55,32 @@ rcar_dw_hdmi0_out: endpoint { ...@@ -50,9 +55,32 @@ rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>; remote-endpoint = <&hdmi0_con>;
}; };
}; };
port@2 {
reg = <2>;
dw_hdmi0_snd_in: endpoint {
remote-endpoint = <&rsnd_endpoint1>;
};
};
}; };
}; };
&hdmi0_con { &hdmi0_con {
remote-endpoint = <&rcar_dw_hdmi0_out>; remote-endpoint = <&rcar_dw_hdmi0_out>;
}; };
&rcar_sound {
ports {
/* rsnd_port0 is on salvator-common */
rsnd_port1: port@1 {
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
dai-format = "i2s";
bitclock-master = <&rsnd_endpoint1>;
frame-master = <&rsnd_endpoint1>;
playback = <&ssi2>;
};
};
};
};
arch/arm64/boot/dts/renesas/r8a7796.dtsi
View file @ 171d429a
...@@ -60,6 +60,72 @@ can_clk: can { ...@@ -60,6 +60,72 @@ can_clk: can {
clock-frequency = <0>; clock-frequency = <0>;
}; };
cluster0_opp: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <900000>;
clock-latency-ns = <300000>;
turbo-mode;
};
opp-1700000000 {
opp-hz = /bits/ 64 <1700000000>;
opp-microvolt = <900000>;
clock-latency-ns = <300000>;
turbo-mode;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <960000>;
clock-latency-ns = <300000>;
turbo-mode;
};
};
cluster1_opp: opp_table1 {
compatible = "operating-points-v2";
opp-shared;
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1300000000 {
opp-hz = /bits/ 64 <1300000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
turbo-mode;
};
};
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
...@@ -77,7 +143,7 @@ a57_0: cpu@0 { ...@@ -77,7 +143,7 @@ a57_0: cpu@0 {
}; };
a57_1: cpu@1 { a57_1: cpu@1 {
compatible = "arm,cortex-a57","arm,armv8"; compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x1>; reg = <0x1>;
device_type = "cpu"; device_type = "cpu";
power-domains = <&sysc R8A7796_PD_CA57_CPU1>; power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
...@@ -100,7 +166,7 @@ a53_0: cpu@100 { ...@@ -100,7 +166,7 @@ a53_0: cpu@100 {
}; };
a53_1: cpu@101 { a53_1: cpu@101 {
compatible = "arm,cortex-a53","arm,armv8"; compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x101>; reg = <0x101>;
device_type = "cpu"; device_type = "cpu";
power-domains = <&sysc R8A7796_PD_CA53_CPU1>; power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
...@@ -111,7 +177,7 @@ a53_1: cpu@101 { ...@@ -111,7 +177,7 @@ a53_1: cpu@101 {
}; };
a53_2: cpu@102 { a53_2: cpu@102 {
compatible = "arm,cortex-a53","arm,armv8"; compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x102>; reg = <0x102>;
device_type = "cpu"; device_type = "cpu";
power-domains = <&sysc R8A7796_PD_CA53_CPU2>; power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
...@@ -122,7 +188,7 @@ a53_2: cpu@102 { ...@@ -122,7 +188,7 @@ a53_2: cpu@102 {
}; };
a53_3: cpu@103 { a53_3: cpu@103 {
compatible = "arm,cortex-a53","arm,armv8"; compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x103>; reg = <0x103>;
device_type = "cpu"; device_type = "cpu";
power-domains = <&sysc R8A7796_PD_CA53_CPU3>; power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
...@@ -161,72 +227,6 @@ extalr_clk: extalr { ...@@ -161,72 +227,6 @@ extalr_clk: extalr {
clock-frequency = <0>; clock-frequency = <0>;
}; };
cluster0_opp: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <900000>;
clock-latency-ns = <300000>;
turbo-mode;
};
opp-1700000000 {
opp-hz = /bits/ 64 <1700000000>;
opp-microvolt = <900000>;
clock-latency-ns = <300000>;
turbo-mode;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <960000>;
clock-latency-ns = <300000>;
turbo-mode;
};
};
cluster1_opp: opp_table1 {
compatible = "operating-points-v2";
opp-shared;
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
};
opp-1300000000 {
opp-hz = /bits/ 64 <1300000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
turbo-mode;
};
};
/* External PCIe clock - can be overridden by the board */ /* External PCIe clock - can be overridden by the board */
pcie_bus_clk: pcie_bus { pcie_bus_clk: pcie_bus {
compatible = "fixed-clock"; compatible = "fixed-clock";
...@@ -234,13 +234,6 @@ pcie_bus_clk: pcie_bus { ...@@ -234,13 +234,6 @@ pcie_bus_clk: pcie_bus {
clock-frequency = <0>; clock-frequency = <0>;
}; };
pmu_a57 {
compatible = "arm,cortex-a57-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a57_0>, <&a57_1>;
};
pmu_a53 { pmu_a53 {
compatible = "arm,cortex-a53-pmu"; compatible = "arm,cortex-a53-pmu";
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
...@@ -250,6 +243,13 @@ pmu_a53 { ...@@ -250,6 +243,13 @@ pmu_a53 {
interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
}; };
pmu_a57 {
compatible = "arm,cortex-a57-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a57_0>, <&a57_1>;
};
psci { psci {
compatible = "arm,psci-1.0", "arm,psci-0.2"; compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc"; method = "smc";
...@@ -269,23 +269,6 @@ soc { ...@@ -269,23 +269,6 @@ soc {
#size-cells = <2>; #size-cells = <2>;
ranges; ranges;
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xf1010000 0 0x1000>,
<0x0 0xf1020000 0 0x20000>,
<0x0 0xf1040000 0 0x20000>,
<0x0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 408>;
};
wdt0: watchdog@e6020000 { wdt0: watchdog@e6020000 {
compatible = "renesas,r8a7796-wdt", compatible = "renesas,r8a7796-wdt",
"renesas,rcar-gen3-wdt"; "renesas,rcar-gen3-wdt";
...@@ -421,242 +404,72 @@ pfc: pin-controller@e6060000 { ...@@ -421,242 +404,72 @@ pfc: pin-controller@e6060000 {
reg = <0 0xe6060000 0 0x50c>; reg = <0 0xe6060000 0 0x50c>;
}; };
ipmmu_vi0: mmu@febd0000 { cpg: clock-controller@e6150000 {
compatible = "renesas,ipmmu-r8a7796"; compatible = "renesas,r8a7796-cpg-mssr";
reg = <0 0xfebd0000 0 0x1000>; reg = <0 0xe6150000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 9>; clocks = <&extal_clk>, <&extalr_clk>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; clock-names = "extal", "extalr";
#iommu-cells = <1>; #clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
}; };
ipmmu_vc0: mmu@fe6b0000 { rst: reset-controller@e6160000 {
compatible = "renesas,ipmmu-r8a7796"; compatible = "renesas,r8a7796-rst";
reg = <0 0xfe6b0000 0 0x1000>; reg = <0 0xe6160000 0 0x0200>;
renesas,ipmmu-main = <&ipmmu_mm 8>;
power-domains = <&sysc R8A7796_PD_A3VC>;
#iommu-cells = <1>;
status = "disabled";
}; };
ipmmu_pv0: mmu@fd800000 { sysc: system-controller@e6180000 {
compatible = "renesas,ipmmu-r8a7796"; compatible = "renesas,r8a7796-sysc";
reg = <0 0xfd800000 0 0x1000>; reg = <0 0xe6180000 0 0x0400>;
renesas,ipmmu-main = <&ipmmu_mm 5>; #power-domain-cells = <1>;
};
tsc: thermal@e6198000 {
compatible = "renesas,r8a7796-thermal";
reg = <0 0xe6198000 0 0x100>,
<0 0xe61a0000 0 0x100>,
<0 0xe61a8000 0 0x100>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 522>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#iommu-cells = <1>; resets = <&cpg 522>;
#thermal-sensor-cells = <1>;
status = "okay";
}; };
ipmmu_pv1: mmu@fd950000 { intc_ex: interrupt-controller@e61c0000 {
compatible = "renesas,ipmmu-r8a7796"; compatible = "renesas,intc-ex-r8a7796", "renesas,irqc";
reg = <0 0xfd950000 0 0x1000>; #interrupt-cells = <2>;
renesas,ipmmu-main = <&ipmmu_mm 6>; interrupt-controller;
reg = <0 0xe61c0000 0 0x200>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 407>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#iommu-cells = <1>; resets = <&cpg 407>;
status = "disabled";
}; };
ipmmu_ir: mmu@ff8b0000 { i2c0: i2c@e6500000 {
compatible = "renesas,ipmmu-r8a7796"; #address-cells = <1>;
reg = <0 0xff8b0000 0 0x1000>; #size-cells = <0>;
renesas,ipmmu-main = <&ipmmu_mm 3>; compatible = "renesas,i2c-r8a7796",
power-domains = <&sysc R8A7796_PD_A3IR>; "renesas,rcar-gen3-i2c";
#iommu-cells = <1>; reg = <0 0xe6500000 0 0x40>;
status = "disabled"; interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
}; clocks = <&cpg CPG_MOD 931>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
ipmmu_hc: mmu@e6570000 { resets = <&cpg 931>;
compatible = "renesas,ipmmu-r8a7796"; dmas = <&dmac1 0x91>, <&dmac1 0x90>,
reg = <0 0xe6570000 0 0x1000>; <&dmac2 0x91>, <&dmac2 0x90>;
renesas,ipmmu-main = <&ipmmu_mm 2>; dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; i2c-scl-internal-delay-ns = <110>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_rt: mmu@ffc80000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xffc80000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 7>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_mp: mmu@ec670000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xec670000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 4>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_ds0: mmu@e6740000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xe6740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 0>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_ds1: mmu@e7740000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xe7740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 1>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_mm: mmu@e67b0000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xe67b0000 0 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a7796-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
clocks = <&extal_clk>, <&extalr_clk>;
clock-names = "extal", "extalr";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};
rst: reset-controller@e6160000 {
compatible = "renesas,r8a7796-rst";
reg = <0 0xe6160000 0 0x0200>;
};
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7796-sysc";
reg = <0 0xe6180000 0 0x0400>;
#power-domain-cells = <1>;
};
intc_ex: interrupt-controller@e61c0000 {
compatible = "renesas,intc-ex-r8a7796", "renesas,irqc";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0 0xe61c0000 0 0x200>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 407>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 407>;
};
i2c_dvfs: i2c@e60b0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,iic-r8a7796",
"renesas,rcar-gen3-iic",
"renesas,rmobile-iic";
reg = <0 0xe60b0000 0 0x425>;
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 926>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 926>;
dmas = <&dmac0 0x11>, <&dmac0 0x10>;
dma-names = "tx", "rx";
status = "disabled";
};
pwm0: pwm@e6e30000 {
compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
reg = <0 0xe6e30000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
pwm1: pwm@e6e31000 {
compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
reg = <0 0xe6e31000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
pwm2: pwm@e6e32000 {
compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
reg = <0 0xe6e32000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
pwm3: pwm@e6e33000 {
compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
reg = <0 0xe6e33000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
pwm4: pwm@e6e34000 {
compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
reg = <0 0xe6e34000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
pwm5: pwm@e6e35000 {
compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
reg = <0 0xe6e35000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
pwm6: pwm@e6e36000 {
compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
reg = <0 0xe6e36000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
i2c0: i2c@e6500000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a7796",
"renesas,rcar-gen3-i2c";
reg = <0 0xe6500000 0 0x40>;
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 931>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 931>;
dmas = <&dmac1 0x91>, <&dmac1 0x90>,
<&dmac2 0x91>, <&dmac2 0x90>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
status = "disabled"; status = "disabled";
}; };
...@@ -758,244 +571,37 @@ i2c6: i2c@e66e8000 { ...@@ -758,244 +571,37 @@ i2c6: i2c@e66e8000 {
status = "disabled"; status = "disabled";
}; };
can0: can@e6c30000 { i2c_dvfs: i2c@e60b0000 {
compatible = "renesas,can-r8a7796", #address-cells = <1>;
"renesas,rcar-gen3-can"; #size-cells = <0>;
reg = <0 0xe6c30000 0 0x1000>; compatible = "renesas,iic-r8a7796",
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; "renesas,rcar-gen3-iic",
clocks = <&cpg CPG_MOD 916>, "renesas,rmobile-iic";
<&cpg CPG_CORE R8A7796_CLK_CANFD>, reg = <0 0xe60b0000 0 0x425>;
<&can_clk>; interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "clkp1", "clkp2", "can_clk"; clocks = <&cpg CPG_MOD 926>;
assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 916>; resets = <&cpg 926>;
dmas = <&dmac0 0x11>, <&dmac0 0x10>;
dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
}; };
can1: can@e6c38000 { hscif0: serial@e6540000 {
compatible = "renesas,can-r8a7796", compatible = "renesas,hscif-r8a7796",
"renesas,rcar-gen3-can"; "renesas,rcar-gen3-hscif",
reg = <0 0xe6c38000 0 0x1000>; "renesas,hscif";
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; reg = <0 0xe6540000 0 0x60>;
clocks = <&cpg CPG_MOD 915>, interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
<&cpg CPG_CORE R8A7796_CLK_CANFD>, clocks = <&cpg CPG_MOD 520>,
<&can_clk>; <&cpg CPG_CORE R8A7796_CLK_S3D1>,
clock-names = "clkp1", "clkp2", "can_clk"; <&scif_clk>;
assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; clock-names = "fck", "brg_int", "scif_clk";
assigned-clock-rates = <40000000>; dmas = <&dmac1 0x31>, <&dmac1 0x30>,
<&dmac2 0x31>, <&dmac2 0x30>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 915>; resets = <&cpg 520>;
status = "disabled";
};
canfd: can@e66c0000 {
compatible = "renesas,r8a7796-canfd",
"renesas,rcar-gen3-canfd";
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A7796_CLK_CANFD>,
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";
channel0 {
status = "disabled";
};
channel1 {
status = "disabled";
};
};
drif00: rif@e6f40000 {
compatible = "renesas,r8a7796-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f40000 0 0x64>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 515>;
clock-names = "fck";
dmas = <&dmac1 0x20>, <&dmac2 0x20>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 515>;
renesas,bonding = <&drif01>;
status = "disabled";
};
drif01: rif@e6f50000 {
compatible = "renesas,r8a7796-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f50000 0 0x64>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 514>;
clock-names = "fck";
dmas = <&dmac1 0x22>, <&dmac2 0x22>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 514>;
renesas,bonding = <&drif00>;
status = "disabled";
};
drif10: rif@e6f60000 {
compatible = "renesas,r8a7796-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f60000 0 0x64>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 513>;
clock-names = "fck";
dmas = <&dmac1 0x24>, <&dmac2 0x24>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 513>;
renesas,bonding = <&drif11>;
status = "disabled";
};
drif11: rif@e6f70000 {
compatible = "renesas,r8a7796-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f70000 0 0x64>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 512>;
clock-names = "fck";
dmas = <&dmac1 0x26>, <&dmac2 0x26>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 512>;
renesas,bonding = <&drif10>;
status = "disabled";
};
drif20: rif@e6f80000 {
compatible = "renesas,r8a7796-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f80000 0 0x64>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 511>;
clock-names = "fck";
dmas = <&dmac1 0x28>, <&dmac2 0x28>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 511>;
renesas,bonding = <&drif21>;
status = "disabled";
};
drif21: rif@e6f90000 {
compatible = "renesas,r8a7796-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6f90000 0 0x64>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 510>;
clock-names = "fck";
dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 510>;
renesas,bonding = <&drif20>;
status = "disabled";
};
drif30: rif@e6fa0000 {
compatible = "renesas,r8a7796-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6fa0000 0 0x64>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 509>;
clock-names = "fck";
dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 509>;
renesas,bonding = <&drif31>;
status = "disabled";
};
drif31: rif@e6fb0000 {
compatible = "renesas,r8a7796-drif",
"renesas,rcar-gen3-drif";
reg = <0 0xe6fb0000 0 0x64>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 508>;
clock-names = "fck";
dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 508>;
renesas,bonding = <&drif30>;
status = "disabled";
};
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a7796",
"renesas,etheravb-rcar-gen3";
reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15",
"ch16", "ch17", "ch18", "ch19",
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
hscif0: serial@e6540000 {
compatible = "renesas,hscif-r8a7796",
"renesas,rcar-gen3-hscif",
"renesas,hscif";
reg = <0 0xe6540000 0 0x60>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 520>,
<&cpg CPG_CORE R8A7796_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x31>, <&dmac1 0x30>,
<&dmac2 0x31>, <&dmac2 0x30>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 520>;
status = "disabled"; status = "disabled";
}; };
...@@ -1069,162 +675,61 @@ hscif4: serial@e66b0000 { ...@@ -1069,162 +675,61 @@ hscif4: serial@e66b0000 {
status = "disabled"; status = "disabled";
}; };
scif0: serial@e6e60000 { hsusb: usb@e6590000 {
compatible = "renesas,scif-r8a7796", compatible = "renesas,usbhs-r8a7796",
"renesas,rcar-gen3-scif", "renesas,scif"; "renesas,rcar-gen3-usbhs";
reg = <0 0xe6e60000 0 64>; reg = <0 0xe6590000 0 0x100>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 207>, clocks = <&cpg CPG_MOD 704>;
<&cpg CPG_CORE R8A7796_CLK_S3D1>, dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
<&scif_clk>; <&usb_dmac1 0>, <&usb_dmac1 1>;
clock-names = "fck", "brg_int", "scif_clk"; dma-names = "ch0", "ch1", "ch2", "ch3";
dmas = <&dmac1 0x51>, <&dmac1 0x50>, renesas,buswait = <11>;
<&dmac2 0x51>, <&dmac2 0x50>; phys = <&usb2_phy0>;
dma-names = "tx", "rx", "tx", "rx"; phy-names = "usb";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 207>; resets = <&cpg 704>;
status = "disabled"; status = "disabled";
}; };
scif1: serial@e6e68000 { usb_dmac0: dma-controller@e65a0000 {
compatible = "renesas,scif-r8a7796", compatible = "renesas,r8a7796-usb-dmac",
"renesas,rcar-gen3-scif", "renesas,scif"; "renesas,usb-dmac";
reg = <0 0xe6e68000 0 64>; reg = <0 0xe65a0000 0 0x100>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
clocks = <&cpg CPG_MOD 206>, GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
<&cpg CPG_CORE R8A7796_CLK_S3D1>, interrupt-names = "ch0", "ch1";
<&scif_clk>; clocks = <&cpg CPG_MOD 330>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x53>, <&dmac1 0x52>,
<&dmac2 0x53>, <&dmac2 0x52>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 206>; resets = <&cpg 330>;
status = "disabled"; #dma-cells = <1>;
dma-channels = <2>;
}; };
scif2: serial@e6e88000 { usb_dmac1: dma-controller@e65b0000 {
compatible = "renesas,scif-r8a7796", compatible = "renesas,r8a7796-usb-dmac",
"renesas,rcar-gen3-scif", "renesas,scif"; "renesas,usb-dmac";
reg = <0 0xe6e88000 0 64>; reg = <0 0xe65b0000 0 0x100>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
clocks = <&cpg CPG_MOD 310>, GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
<&cpg CPG_CORE R8A7796_CLK_S3D1>, interrupt-names = "ch0", "ch1";
<&scif_clk>; clocks = <&cpg CPG_MOD 331>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 310>;
status = "disabled";
};
scif3: serial@e6c50000 {
compatible = "renesas,scif-r8a7796",
"renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6c50000 0 64>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 204>,
<&cpg CPG_CORE R8A7796_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x57>, <&dmac0 0x56>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 204>;
status = "disabled";
};
scif4: serial@e6c40000 {
compatible = "renesas,scif-r8a7796",
"renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6c40000 0 64>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 203>,
<&cpg CPG_CORE R8A7796_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x59>, <&dmac0 0x58>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 203>;
status = "disabled";
};
scif5: serial@e6f30000 {
compatible = "renesas,scif-r8a7796",
"renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6f30000 0 64>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 202>,
<&cpg CPG_CORE R8A7796_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
<&dmac2 0x5b>, <&dmac2 0x5a>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 202>;
status = "disabled";
};
msiof0: spi@e6e90000 {
compatible = "renesas,msiof-r8a7796",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6e90000 0 0x0064>;
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 211>;
dmas = <&dmac1 0x41>, <&dmac1 0x40>,
<&dmac2 0x41>, <&dmac2 0x40>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 211>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof1: spi@e6ea0000 {
compatible = "renesas,msiof-r8a7796",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6ea0000 0 0x0064>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 210>;
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
<&dmac2 0x43>, <&dmac2 0x42>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 210>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof2: spi@e6c00000 {
compatible = "renesas,msiof-r8a7796",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6c00000 0 0x0064>;
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 209>;
dmas = <&dmac0 0x45>, <&dmac0 0x44>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 209>; resets = <&cpg 331>;
#address-cells = <1>; #dma-cells = <1>;
#size-cells = <0>; dma-channels = <2>;
status = "disabled";
}; };
msiof3: spi@e6c10000 { usb3_phy0: usb-phy@e65ee000 {
compatible = "renesas,msiof-r8a7796", compatible = "renesas,r8a7796-usb3-phy",
"renesas,rcar-gen3-msiof"; "renesas,rcar-gen3-usb3-phy";
reg = <0 0xe6c10000 0 0x0064>; reg = <0 0xe65ee000 0 0x90>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
clocks = <&cpg CPG_MOD 208>; <&usb_extal_clk>;
dmas = <&dmac0 0x47>, <&dmac0 0x46>; clock-names = "usb3-if", "usb3s_clk", "usb_extal";
dma-names = "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 208>; resets = <&cpg 328>;
#address-cells = <1>; #phy-cells = <0>;
#size-cells = <0>;
status = "disabled"; status = "disabled";
}; };
...@@ -1354,306 +859,803 @@ GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH ...@@ -1354,306 +859,803 @@ GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
<&ipmmu_ds1 30>, <&ipmmu_ds1 31>; <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
}; };
audma0: dma-controller@ec700000 { ipmmu_ds0: mmu@e6740000 {
compatible = "renesas,dmac-r8a7796", compatible = "renesas,ipmmu-r8a7796";
"renesas,rcar-dmac"; reg = <0 0xe6740000 0 0x1000>;
reg = <0 0xec700000 0 0x10000>; renesas,ipmmu-main = <&ipmmu_mm 0>;
interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 502>;
clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 502>; #iommu-cells = <1>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
<&ipmmu_mp 2>, <&ipmmu_mp 3>,
<&ipmmu_mp 4>, <&ipmmu_mp 5>,
<&ipmmu_mp 6>, <&ipmmu_mp 7>,
<&ipmmu_mp 8>, <&ipmmu_mp 9>,
<&ipmmu_mp 10>, <&ipmmu_mp 11>,
<&ipmmu_mp 12>, <&ipmmu_mp 13>,
<&ipmmu_mp 14>, <&ipmmu_mp 15>;
}; };
audma1: dma-controller@ec720000 { ipmmu_ds1: mmu@e7740000 {
compatible = "renesas,dmac-r8a7796", compatible = "renesas,ipmmu-r8a7796";
"renesas,rcar-dmac"; reg = <0 0xe7740000 0 0x1000>;
reg = <0 0xec720000 0 0x10000>; renesas,ipmmu-main = <&ipmmu_mm 1>;
interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 501>;
clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 501>; #iommu-cells = <1>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
<&ipmmu_mp 18>, <&ipmmu_mp 19>,
<&ipmmu_mp 20>, <&ipmmu_mp 21>,
<&ipmmu_mp 22>, <&ipmmu_mp 23>,
<&ipmmu_mp 24>, <&ipmmu_mp 25>,
<&ipmmu_mp 26>, <&ipmmu_mp 27>,
<&ipmmu_mp 28>, <&ipmmu_mp 29>,
<&ipmmu_mp 30>, <&ipmmu_mp 31>;
}; };
usb_dmac0: dma-controller@e65a0000 { ipmmu_hc: mmu@e6570000 {
compatible = "renesas,r8a7796-usb-dmac", compatible = "renesas,ipmmu-r8a7796";
"renesas,usb-dmac"; reg = <0 0xe6570000 0 0x1000>;
reg = <0 0xe65a0000 0 0x100>; renesas,ipmmu-main = <&ipmmu_mm 2>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 330>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 330>; #iommu-cells = <1>;
#dma-cells = <1>;
dma-channels = <2>;
}; };
usb_dmac1: dma-controller@e65b0000 { ipmmu_ir: mmu@ff8b0000 {
compatible = "renesas,r8a7796-usb-dmac", compatible = "renesas,ipmmu-r8a7796";
"renesas,usb-dmac"; reg = <0 0xff8b0000 0 0x1000>;
reg = <0 0xe65b0000 0 0x100>; renesas,ipmmu-main = <&ipmmu_mm 3>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH power-domains = <&sysc R8A7796_PD_A3IR>;
GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; #iommu-cells = <1>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 331>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 331>;
#dma-cells = <1>;
dma-channels = <2>;
}; };
hsusb: usb@e6590000 { ipmmu_mm: mmu@e67b0000 {
compatible = "renesas,usbhs-r8a7796", compatible = "renesas,ipmmu-r8a7796";
"renesas,rcar-gen3-usbhs"; reg = <0 0xe67b0000 0 0x1000>;
reg = <0 0xe6590000 0 0x100>; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 704>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, #iommu-cells = <1>;
<&usb_dmac1 0>, <&usb_dmac1 1>; };
dma-names = "ch0", "ch1", "ch2", "ch3";
renesas,buswait = <11>; ipmmu_mp: mmu@ec670000 {
phys = <&usb2_phy0>; compatible = "renesas,ipmmu-r8a7796";
phy-names = "usb"; reg = <0 0xec670000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 4>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_pv0: mmu@fd800000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xfd800000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 5>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_pv1: mmu@fd950000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xfd950000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 6>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_rt: mmu@ffc80000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xffc80000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 7>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_vc0: mmu@fe6b0000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xfe6b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 8>;
power-domains = <&sysc R8A7796_PD_A3VC>;
#iommu-cells = <1>;
};
ipmmu_vi0: mmu@febd0000 {
compatible = "renesas,ipmmu-r8a7796";
reg = <0 0xfebd0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 9>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a7796",
"renesas,etheravb-rcar-gen3";
reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15",
"ch16", "ch17", "ch18", "ch19",
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
iommus = <&ipmmu_ds0 16>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
can0: can@e6c30000 {
compatible = "renesas,can-r8a7796",
"renesas,rcar-gen3-can";
reg = <0 0xe6c30000 0 0x1000>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 916>,
<&cpg CPG_CORE R8A7796_CLK_CANFD>,
<&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 916>;
status = "disabled";
};
can1: can@e6c38000 {
compatible = "renesas,can-r8a7796",
"renesas,rcar-gen3-can";
reg = <0 0xe6c38000 0 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 915>,
<&cpg CPG_CORE R8A7796_CLK_CANFD>,
<&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 915>;
status = "disabled";
};
canfd: can@e66c0000 {
compatible = "renesas,r8a7796-canfd",
"renesas,rcar-gen3-canfd";
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A7796_CLK_CANFD>,
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";
channel0 {
status = "disabled";
};
channel1 {
status = "disabled";
};
};
pwm0: pwm@e6e30000 {
compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
reg = <0 0xe6e30000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
pwm1: pwm@e6e31000 {
compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
reg = <0 0xe6e31000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
pwm2: pwm@e6e32000 {
compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
reg = <0 0xe6e32000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
pwm3: pwm@e6e33000 {
compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
reg = <0 0xe6e33000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
pwm4: pwm@e6e34000 {
compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
reg = <0 0xe6e34000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
pwm5: pwm@e6e35000 {
compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
reg = <0 0xe6e35000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
pwm6: pwm@e6e36000 {
compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
reg = <0 0xe6e36000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "disabled";
};
scif0: serial@e6e60000 {
compatible = "renesas,scif-r8a7796",
"renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6e60000 0 64>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 207>,
<&cpg CPG_CORE R8A7796_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x51>, <&dmac1 0x50>,
<&dmac2 0x51>, <&dmac2 0x50>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 207>;
status = "disabled";
};
scif1: serial@e6e68000 {
compatible = "renesas,scif-r8a7796",
"renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6e68000 0 64>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 206>,
<&cpg CPG_CORE R8A7796_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x53>, <&dmac1 0x52>,
<&dmac2 0x53>, <&dmac2 0x52>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 206>;
status = "disabled";
};
scif2: serial@e6e88000 {
compatible = "renesas,scif-r8a7796",
"renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6e88000 0 64>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 310>,
<&cpg CPG_CORE R8A7796_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 310>;
status = "disabled";
};
scif3: serial@e6c50000 {
compatible = "renesas,scif-r8a7796",
"renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6c50000 0 64>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 204>,
<&cpg CPG_CORE R8A7796_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x57>, <&dmac0 0x56>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 204>;
status = "disabled";
};
scif4: serial@e6c40000 {
compatible = "renesas,scif-r8a7796",
"renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6c40000 0 64>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 203>,
<&cpg CPG_CORE R8A7796_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x59>, <&dmac0 0x58>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 203>;
status = "disabled";
};
scif5: serial@e6f30000 {
compatible = "renesas,scif-r8a7796",
"renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6f30000 0 64>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 202>,
<&cpg CPG_CORE R8A7796_CLK_S3D1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
<&dmac2 0x5b>, <&dmac2 0x5a>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 202>;
status = "disabled";
};
msiof0: spi@e6e90000 {
compatible = "renesas,msiof-r8a7796",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6e90000 0 0x0064>;
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 211>;
dmas = <&dmac1 0x41>, <&dmac1 0x40>,
<&dmac2 0x41>, <&dmac2 0x40>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 211>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof1: spi@e6ea0000 {
compatible = "renesas,msiof-r8a7796",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6ea0000 0 0x0064>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 210>;
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
<&dmac2 0x43>, <&dmac2 0x42>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 210>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof2: spi@e6c00000 {
compatible = "renesas,msiof-r8a7796",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6c00000 0 0x0064>;
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 209>;
dmas = <&dmac0 0x45>, <&dmac0 0x44>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 209>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof3: spi@e6c10000 {
compatible = "renesas,msiof-r8a7796",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6c10000 0 0x0064>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 208>;
dmas = <&dmac0 0x47>, <&dmac0 0x46>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 208>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
vin0: video@e6ef0000 {
compatible = "renesas,vin-r8a7796";
reg = <0 0xe6ef0000 0 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 811>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 811>;
renesas,id = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin0csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin0>;
};
vin0csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin0>;
};
};
};
};
vin1: video@e6ef1000 {
compatible = "renesas,vin-r8a7796";
reg = <0 0xe6ef1000 0 0x1000>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 810>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 704>; resets = <&cpg 810>;
renesas,id = <1>;
status = "disabled"; status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin1csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin1>;
};
vin1csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin1>;
};
};
};
}; };
usb3_phy0: usb-phy@e65ee000 { vin2: video@e6ef2000 {
compatible = "renesas,r8a7796-usb3-phy", compatible = "renesas,vin-r8a7796";
"renesas,rcar-gen3-usb3-phy"; reg = <0 0xe6ef2000 0 0x1000>;
reg = <0 0xe65ee000 0 0x90>; interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, clocks = <&cpg CPG_MOD 809>;
<&usb_extal_clk>;
clock-names = "usb3-if", "usb3s_clk", "usb_extal";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 328>; resets = <&cpg 809>;
#phy-cells = <0>; renesas,id = <2>;
status = "disabled"; status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin2csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin2>;
};
vin2csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin2>;
};
};
};
}; };
xhci0: usb@ee000000 { vin3: video@e6ef3000 {
compatible = "renesas,xhci-r8a7796", compatible = "renesas,vin-r8a7796";
"renesas,rcar-gen3-xhci"; reg = <0 0xe6ef3000 0 0x1000>;
reg = <0 0xee000000 0 0xc00>; interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 808>;
clocks = <&cpg CPG_MOD 328>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 328>; resets = <&cpg 808>;
renesas,id = <3>;
status = "disabled"; status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin3csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin3>;
};
vin3csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin3>;
};
};
};
}; };
usb3_peri0: usb@ee020000 { vin4: video@e6ef4000 {
compatible = "renesas,r8a7796-usb3-peri", compatible = "renesas,vin-r8a7796";
"renesas,rcar-gen3-usb3-peri"; reg = <0 0xe6ef4000 0 0x1000>;
reg = <0 0xee020000 0 0x400>; interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 807>;
clocks = <&cpg CPG_MOD 328>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 328>; resets = <&cpg 807>;
renesas,id = <4>;
status = "disabled"; status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin4csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin4>;
};
vin4csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin4>;
};
};
};
}; };
ohci0: usb@ee080000 { vin5: video@e6ef5000 {
compatible = "generic-ohci"; compatible = "renesas,vin-r8a7796";
reg = <0 0xee080000 0 0x100>; reg = <0 0xe6ef5000 0 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>; clocks = <&cpg CPG_MOD 806>;
phys = <&usb2_phy0>;
phy-names = "usb";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 703>; resets = <&cpg 806>;
renesas,id = <5>;
status = "disabled"; status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin5csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin5>;
};
vin5csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin5>;
};
};
};
}; };
ehci0: usb@ee080100 { vin6: video@e6ef6000 {
compatible = "generic-ehci"; compatible = "renesas,vin-r8a7796";
reg = <0 0xee080100 0 0x100>; reg = <0 0xe6ef6000 0 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>; clocks = <&cpg CPG_MOD 805>;
phys = <&usb2_phy0>;
phy-names = "usb";
companion= <&ohci0>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 703>; resets = <&cpg 805>;
renesas,id = <6>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin6csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin6>;
};
vin6csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin6>;
};
};
};
};
vin7: video@e6ef7000 {
compatible = "renesas,vin-r8a7796";
reg = <0 0xe6ef7000 0 0x1000>;
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 804>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 804>;
renesas,id = <7>;
status = "disabled"; status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin7csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin7>;
};
vin7csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin7>;
};
};
};
}; };
usb2_phy0: usb-phy@ee080200 { drif00: rif@e6f40000 {
compatible = "renesas,usb2-phy-r8a7796", compatible = "renesas,r8a7796-drif",
"renesas,rcar-gen3-usb2-phy"; "renesas,rcar-gen3-drif";
reg = <0 0xee080200 0 0x700>; reg = <0 0xe6f40000 0 0x64>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>; clocks = <&cpg CPG_MOD 515>;
clock-names = "fck";
dmas = <&dmac1 0x20>, <&dmac2 0x20>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 703>; resets = <&cpg 515>;
#phy-cells = <0>; renesas,bonding = <&drif01>;
status = "disabled"; status = "disabled";
}; };
ohci1: usb@ee0a0000 { drif01: rif@e6f50000 {
compatible = "generic-ohci"; compatible = "renesas,r8a7796-drif",
reg = <0 0xee0a0000 0 0x100>; "renesas,rcar-gen3-drif";
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; reg = <0 0xe6f50000 0 0x64>;
clocks = <&cpg CPG_MOD 702>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb2_phy1>; clocks = <&cpg CPG_MOD 514>;
phy-names = "usb"; clock-names = "fck";
dmas = <&dmac1 0x22>, <&dmac2 0x22>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 702>; resets = <&cpg 514>;
renesas,bonding = <&drif00>;
status = "disabled"; status = "disabled";
}; };
ehci1: usb@ee0a0100 { drif10: rif@e6f60000 {
compatible = "generic-ehci"; compatible = "renesas,r8a7796-drif",
reg = <0 0xee0a0100 0 0x100>; "renesas,rcar-gen3-drif";
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; reg = <0 0xe6f60000 0 0x64>;
clocks = <&cpg CPG_MOD 702>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb2_phy1>; clocks = <&cpg CPG_MOD 513>;
phy-names = "usb"; clock-names = "fck";
companion= <&ohci1>; dmas = <&dmac1 0x24>, <&dmac2 0x24>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 702>; resets = <&cpg 513>;
renesas,bonding = <&drif11>;
status = "disabled"; status = "disabled";
}; };
usb2_phy1: usb-phy@ee0a0200 { drif11: rif@e6f70000 {
compatible = "renesas,usb2-phy-r8a7796", compatible = "renesas,r8a7796-drif",
"renesas,rcar-gen3-usb2-phy"; "renesas,rcar-gen3-drif";
reg = <0 0xee0a0200 0 0x700>; reg = <0 0xe6f70000 0 0x64>;
clocks = <&cpg CPG_MOD 702>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 512>;
clock-names = "fck";
dmas = <&dmac1 0x26>, <&dmac2 0x26>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 702>; resets = <&cpg 512>;
#phy-cells = <0>; renesas,bonding = <&drif10>;
status = "disabled"; status = "disabled";
}; };
sdhi0: sd@ee100000 { drif20: rif@e6f80000 {
compatible = "renesas,sdhi-r8a7796", compatible = "renesas,r8a7796-drif",
"renesas,rcar-gen3-sdhi"; "renesas,rcar-gen3-drif";
reg = <0 0xee100000 0 0x2000>; reg = <0 0xe6f80000 0 0x64>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>; clocks = <&cpg CPG_MOD 511>;
max-frequency = <200000000>; clock-names = "fck";
dmas = <&dmac1 0x28>, <&dmac2 0x28>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 314>; resets = <&cpg 511>;
renesas,bonding = <&drif21>;
status = "disabled"; status = "disabled";
}; };
sdhi1: sd@ee120000 { drif21: rif@e6f90000 {
compatible = "renesas,sdhi-r8a7796", compatible = "renesas,r8a7796-drif",
"renesas,rcar-gen3-sdhi"; "renesas,rcar-gen3-drif";
reg = <0 0xee120000 0 0x2000>; reg = <0 0xe6f90000 0 0x64>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 313>; clocks = <&cpg CPG_MOD 510>;
max-frequency = <200000000>; clock-names = "fck";
dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 313>; resets = <&cpg 510>;
renesas,bonding = <&drif20>;
status = "disabled"; status = "disabled";
}; };
sdhi2: sd@ee140000 { drif30: rif@e6fa0000 {
compatible = "renesas,sdhi-r8a7796", compatible = "renesas,r8a7796-drif",
"renesas,rcar-gen3-sdhi"; "renesas,rcar-gen3-drif";
reg = <0 0xee140000 0 0x2000>; reg = <0 0xe6fa0000 0 0x64>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>; clocks = <&cpg CPG_MOD 509>;
max-frequency = <200000000>; clock-names = "fck";
dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 312>; resets = <&cpg 509>;
renesas,bonding = <&drif31>;
status = "disabled"; status = "disabled";
}; };
sdhi3: sd@ee160000 { drif31: rif@e6fb0000 {
compatible = "renesas,sdhi-r8a7796", compatible = "renesas,r8a7796-drif",
"renesas,rcar-gen3-sdhi"; "renesas,rcar-gen3-drif";
reg = <0 0xee160000 0 0x2000>; reg = <0 0xe6fb0000 0 0x64>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>; clocks = <&cpg CPG_MOD 508>;
max-frequency = <200000000>; clock-names = "fck";
dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
dma-names = "rx", "rx";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 311>; resets = <&cpg 508>;
renesas,bonding = <&drif30>;
status = "disabled"; status = "disabled";
}; };
tsc: thermal@e6198000 {
compatible = "renesas,r8a7796-thermal";
reg = <0 0xe6198000 0 0x100>,
<0 0xe61a0000 0 0x100>,
<0 0xe61a8000 0 0x100>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 522>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 522>;
#thermal-sensor-cells = <1>;
status = "okay";
};
rcar_sound: sound@ec500000 { rcar_sound: sound@ec500000 {
/* /*
* #sound-dai-cells is required * #sound-dai-cells is required
...@@ -1848,6 +1850,261 @@ ssi9: ssi-9 { ...@@ -1848,6 +1850,261 @@ ssi9: ssi-9 {
dma-names = "rx", "tx", "rxu", "txu"; dma-names = "rx", "tx", "rxu", "txu";
}; };
}; };
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
};
};
};
audma0: dma-controller@ec700000 {
compatible = "renesas,dmac-r8a7796",
"renesas,rcar-dmac";
reg = <0 0xec700000 0 0x10000>;
interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 502>;
clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 502>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
<&ipmmu_mp 2>, <&ipmmu_mp 3>,
<&ipmmu_mp 4>, <&ipmmu_mp 5>,
<&ipmmu_mp 6>, <&ipmmu_mp 7>,
<&ipmmu_mp 8>, <&ipmmu_mp 9>,
<&ipmmu_mp 10>, <&ipmmu_mp 11>,
<&ipmmu_mp 12>, <&ipmmu_mp 13>,
<&ipmmu_mp 14>, <&ipmmu_mp 15>;
};
audma1: dma-controller@ec720000 {
compatible = "renesas,dmac-r8a7796",
"renesas,rcar-dmac";
reg = <0 0xec720000 0 0x10000>;
interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 501>;
clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 501>;
#dma-cells = <1>;
dma-channels = <16>;
iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
<&ipmmu_mp 18>, <&ipmmu_mp 19>,
<&ipmmu_mp 20>, <&ipmmu_mp 21>,
<&ipmmu_mp 22>, <&ipmmu_mp 23>,
<&ipmmu_mp 24>, <&ipmmu_mp 25>,
<&ipmmu_mp 26>, <&ipmmu_mp 27>,
<&ipmmu_mp 28>, <&ipmmu_mp 29>,
<&ipmmu_mp 30>, <&ipmmu_mp 31>;
};
xhci0: usb@ee000000 {
compatible = "renesas,xhci-r8a7796",
"renesas,rcar-gen3-xhci";
reg = <0 0xee000000 0 0xc00>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 328>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 328>;
status = "disabled";
};
usb3_peri0: usb@ee020000 {
compatible = "renesas,r8a7796-usb3-peri",
"renesas,rcar-gen3-usb3-peri";
reg = <0 0xee020000 0 0x400>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 328>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 328>;
status = "disabled";
};
ohci0: usb@ee080000 {
compatible = "generic-ohci";
reg = <0 0xee080000 0 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>;
phys = <&usb2_phy0>;
phy-names = "usb";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 703>;
status = "disabled";
};
ohci1: usb@ee0a0000 {
compatible = "generic-ohci";
reg = <0 0xee0a0000 0 0x100>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 702>;
phys = <&usb2_phy1>;
phy-names = "usb";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 702>;
status = "disabled";
};
ehci0: usb@ee080100 {
compatible = "generic-ehci";
reg = <0 0xee080100 0 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>;
phys = <&usb2_phy0>;
phy-names = "usb";
companion= <&ohci0>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 703>;
status = "disabled";
};
ehci1: usb@ee0a0100 {
compatible = "generic-ehci";
reg = <0 0xee0a0100 0 0x100>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 702>;
phys = <&usb2_phy1>;
phy-names = "usb";
companion= <&ohci1>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 702>;
status = "disabled";
};
usb2_phy0: usb-phy@ee080200 {
compatible = "renesas,usb2-phy-r8a7796",
"renesas,rcar-gen3-usb2-phy";
reg = <0 0xee080200 0 0x700>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 703>;
#phy-cells = <0>;
status = "disabled";
};
usb2_phy1: usb-phy@ee0a0200 {
compatible = "renesas,usb2-phy-r8a7796",
"renesas,rcar-gen3-usb2-phy";
reg = <0 0xee0a0200 0 0x700>;
clocks = <&cpg CPG_MOD 702>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 702>;
#phy-cells = <0>;
status = "disabled";
};
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7796",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
max-frequency = <200000000>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 314>;
status = "disabled";
};
sdhi1: sd@ee120000 {
compatible = "renesas,sdhi-r8a7796",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 313>;
max-frequency = <200000000>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 313>;
status = "disabled";
};
sdhi2: sd@ee140000 {
compatible = "renesas,sdhi-r8a7796",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
max-frequency = <200000000>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 312>;
status = "disabled";
};
sdhi3: sd@ee160000 {
compatible = "renesas,sdhi-r8a7796",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
max-frequency = <200000000>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 311>;
status = "disabled";
};
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xf1010000 0 0x1000>,
<0x0 0xf1020000 0 0x20000>,
<0x0 0xf1040000 0 0x20000>,
<0x0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 408>;
}; };
pciec0: pcie@fe000000 { pciec0: pcie@fe000000 {
...@@ -1860,6 +2117,26 @@ pciec1: pcie@ee800000 { ...@@ -1860,6 +2117,26 @@ pciec1: pcie@ee800000 {
/* placeholder */ /* placeholder */
}; };
imr-lx4@fe860000 {
compatible = "renesas,r8a7796-imr-lx4",
"renesas,imr-lx4";
reg = <0 0xfe860000 0 0x2000>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 823>;
power-domains = <&sysc R8A7796_PD_A3VC>;
resets = <&cpg 823>;
};
imr-lx4@fe870000 {
compatible = "renesas,r8a7796-imr-lx4",
"renesas,imr-lx4";
reg = <0 0xfe870000 0 0x2000>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 822>;
power-domains = <&sysc R8A7796_PD_A3VC>;
resets = <&cpg 822>;
};
fdp1@fe940000 { fdp1@fe940000 {
compatible = "renesas,fdp1"; compatible = "renesas,fdp1";
reg = <0 0xfe940000 0 0x2400>; reg = <0 0xfe940000 0 0x2400>;
...@@ -1878,17 +2155,6 @@ fcpf0: fcp@fe950000 { ...@@ -1878,17 +2155,6 @@ fcpf0: fcp@fe950000 {
resets = <&cpg 615>; resets = <&cpg 615>;
}; };
vspb: vsp@fe960000 {
compatible = "renesas,vsp2";
reg = <0 0xfe960000 0 0x8000>;
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 626>;
power-domains = <&sysc R8A7796_PD_A3VC>;
resets = <&cpg 626>;
renesas,fcp = <&fcpvb0>;
};
fcpvb0: fcp@fe96f000 { fcpvb0: fcp@fe96f000 {
compatible = "renesas,fcpv"; compatible = "renesas,fcpv";
reg = <0 0xfe96f000 0 0x200>; reg = <0 0xfe96f000 0 0x200>;
...@@ -1897,17 +2163,6 @@ fcpvb0: fcp@fe96f000 { ...@@ -1897,17 +2163,6 @@ fcpvb0: fcp@fe96f000 {
resets = <&cpg 607>; resets = <&cpg 607>;
}; };
vspi0: vsp@fe9a0000 {
compatible = "renesas,vsp2";
reg = <0 0xfe9a0000 0 0x8000>;
interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 631>;
power-domains = <&sysc R8A7796_PD_A3VC>;
resets = <&cpg 631>;
renesas,fcp = <&fcpvi0>;
};
fcpvi0: fcp@fe9af000 { fcpvi0: fcp@fe9af000 {
compatible = "renesas,fcpv"; compatible = "renesas,fcpv";
reg = <0 0xfe9af000 0 0x200>; reg = <0 0xfe9af000 0 0x200>;
...@@ -1917,6 +2172,44 @@ fcpvi0: fcp@fe9af000 { ...@@ -1917,6 +2172,44 @@ fcpvi0: fcp@fe9af000 {
iommus = <&ipmmu_vc0 19>; iommus = <&ipmmu_vc0 19>;
}; };
fcpvd0: fcp@fea27000 {
compatible = "renesas,fcpv";
reg = <0 0xfea27000 0 0x200>;
clocks = <&cpg CPG_MOD 603>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 603>;
iommus = <&ipmmu_vi0 8>;
};
fcpvd1: fcp@fea2f000 {
compatible = "renesas,fcpv";
reg = <0 0xfea2f000 0 0x200>;
clocks = <&cpg CPG_MOD 602>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 602>;
iommus = <&ipmmu_vi0 9>;
};
fcpvd2: fcp@fea37000 {
compatible = "renesas,fcpv";
reg = <0 0xfea37000 0 0x200>;
clocks = <&cpg CPG_MOD 601>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 601>;
iommus = <&ipmmu_vi0 10>;
};
vspb: vsp@fe960000 {
compatible = "renesas,vsp2";
reg = <0 0xfe960000 0 0x8000>;
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 626>;
power-domains = <&sysc R8A7796_PD_A3VC>;
resets = <&cpg 626>;
renesas,fcp = <&fcpvb0>;
};
vspd0: vsp@fea20000 { vspd0: vsp@fea20000 {
compatible = "renesas,vsp2"; compatible = "renesas,vsp2";
reg = <0 0xfea20000 0 0x8000>; reg = <0 0xfea20000 0 0x8000>;
...@@ -1928,15 +2221,6 @@ vspd0: vsp@fea20000 { ...@@ -1928,15 +2221,6 @@ vspd0: vsp@fea20000 {
renesas,fcp = <&fcpvd0>; renesas,fcp = <&fcpvd0>;
}; };
fcpvd0: fcp@fea27000 {
compatible = "renesas,fcpv";
reg = <0 0xfea27000 0 0x200>;
clocks = <&cpg CPG_MOD 603>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 603>;
iommus = <&ipmmu_vi0 8>;
};
vspd1: vsp@fea28000 { vspd1: vsp@fea28000 {
compatible = "renesas,vsp2"; compatible = "renesas,vsp2";
reg = <0 0xfea28000 0 0x8000>; reg = <0 0xfea28000 0 0x8000>;
...@@ -1948,15 +2232,6 @@ vspd1: vsp@fea28000 { ...@@ -1948,15 +2232,6 @@ vspd1: vsp@fea28000 {
renesas,fcp = <&fcpvd1>; renesas,fcp = <&fcpvd1>;
}; };
fcpvd1: fcp@fea2f000 {
compatible = "renesas,fcpv";
reg = <0 0xfea2f000 0 0x200>;
clocks = <&cpg CPG_MOD 602>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 602>;
iommus = <&ipmmu_vi0 9>;
};
vspd2: vsp@fea30000 { vspd2: vsp@fea30000 {
compatible = "renesas,vsp2"; compatible = "renesas,vsp2";
reg = <0 0xfea30000 0 0x8000>; reg = <0 0xfea30000 0 0x8000>;
...@@ -1968,13 +2243,126 @@ vspd2: vsp@fea30000 { ...@@ -1968,13 +2243,126 @@ vspd2: vsp@fea30000 {
renesas,fcp = <&fcpvd2>; renesas,fcp = <&fcpvd2>;
}; };
fcpvd2: fcp@fea37000 { vspi0: vsp@fe9a0000 {
compatible = "renesas,fcpv"; compatible = "renesas,vsp2";
reg = <0 0xfea37000 0 0x200>; reg = <0 0xfe9a0000 0 0x8000>;
clocks = <&cpg CPG_MOD 601>; interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 631>;
power-domains = <&sysc R8A7796_PD_A3VC>;
resets = <&cpg 631>;
renesas,fcp = <&fcpvi0>;
};
csi20: csi2@fea80000 {
compatible = "renesas,r8a7796-csi2";
reg = <0 0xfea80000 0 0x10000>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 714>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 601>; resets = <&cpg 714>;
iommus = <&ipmmu_vi0 10>; status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
csi20vin0: endpoint@0 {
reg = <0>;
remote-endpoint = <&vin0csi20>;
};
csi20vin1: endpoint@1 {
reg = <1>;
remote-endpoint = <&vin1csi20>;
};
csi20vin2: endpoint@2 {
reg = <2>;
remote-endpoint = <&vin2csi20>;
};
csi20vin3: endpoint@3 {
reg = <3>;
remote-endpoint = <&vin3csi20>;
};
csi20vin4: endpoint@4 {
reg = <4>;
remote-endpoint = <&vin4csi20>;
};
csi20vin5: endpoint@5 {
reg = <5>;
remote-endpoint = <&vin5csi20>;
};
csi20vin6: endpoint@6 {
reg = <6>;
remote-endpoint = <&vin6csi20>;
};
csi20vin7: endpoint@7 {
reg = <7>;
remote-endpoint = <&vin7csi20>;
};
};
};
};
csi40: csi2@feaa0000 {
compatible = "renesas,r8a7796-csi2";
reg = <0 0xfeaa0000 0 0x10000>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 716>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 716>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
csi40vin0: endpoint@0 {
reg = <0>;
remote-endpoint = <&vin0csi40>;
};
csi40vin1: endpoint@1 {
reg = <1>;
remote-endpoint = <&vin1csi40>;
};
csi40vin2: endpoint@2 {
reg = <2>;
remote-endpoint = <&vin2csi40>;
};
csi40vin3: endpoint@3 {
reg = <3>;
remote-endpoint = <&vin3csi40>;
};
csi40vin4: endpoint@4 {
reg = <4>;
remote-endpoint = <&vin4csi40>;
};
csi40vin5: endpoint@5 {
reg = <5>;
remote-endpoint = <&vin5csi40>;
};
csi40vin6: endpoint@6 {
reg = <6>;
remote-endpoint = <&vin6csi40>;
};
csi40vin7: endpoint@7 {
reg = <7>;
remote-endpoint = <&vin7csi40>;
};
};
};
}; };
hdmi0: hdmi@fead0000 { hdmi0: hdmi@fead0000 {
...@@ -1999,6 +2387,10 @@ dw_hdmi0_in: endpoint { ...@@ -1999,6 +2387,10 @@ dw_hdmi0_in: endpoint {
port@1 { port@1 {
reg = <1>; reg = <1>;
}; };
port@2 {
/* HDMI sound */
reg = <2>;
};
}; };
}; };
...@@ -2042,35 +2434,12 @@ du_out_lvds0: endpoint { ...@@ -2042,35 +2434,12 @@ du_out_lvds0: endpoint {
}; };
}; };
imr-lx4@fe860000 { prr: chipid@fff00044 {
compatible = "renesas,r8a7796-imr-lx4", compatible = "renesas,prr";
"renesas,imr-lx4"; reg = <0 0xfff00044 0 4>;
reg = <0 0xfe860000 0 0x2000>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 823>;
power-domains = <&sysc R8A7796_PD_A3VC>;
resets = <&cpg 823>;
};
imr-lx4@fe870000 {
compatible = "renesas,r8a7796-imr-lx4",
"renesas,imr-lx4";
reg = <0 0xfe870000 0 0x2000>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 822>;
power-domains = <&sysc R8A7796_PD_A3VC>;
resets = <&cpg 822>;
}; };
}; };
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
};
thermal-zones { thermal-zones {
sensor_thermal1: sensor-thermal1 { sensor_thermal1: sensor-thermal1 {
polling-delay-passive = <250>; polling-delay-passive = <250>;
...@@ -2080,12 +2449,12 @@ sensor_thermal1: sensor-thermal1 { ...@@ -2080,12 +2449,12 @@ sensor_thermal1: sensor-thermal1 {
trips { trips {
sensor1_passive: sensor1-passive { sensor1_passive: sensor1-passive {
temperature = <95000>; temperature = <95000>;
hysteresis = <2000>; hysteresis = <1000>;
type = "passive"; type = "passive";
}; };
sensor1_crit: sensor1-crit { sensor1_crit: sensor1-crit {
temperature = <120000>; temperature = <120000>;
hysteresis = <2000>; hysteresis = <1000>;
type = "critical"; type = "critical";
}; };
}; };
...@@ -2106,12 +2475,12 @@ sensor_thermal2: sensor-thermal2 { ...@@ -2106,12 +2475,12 @@ sensor_thermal2: sensor-thermal2 {
trips { trips {
sensor2_passive: sensor2-passive { sensor2_passive: sensor2-passive {
temperature = <95000>; temperature = <95000>;
hysteresis = <2000>; hysteresis = <1000>;
type = "passive"; type = "passive";
}; };
sensor2_crit: sensor2-crit { sensor2_crit: sensor2-crit {
temperature = <120000>; temperature = <120000>;
hysteresis = <2000>; hysteresis = <1000>;
type = "critical"; type = "critical";
}; };
}; };
...@@ -2132,12 +2501,12 @@ sensor_thermal3: sensor-thermal3 { ...@@ -2132,12 +2501,12 @@ sensor_thermal3: sensor-thermal3 {
trips { trips {
sensor3_passive: sensor3-passive { sensor3_passive: sensor3-passive {
temperature = <95000>; temperature = <95000>;
hysteresis = <2000>; hysteresis = <1000>;
type = "passive"; type = "passive";
}; };
sensor3_crit: sensor3-crit { sensor3_crit: sensor3-crit {
temperature = <120000>; temperature = <120000>;
hysteresis = <2000>; hysteresis = <1000>;
type = "critical"; type = "critical";
}; };
}; };
...@@ -2151,6 +2520,14 @@ map0 { ...@@ -2151,6 +2520,14 @@ map0 {
}; };
}; };
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
};
/* External USB clocks - can be overridden by the board */ /* External USB clocks - can be overridden by the board */
usb3s0_clk: usb3s0 { usb3s0_clk: usb3s0 {
compatible = "fixed-clock"; compatible = "fixed-clock";
......
arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts
View file @ 171d429a
...@@ -19,3 +19,31 @@ memory@48000000 { ...@@ -19,3 +19,31 @@ memory@48000000 {
reg = <0x0 0x48000000 0x0 0x78000000>; reg = <0x0 0x48000000 0x0 0x78000000>;
}; };
}; };
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 721>,
<&versaclock5 1>,
<&x21_clk>,
<&versaclock5 2>;
clock-names = "du.0", "du.1", "du.3",
"dclkin.0", "dclkin.1", "dclkin.3";
};
&hdmi0 {
status = "okay";
ports {
port@1 {
reg = <1>;
rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>;
};
};
};
};
&hdmi0_con {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
View file @ 171d429a
...@@ -19,3 +19,31 @@ memory@48000000 { ...@@ -19,3 +19,31 @@ memory@48000000 {
reg = <0x0 0x48000000 0x0 0x78000000>; reg = <0x0 0x48000000 0x0 0x78000000>;
}; };
}; };
&du {
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 721>,
<&versaclock6 1>,
<&x21_clk>,
<&versaclock6 2>;
clock-names = "du.0", "du.1", "du.3",
"dclkin.0", "dclkin.1", "dclkin.3";
};
&hdmi0 {
status = "okay";
ports {
port@1 {
reg = <1>;
rcar_dw_hdmi0_out: endpoint {
remote-endpoint = <&hdmi0_con>;
};
};
};
};
&hdmi0_con {
remote-endpoint = <&rcar_dw_hdmi0_out>;
};
arch/arm64/boot/dts/renesas/r8a77965.dtsi
View file @ 171d429a
...@@ -8,8 +8,9 @@ ...@@ -8,8 +8,9 @@
* Copyright (C) 2016 Renesas Electronics Corp. * Copyright (C) 2016 Renesas Electronics Corp.
*/ */
#include <dt-bindings/clock/renesas-cpg-mssr.h> #include <dt-bindings/clock/r8a77965-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a77965-sysc.h>
#define CPG_AUDIO_CLK_I 10 #define CPG_AUDIO_CLK_I 10
...@@ -19,12 +20,44 @@ / { ...@@ -19,12 +20,44 @@ / {
#size-cells = <2>; #size-cells = <2>;
aliases { aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c_dvfs; i2c7 = &i2c_dvfs;
}; };
psci { /*
compatible = "arm,psci-1.0", "arm,psci-0.2"; * The external audio clocks are configured as 0 Hz fixed frequency
method = "smc"; * clocks by default.
* Boards that provide audio clocks should override them.
*/
audio_clk_a: audio_clk_a {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
audio_clk_b: audio_clk_b {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
audio_clk_c: audio_clk_c {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
}; };
cpus { cpus {
...@@ -35,23 +68,23 @@ a57_0: cpu@0 { ...@@ -35,23 +68,23 @@ a57_0: cpu@0 {
compatible = "arm,cortex-a57", "arm,armv8"; compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x0>; reg = <0x0>;
device_type = "cpu"; device_type = "cpu";
power-domains = <&sysc 0>; power-domains = <&sysc R8A77965_PD_CA57_CPU0>;
next-level-cache = <&L2_CA57>; next-level-cache = <&L2_CA57>;
enable-method = "psci"; enable-method = "psci";
}; };
a57_1: cpu@1 { a57_1: cpu@1 {
compatible = "arm,cortex-a57","arm,armv8"; compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x1>; reg = <0x1>;
device_type = "cpu"; device_type = "cpu";
power-domains = <&sysc 1>; power-domains = <&sysc R8A77965_PD_CA57_CPU1>;
next-level-cache = <&L2_CA57>; next-level-cache = <&L2_CA57>;
enable-method = "psci"; enable-method = "psci";
}; };
L2_CA57: cache-controller-0 { L2_CA57: cache-controller-0 {
compatible = "cache"; compatible = "cache";
power-domains = <&sysc 12>; power-domains = <&sysc R8A77965_PD_CA57_SCU>;
cache-unified; cache-unified;
cache-level = <2>; cache-level = <2>;
}; };
...@@ -71,34 +104,24 @@ extalr_clk: extalr { ...@@ -71,34 +104,24 @@ extalr_clk: extalr {
clock-frequency = <0>; clock-frequency = <0>;
}; };
/* /* External PCIe clock - can be overridden by the board */
* The external audio clocks are configured as 0 Hz fixed frequency pcie_bus_clk: pcie_bus {
* clocks by default.
* Boards that provide audio clocks should override them.
*/
audio_clk_a: audio_clk_a {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
audio_clk_b: audio_clk_b {
compatible = "fixed-clock"; compatible = "fixed-clock";
#clock-cells = <0>; #clock-cells = <0>;
clock-frequency = <0>; clock-frequency = <0>;
}; };
audio_clk_c: audio_clk_c { pmu_a57 {
compatible = "fixed-clock"; compatible = "arm,cortex-a57-pmu";
#clock-cells = <0>; interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
clock-frequency = <0>; <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a57_0>,
<&a57_1>;
}; };
/* External CAN clock - to be overridden by boards that provide it */ psci {
can_clk: can { compatible = "arm,psci-1.0", "arm,psci-0.2";
compatible = "fixed-clock"; method = "smc";
#clock-cells = <0>;
clock-frequency = <0>;
}; };
/* External SCIF clock - to be overridden by boards that provide it */ /* External SCIF clock - to be overridden by boards that provide it */
...@@ -108,42 +131,6 @@ scif_clk: scif { ...@@ -108,42 +131,6 @@ scif_clk: scif {
clock-frequency = <0>; clock-frequency = <0>;
}; };
/* External PCIe clock - can be overridden by the board */
pcie_bus_clk: pcie_bus {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
/* External USB clocks - can be overridden by the board */
usb3s0_clk: usb3s0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
usb_extal_clk: usb_extal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu_a57 {
compatible = "arm,cortex-a57-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a57_0>,
<&a57_1>;
};
soc { soc {
compatible = "simple-bus"; compatible = "simple-bus";
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
...@@ -151,52 +138,9 @@ soc { ...@@ -151,52 +138,9 @@ soc {
#size-cells = <2>; #size-cells = <2>;
ranges; ranges;
gic: interrupt-controller@f1010000 { wdt0: watchdog@e6020000 {
compatible = "arm,gic-400"; reg = <0 0xe6020000 0 0x0c>;
#interrupt-cells = <3>; /* placeholder */
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xf1010000 0 0x1000>,
<0x0 0xf1020000 0 0x20000>,
<0x0 0xf1040000 0 0x20000>,
<0x0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc 32>;
resets = <&cpg 408>;
};
pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a77965";
reg = <0 0xe6060000 0 0x50c>;
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a77965-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
clocks = <&extal_clk>, <&extalr_clk>;
clock-names = "extal", "extalr";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};
rst: reset-controller@e6160000 {
compatible = "renesas,r8a77965-rst";
reg = <0 0xe6160000 0 0x0200>;
};
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a77965-sysc";
reg = <0 0xe6180000 0 0x0400>;
#power-domain-cells = <1>;
}; };
gpio0: gpio@e6050000 { gpio0: gpio@e6050000 {
...@@ -210,7 +154,7 @@ gpio0: gpio@e6050000 { ...@@ -210,7 +154,7 @@ gpio0: gpio@e6050000 {
#interrupt-cells = <2>; #interrupt-cells = <2>;
interrupt-controller; interrupt-controller;
clocks = <&cpg CPG_MOD 912>; clocks = <&cpg CPG_MOD 912>;
power-domains = <&sysc 32>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 912>; resets = <&cpg 912>;
}; };
...@@ -225,7 +169,7 @@ gpio1: gpio@e6051000 { ...@@ -225,7 +169,7 @@ gpio1: gpio@e6051000 {
#interrupt-cells = <2>; #interrupt-cells = <2>;
interrupt-controller; interrupt-controller;
clocks = <&cpg CPG_MOD 911>; clocks = <&cpg CPG_MOD 911>;
power-domains = <&sysc 32>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 911>; resets = <&cpg 911>;
}; };
...@@ -240,7 +184,7 @@ gpio2: gpio@e6052000 { ...@@ -240,7 +184,7 @@ gpio2: gpio@e6052000 {
#interrupt-cells = <2>; #interrupt-cells = <2>;
interrupt-controller; interrupt-controller;
clocks = <&cpg CPG_MOD 910>; clocks = <&cpg CPG_MOD 910>;
power-domains = <&sysc 32>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 910>; resets = <&cpg 910>;
}; };
...@@ -255,7 +199,7 @@ gpio3: gpio@e6053000 { ...@@ -255,7 +199,7 @@ gpio3: gpio@e6053000 {
#interrupt-cells = <2>; #interrupt-cells = <2>;
interrupt-controller; interrupt-controller;
clocks = <&cpg CPG_MOD 909>; clocks = <&cpg CPG_MOD 909>;
power-domains = <&sysc 32>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 909>; resets = <&cpg 909>;
}; };
...@@ -270,7 +214,7 @@ gpio4: gpio@e6054000 { ...@@ -270,7 +214,7 @@ gpio4: gpio@e6054000 {
#interrupt-cells = <2>; #interrupt-cells = <2>;
interrupt-controller; interrupt-controller;
clocks = <&cpg CPG_MOD 908>; clocks = <&cpg CPG_MOD 908>;
power-domains = <&sysc 32>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 908>; resets = <&cpg 908>;
}; };
...@@ -285,7 +229,7 @@ gpio5: gpio@e6055000 { ...@@ -285,7 +229,7 @@ gpio5: gpio@e6055000 {
#interrupt-cells = <2>; #interrupt-cells = <2>;
interrupt-controller; interrupt-controller;
clocks = <&cpg CPG_MOD 907>; clocks = <&cpg CPG_MOD 907>;
power-domains = <&sysc 32>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 907>; resets = <&cpg 907>;
}; };
...@@ -300,7 +244,7 @@ gpio6: gpio@e6055400 { ...@@ -300,7 +244,7 @@ gpio6: gpio@e6055400 {
#interrupt-cells = <2>; #interrupt-cells = <2>;
interrupt-controller; interrupt-controller;
clocks = <&cpg CPG_MOD 906>; clocks = <&cpg CPG_MOD 906>;
power-domains = <&sysc 32>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 906>; resets = <&cpg 906>;
}; };
...@@ -315,10 +259,51 @@ gpio7: gpio@e6055800 { ...@@ -315,10 +259,51 @@ gpio7: gpio@e6055800 {
#interrupt-cells = <2>; #interrupt-cells = <2>;
interrupt-controller; interrupt-controller;
clocks = <&cpg CPG_MOD 905>; clocks = <&cpg CPG_MOD 905>;
power-domains = <&sysc 32>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 905>; resets = <&cpg 905>;
}; };
pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a77965";
reg = <0 0xe6060000 0 0x50c>;
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a77965-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
clocks = <&extal_clk>, <&extalr_clk>;
clock-names = "extal", "extalr";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};
rst: reset-controller@e6160000 {
compatible = "renesas,r8a77965-rst";
reg = <0 0xe6160000 0 0x0200>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a77965-sysc";
reg = <0 0xe6180000 0 0x0400>;
#power-domain-cells = <1>;
};
tsc: thermal@e6198000 {
compatible = "renesas,r8a77965-thermal";
reg = <0 0xe6198000 0 0x100>,
<0 0xe61a0000 0 0x100>,
<0 0xe61a8000 0 0x100>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 522>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 522>;
#thermal-sensor-cells = <1>;
status = "okay";
};
intc_ex: interrupt-controller@e61c0000 { intc_ex: interrupt-controller@e61c0000 {
compatible = "renesas,intc-ex-r8a77965", "renesas,irqc"; compatible = "renesas,intc-ex-r8a77965", "renesas,irqc";
#interrupt-cells = <2>; #interrupt-cells = <2>;
...@@ -331,84 +316,273 @@ GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH ...@@ -331,84 +316,273 @@ GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 407>; clocks = <&cpg CPG_MOD 407>;
power-domains = <&sysc 32>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 407>; resets = <&cpg 407>;
}; };
dmac0: dma-controller@e6700000 { i2c0: i2c@e6500000 {
compatible = "renesas,dmac-r8a77965", #address-cells = <1>;
"renesas,rcar-dmac"; #size-cells = <0>;
reg = <0 0xe6700000 0 0x10000>; compatible = "renesas,i2c-r8a77965",
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH "renesas,rcar-gen3-i2c";
GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH reg = <0 0xe6500000 0 0x40>;
GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH clocks = <&cpg CPG_MOD 931>;
GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH resets = <&cpg 931>;
GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH dmas = <&dmac1 0x91>, <&dmac1 0x90>,
GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH <&dmac2 0x91>, <&dmac2 0x90>;
GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH dma-names = "tx", "rx", "tx", "rx";
GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH i2c-scl-internal-delay-ns = <110>;
GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH status = "disabled";
GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 219>;
clock-names = "fck";
power-domains = <&sysc 32>;
resets = <&cpg 219>;
#dma-cells = <1>;
dma-channels = <16>;
}; };
dmac1: dma-controller@e7300000 { i2c1: i2c@e6508000 {
compatible = "renesas,dmac-r8a77965", #address-cells = <1>;
"renesas,rcar-dmac"; #size-cells = <0>;
reg = <0 0xe7300000 0 0x10000>; compatible = "renesas,i2c-r8a77965",
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH "renesas,rcar-gen3-i2c";
GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH reg = <0 0xe6508000 0 0x40>;
GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH clocks = <&cpg CPG_MOD 930>;
GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH resets = <&cpg 930>;
GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH dmas = <&dmac1 0x93>, <&dmac1 0x92>,
GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH <&dmac2 0x93>, <&dmac2 0x92>;
GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH dma-names = "tx", "rx", "tx", "rx";
GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH i2c-scl-internal-delay-ns = <6>;
GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH status = "disabled";
GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 218>;
clock-names = "fck";
power-domains = <&sysc 32>;
resets = <&cpg 218>;
#dma-cells = <1>;
dma-channels = <16>;
}; };
dmac2: dma-controller@e7310000 { i2c2: i2c@e6510000 {
compatible = "renesas,dmac-r8a77965", #address-cells = <1>;
"renesas,rcar-dmac"; #size-cells = <0>;
reg = <0 0xe7310000 0 0x10000>; compatible = "renesas,i2c-r8a77965",
interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH "renesas,rcar-gen3-i2c";
GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH reg = <0 0xe6510000 0 0x40>;
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 929>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 929>;
dmas = <&dmac1 0x95>, <&dmac1 0x94>,
<&dmac2 0x95>, <&dmac2 0x94>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c3: i2c@e66d0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a77965",
"renesas,rcar-gen3-i2c";
reg = <0 0xe66d0000 0 0x40>;
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 928>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 928>;
dmas = <&dmac0 0x97>, <&dmac0 0x96>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
status = "disabled";
};
i2c4: i2c@e66d8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a77965",
"renesas,rcar-gen3-i2c";
reg = <0 0xe66d8000 0 0x40>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 927>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 927>;
dmas = <&dmac0 0x99>, <&dmac0 0x98>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
status = "disabled";
};
i2c5: i2c@e66e0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a77965",
"renesas,rcar-gen3-i2c";
reg = <0 0xe66e0000 0 0x40>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 919>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 919>;
dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
status = "disabled";
};
i2c6: i2c@e66e8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a77965",
"renesas,rcar-gen3-i2c";
reg = <0 0xe66e8000 0 0x40>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 918>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 918>;
dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c_dvfs: i2c@e60b0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,iic-r8a77965",
"renesas,rcar-gen3-iic",
"renesas,rmobile-iic";
reg = <0 0xe60b0000 0 0x425>;
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 926>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 926>;
dmas = <&dmac0 0x11>, <&dmac0 0x10>;
dma-names = "tx", "rx";
status = "disabled";
};
hsusb: usb@e6590000 {
compatible = "renesas,usbhs-r8a7796",
"renesas,rcar-gen3-usbhs";
reg = <0 0xe6590000 0 0x100>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 704>;
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
<&usb_dmac1 0>, <&usb_dmac1 1>;
dma-names = "ch0", "ch1", "ch2", "ch3";
renesas,buswait = <11>;
phys = <&usb2_phy0>;
phy-names = "usb";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 704>;
status = "disabled";
};
usb_dmac0: dma-controller@e65a0000 {
compatible = "renesas,r8a77965-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65a0000 0 0x100>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 330>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 330>;
#dma-cells = <1>;
dma-channels = <2>;
};
usb_dmac1: dma-controller@e65b0000 {
compatible = "renesas,r8a77965-usb-dmac",
"renesas,usb-dmac";
reg = <0 0xe65b0000 0 0x100>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&cpg CPG_MOD 331>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 331>;
#dma-cells = <1>;
dma-channels = <2>;
};
usb3_phy0: usb-phy@e65ee000 {
compatible = "renesas,r8a77965-usb3-phy",
"renesas,rcar-gen3-usb3-phy";
reg = <0 0xe65ee000 0 0x90>;
clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
<&usb_extal_clk>;
clock-names = "usb3-if", "usb3s_clk", "usb_extal";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 328>;
#phy-cells = <0>;
status = "disabled";
};
dmac0: dma-controller@e6700000 {
compatible = "renesas,dmac-r8a77965",
"renesas,rcar-dmac";
reg = <0 0xe6700000 0 0x10000>;
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 219>;
clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 219>;
#dma-cells = <1>;
dma-channels = <16>;
};
dmac1: dma-controller@e7300000 {
compatible = "renesas,dmac-r8a77965",
"renesas,rcar-dmac";
reg = <0 0xe7300000 0 0x10000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 218>;
clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 218>;
#dma-cells = <1>;
dma-channels = <16>;
};
dmac2: dma-controller@e7310000 {
compatible = "renesas,dmac-r8a77965",
"renesas,rcar-dmac";
reg = <0 0xe7310000 0 0x10000>;
interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
...@@ -431,12 +605,127 @@ GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH ...@@ -431,12 +605,127 @@ GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
"ch12", "ch13", "ch14", "ch15"; "ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 217>; clocks = <&cpg CPG_MOD 217>;
clock-names = "fck"; clock-names = "fck";
power-domains = <&sysc 32>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 217>; resets = <&cpg 217>;
#dma-cells = <1>; #dma-cells = <1>;
dma-channels = <16>; dma-channels = <16>;
}; };
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a77965",
"renesas,etheravb-rcar-gen3";
reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15",
"ch16", "ch17", "ch18", "ch19",
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pwm0: pwm@e6e30000 {
compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
reg = <0 0xe6e30000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
status = "disabled";
};
pwm1: pwm@e6e31000 {
compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
reg = <0 0xe6e31000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
status = "disabled";
};
pwm2: pwm@e6e32000 {
compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
reg = <0 0xe6e32000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
status = "disabled";
};
pwm3: pwm@e6e33000 {
compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
reg = <0 0xe6e33000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
status = "disabled";
};
pwm4: pwm@e6e34000 {
compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
reg = <0 0xe6e34000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
status = "disabled";
};
pwm5: pwm@e6e35000 {
compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
reg = <0 0xe6e35000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
status = "disabled";
};
pwm6: pwm@e6e36000 {
compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
reg = <0 0xe6e36000 0 8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
resets = <&cpg 523>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
status = "disabled";
};
scif0: serial@e6e60000 { scif0: serial@e6e60000 {
compatible = "renesas,scif-r8a77965", compatible = "renesas,scif-r8a77965",
"renesas,rcar-gen3-scif", "renesas,scif"; "renesas,rcar-gen3-scif", "renesas,scif";
...@@ -449,7 +738,7 @@ scif0: serial@e6e60000 { ...@@ -449,7 +738,7 @@ scif0: serial@e6e60000 {
dmas = <&dmac1 0x51>, <&dmac1 0x50>, dmas = <&dmac1 0x51>, <&dmac1 0x50>,
<&dmac2 0x51>, <&dmac2 0x50>; <&dmac2 0x51>, <&dmac2 0x50>;
dma-names = "tx", "rx", "tx", "rx"; dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 207>; resets = <&cpg 207>;
status = "disabled"; status = "disabled";
}; };
...@@ -466,7 +755,7 @@ scif1: serial@e6e68000 { ...@@ -466,7 +755,7 @@ scif1: serial@e6e68000 {
dmas = <&dmac1 0x53>, <&dmac1 0x52>, dmas = <&dmac1 0x53>, <&dmac1 0x52>,
<&dmac2 0x53>, <&dmac2 0x52>; <&dmac2 0x53>, <&dmac2 0x52>;
dma-names = "tx", "rx", "tx", "rx"; dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 206>; resets = <&cpg 206>;
status = "disabled"; status = "disabled";
}; };
...@@ -480,7 +769,7 @@ scif2: serial@e6e88000 { ...@@ -480,7 +769,7 @@ scif2: serial@e6e88000 {
<&cpg CPG_CORE 20>, <&cpg CPG_CORE 20>,
<&scif_clk>; <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&sysc 32>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 310>; resets = <&cpg 310>;
status = "disabled"; status = "disabled";
}; };
...@@ -496,7 +785,7 @@ scif3: serial@e6c50000 { ...@@ -496,7 +785,7 @@ scif3: serial@e6c50000 {
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x57>, <&dmac0 0x56>; dmas = <&dmac0 0x57>, <&dmac0 0x56>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
power-domains = <&sysc 32>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 204>; resets = <&cpg 204>;
status = "disabled"; status = "disabled";
}; };
...@@ -512,7 +801,7 @@ scif4: serial@e6c40000 { ...@@ -512,7 +801,7 @@ scif4: serial@e6c40000 {
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x59>, <&dmac0 0x58>; dmas = <&dmac0 0x59>, <&dmac0 0x58>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
power-domains = <&sysc 32>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 203>; resets = <&cpg 203>;
status = "disabled"; status = "disabled";
}; };
...@@ -529,243 +818,772 @@ scif5: serial@e6f30000 { ...@@ -529,243 +818,772 @@ scif5: serial@e6f30000 {
dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
<&dmac2 0x5b>, <&dmac2 0x5a>; <&dmac2 0x5b>, <&dmac2 0x5a>;
dma-names = "tx", "rx", "tx", "rx"; dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 202>; resets = <&cpg 202>;
status = "disabled"; status = "disabled";
}; };
avb: ethernet@e6800000 { msiof0: spi@e6e90000 {
compatible = "renesas,etheravb-r8a77965", compatible = "renesas,msiof-r8a77965",
"renesas,etheravb-rcar-gen3"; "renesas,rcar-gen3-msiof";
reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; reg = <0 0xe6e90000 0 0x0064>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, clocks = <&cpg CPG_MOD 211>;
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, dmas = <&dmac1 0x41>, <&dmac1 0x40>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, <&dmac2 0x41>, <&dmac2 0x40>;
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, dma-names = "tx", "rx", "tx", "rx";
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, resets = <&cpg 211>;
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15",
"ch16", "ch17", "ch18", "ch19",
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc 32>;
resets = <&cpg 812>;
phy-mode = "rgmii";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
status = "disabled"; status = "disabled";
}; };
csi20: csi2@fea80000 { msiof1: spi@e6ea0000 {
reg = <0 0xfea80000 0 0x10000>; compatible = "renesas,msiof-r8a77965",
/* placeholder */ "renesas,rcar-gen3-msiof";
reg = <0 0xe6ea0000 0 0x0064>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 210>;
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
<&dmac2 0x43>, <&dmac2 0x42>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 210>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof2: spi@e6c00000 {
compatible = "renesas,msiof-r8a77965",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6c00000 0 0x0064>;
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 209>;
dmas = <&dmac0 0x45>, <&dmac0 0x44>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 209>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof3: spi@e6c10000 {
compatible = "renesas,msiof-r8a77965",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6c10000 0 0x0064>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 208>;
dmas = <&dmac0 0x47>, <&dmac0 0x46>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 208>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
vin0: video@e6ef0000 {
compatible = "renesas,vin-r8a77965";
reg = <0 0xe6ef0000 0 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 811>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 811>;
renesas,id = <0>;
status = "disabled";
ports { ports {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin0csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin0>;
};
vin0csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin0>;
};
};
}; };
}; };
csi40: csi2@feaa0000 { vin1: video@e6ef1000 {
reg = <0 0xfeaa0000 0 0x10000>; compatible = "renesas,vin-r8a77965";
/* placeholder */ reg = <0 0xe6ef1000 0 0x1000>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 810>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 810>;
renesas,id = <1>;
status = "disabled";
ports { ports {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
};
};
vin0: video@e6ef0000 { port@1 {
reg = <0 0xe6ef0000 0 0x1000>; #address-cells = <1>;
/* placeholder */ #size-cells = <0>;
};
vin1: video@e6ef1000 { reg = <1>;
reg = <0 0xe6ef1000 0 0x1000>;
/* placeholder */ vin1csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin1>;
};
vin1csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin1>;
};
};
};
}; };
vin2: video@e6ef2000 { vin2: video@e6ef2000 {
compatible = "renesas,vin-r8a77965";
reg = <0 0xe6ef2000 0 0x1000>; reg = <0 0xe6ef2000 0 0x1000>;
/* placeholder */ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 809>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 809>;
renesas,id = <2>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin2csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin2>;
};
vin2csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin2>;
};
};
};
}; };
vin3: video@e6ef3000 { vin3: video@e6ef3000 {
compatible = "renesas,vin-r8a77965";
reg = <0 0xe6ef3000 0 0x1000>; reg = <0 0xe6ef3000 0 0x1000>;
/* placeholder */ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 808>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 808>;
renesas,id = <3>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin3csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin3>;
};
vin3csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin3>;
};
};
};
}; };
vin4: video@e6ef4000 { vin4: video@e6ef4000 {
compatible = "renesas,vin-r8a77965";
reg = <0 0xe6ef4000 0 0x1000>; reg = <0 0xe6ef4000 0 0x1000>;
/* placeholder */ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 807>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 807>;
renesas,id = <4>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin4csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin4>;
};
vin4csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin4>;
};
};
};
}; };
vin5: video@e6ef5000 { vin5: video@e6ef5000 {
compatible = "renesas,vin-r8a77965";
reg = <0 0xe6ef5000 0 0x1000>; reg = <0 0xe6ef5000 0 0x1000>;
/* placeholder */ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 806>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 806>;
renesas,id = <5>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin5csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin5>;
};
vin5csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin5>;
};
};
};
}; };
vin6: video@e6ef6000 { vin6: video@e6ef6000 {
compatible = "renesas,vin-r8a77965";
reg = <0 0xe6ef6000 0 0x1000>; reg = <0 0xe6ef6000 0 0x1000>;
/* placeholder */ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 805>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 805>;
renesas,id = <6>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin6csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin6>;
};
vin6csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin6>;
};
};
};
}; };
vin7: video@e6ef7000 { vin7: video@e6ef7000 {
compatible = "renesas,vin-r8a77965";
reg = <0 0xe6ef7000 0 0x1000>; reg = <0 0xe6ef7000 0 0x1000>;
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 804>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 804>;
renesas,id = <7>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin7csi20: endpoint@0 {
reg = <0>;
remote-endpoint= <&csi20vin7>;
};
vin7csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin7>;
};
};
};
};
rcar_sound: sound@ec500000 {
reg = <0 0xec500000 0 0x1000>, /* SCU */
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
<0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
/* placeholder */ /* placeholder */
rcar_sound,dvc {
dvc0: dvc-0 {
};
dvc1: dvc-1 {
};
};
rcar_sound,src {
src0: src-0 {
};
src1: src-1 {
};
};
rcar_sound,ssi {
ssi0: ssi-0 {
};
ssi1: ssi-1 {
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
};
};
xhci0: usb@ee000000 {
compatible = "renesas,xhci-r8a77965",
"renesas,rcar-gen3-xhci";
reg = <0 0xee000000 0 0xc00>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 328>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 328>;
status = "disabled";
};
usb3_peri0: usb@ee020000 {
compatible = "renesas,r8a77965-usb3-peri",
"renesas,rcar-gen3-usb3-peri";
reg = <0 0xee020000 0 0x400>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 328>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 328>;
status = "disabled";
}; };
ohci0: usb@ee080000 { ohci0: usb@ee080000 {
compatible = "generic-ohci";
reg = <0 0xee080000 0 0x100>; reg = <0 0xee080000 0 0x100>;
/* placeholder */ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>;
phys = <&usb2_phy0>;
phy-names = "usb";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 703>;
status = "disabled";
};
ohci1: usb@ee0a0000 {
compatible = "generic-ohci";
reg = <0 0xee0a0000 0 0x100>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 702>;
phys = <&usb2_phy1>;
phy-names = "usb";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 702>;
status = "disabled";
}; };
ehci0: usb@ee080100 { ehci0: usb@ee080100 {
compatible = "generic-ehci";
reg = <0 0xee080100 0 0x100>; reg = <0 0xee080100 0 0x100>;
/* placeholder */ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>;
phys = <&usb2_phy0>;
phy-names = "usb";
companion = <&ohci0>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 703>;
status = "disabled";
};
ehci1: usb@ee0a0100 {
compatible = "generic-ehci";
reg = <0 0xee0a0100 0 0x100>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 702>;
phys = <&usb2_phy1>;
phy-names = "usb";
companion = <&ohci1>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 702>;
status = "disabled";
}; };
usb2_phy0: usb-phy@ee080200 { usb2_phy0: usb-phy@ee080200 {
compatible = "renesas,usb2-phy-r8a77965",
"renesas,rcar-gen3-usb2-phy";
reg = <0 0xee080200 0 0x700>; reg = <0 0xee080200 0 0x700>;
/* placeholder */ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 703>;
#phy-cells = <0>;
status = "disabled";
}; };
usb2_phy1: usb-phy@ee0a0200 { usb2_phy1: usb-phy@ee0a0200 {
compatible = "renesas,usb2-phy-r8a77965",
"renesas,rcar-gen3-usb2-phy";
reg = <0 0xee0a0200 0 0x700>; reg = <0 0xee0a0200 0 0x700>;
/* placeholder */ clocks = <&cpg CPG_MOD 703>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 703>;
#phy-cells = <0>;
status = "disabled";
}; };
ohci1: usb@ee0a0000 { sdhi0: sd@ee100000 {
reg = <0 0xee0a0000 0 0x100>; compatible = "renesas,sdhi-r8a77965",
/* placeholder */ "renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
max-frequency = <200000000>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 314>;
status = "disabled";
}; };
ehci1: usb@ee0a0100 { sdhi1: sd@ee120000 {
reg = <0 0xee0a0100 0 0x100>; compatible = "renesas,sdhi-r8a77965",
/* placeholder */ "renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 313>;
max-frequency = <200000000>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 313>;
status = "disabled";
}; };
i2c0: i2c@e6500000 { sdhi2: sd@ee140000 {
reg = <0 0xe6500000 0 0x40>; compatible = "renesas,sdhi-r8a77965",
/* placeholder */ "renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
max-frequency = <200000000>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 312>;
status = "disabled";
}; };
i2c1: i2c@e6508000 { sdhi3: sd@ee160000 {
reg = <0 0xe6508000 0 0x40>; compatible = "renesas,sdhi-r8a77965",
/* placeholder */ "renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
max-frequency = <200000000>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 311>;
status = "disabled";
}; };
i2c2: i2c@e6510000 { gic: interrupt-controller@f1010000 {
#address-cells = <1>; compatible = "arm,gic-400";
#size-cells = <0>; #interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xf1010000 0 0x1000>,
<0x0 0xf1020000 0 0x20000>,
<0x0 0xf1040000 0 0x20000>,
<0x0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 408>;
};
reg = <0 0xe6510000 0 0x40>; pciec0: pcie@fe000000 {
reg = <0 0xfe000000 0 0x80000>;
/* placeholder */ /* placeholder */
}; };
i2c3: i2c@e66d0000 { pciec1: pcie@ee800000 {
reg = <0 0xe66d0000 0 0x40>; reg = <0 0xee800000 0 0x80000>;
/* placeholder */ /* placeholder */
}; };
i2c4: i2c@e66d8000 { fcpf0: fcp@fe950000 {
#address-cells = <1>; compatible = "renesas,fcpf";
#size-cells = <0>; reg = <0 0xfe950000 0 0x200>;
clocks = <&cpg CPG_MOD 615>;
power-domains = <&sysc R8A77965_PD_A3VP>;
resets = <&cpg 615>;
};
reg = <0 0xe66d8000 0 0x40>; vspb: vsp@fe960000 {
/* placeholder */ compatible = "renesas,vsp2";
reg = <0 0xfe960000 0 0x8000>;
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 626>;
power-domains = <&sysc R8A77965_PD_A3VP>;
resets = <&cpg 626>;
renesas,fcp = <&fcpvb0>;
}; };
i2c5: i2c@e66e0000 { fcpvb0: fcp@fe96f000 {
reg = <0 0xe66e0000 0 0x40>; compatible = "renesas,fcpv";
/* placeholder */ reg = <0 0xfe96f000 0 0x200>;
clocks = <&cpg CPG_MOD 607>;
power-domains = <&sysc R8A77965_PD_A3VP>;
resets = <&cpg 607>;
}; };
i2c6: i2c@e66e8000 { vspi0: vsp@fe9a0000 {
reg = <0 0xe66e8000 0 0x40>; compatible = "renesas,vsp2";
/* placeholder */ reg = <0 0xfe9a0000 0 0x8000>;
interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 631>;
power-domains = <&sysc R8A77965_PD_A3VP>;
resets = <&cpg 631>;
renesas,fcp = <&fcpvi0>;
}; };
i2c_dvfs: i2c@e60b0000 { fcpvi0: fcp@fe9af000 {
#address-cells = <1>; compatible = "renesas,fcpv";
#size-cells = <0>; reg = <0 0xfe9af000 0 0x200>;
compatible = "renesas,iic-r8a77965", clocks = <&cpg CPG_MOD 611>;
"renesas,rcar-gen3-iic", power-domains = <&sysc R8A77965_PD_A3VP>;
"renesas,rmobile-iic"; resets = <&cpg 611>;
reg = <0 0xe60b0000 0 0x425>;
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 926>;
power-domains = <&sysc 32>;
resets = <&cpg 926>;
dmas = <&dmac0 0x11>, <&dmac0 0x10>;
dma-names = "tx", "rx";
status = "disabled";
}; };
pwm0: pwm@e6e30000 { vspd0: vsp@fea20000 {
reg = <0 0xe6e30000 0 8>; compatible = "renesas,vsp2";
/* placeholder */ reg = <0 0xfea20000 0 0x8000>;
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 623>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 623>;
renesas,fcp = <&fcpvd0>;
}; };
pwm1: pwm@e6e31000 { fcpvd0: fcp@fea27000 {
reg = <0 0xe6e31000 0 8>; compatible = "renesas,fcpv";
#pwm-cells = <2>; reg = <0 0xfea27000 0 0x200>;
/* placeholder */ clocks = <&cpg CPG_MOD 603>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 603>;
}; };
pwm2: pwm@e6e32000 { vspd1: vsp@fea28000 {
reg = <0 0xe6e32000 0 8>; compatible = "renesas,vsp2";
/* placeholder */ reg = <0 0xfea28000 0 0x8000>;
interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 622>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 622>;
renesas,fcp = <&fcpvd1>;
}; };
pwm3: pwm@e6e33000 { fcpvd1: fcp@fea2f000 {
reg = <0 0xe6e33000 0 8>; compatible = "renesas,fcpv";
/* placeholder */ reg = <0 0xfea2f000 0 0x200>;
clocks = <&cpg CPG_MOD 602>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 602>;
}; };
pwm4: pwm@e6e34000 { csi20: csi2@fea80000 {
reg = <0 0xe6e34000 0 8>; compatible = "renesas,r8a77965-csi2";
/* placeholder */ reg = <0 0xfea80000 0 0x10000>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 714>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 714>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
csi20vin0: endpoint@0 {
reg = <0>;
remote-endpoint = <&vin0csi20>;
};
csi20vin1: endpoint@1 {
reg = <1>;
remote-endpoint = <&vin1csi20>;
};
csi20vin2: endpoint@2 {
reg = <2>;
remote-endpoint = <&vin2csi20>;
};
csi20vin3: endpoint@3 {
reg = <3>;
remote-endpoint = <&vin3csi20>;
};
csi20vin4: endpoint@4 {
reg = <4>;
remote-endpoint = <&vin4csi20>;
};
csi20vin5: endpoint@5 {
reg = <5>;
remote-endpoint = <&vin5csi20>;
};
csi20vin6: endpoint@6 {
reg = <6>;
remote-endpoint = <&vin6csi20>;
};
csi20vin7: endpoint@7 {
reg = <7>;
remote-endpoint = <&vin7csi20>;
};
};
};
}; };
pwm5: pwm@e6e35000 { csi40: csi2@feaa0000 {
reg = <0 0xe6e35000 0 8>; compatible = "renesas,r8a77965-csi2";
/* placeholder */ reg = <0 0xfeaa0000 0 0x10000>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 716>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 716>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
csi40vin0: endpoint@0 {
reg = <0>;
remote-endpoint = <&vin0csi40>;
};
csi40vin1: endpoint@1 {
reg = <1>;
remote-endpoint = <&vin1csi40>;
};
csi40vin2: endpoint@2 {
reg = <2>;
remote-endpoint = <&vin2csi40>;
};
csi40vin3: endpoint@3 {
reg = <3>;
remote-endpoint = <&vin3csi40>;
};
csi40vin4: endpoint@4 {
reg = <4>;
remote-endpoint = <&vin4csi40>;
};
csi40vin5: endpoint@5 {
reg = <5>;
remote-endpoint = <&vin5csi40>;
};
csi40vin6: endpoint@6 {
reg = <6>;
remote-endpoint = <&vin6csi40>;
};
csi40vin7: endpoint@7 {
reg = <7>;
remote-endpoint = <&vin7csi40>;
};
};
};
}; };
pwm6: pwm@e6e36000 { hdmi0: hdmi@fead0000 {
reg = <0 0xe6e36000 0 8>; compatible = "renesas,r8a77965-hdmi",
/* placeholder */ "renesas,rcar-gen3-hdmi";
reg = <0 0xfead0000 0 0x10000>;
interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 729>,
<&cpg CPG_CORE R8A77965_CLK_HDMI>;
clock-names = "iahb", "isfr";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 729>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dw_hdmi0_in: endpoint {
remote-endpoint = <&du_out_hdmi0>;
};
};
port@1 {
reg = <1>;
};
};
}; };
du: display@feb00000 { du: display@feb00000 {
reg = <0 0xfeb00000 0 0x80000>, compatible = "renesas,du-r8a77965";
<0 0xfeb90000 0 0x14>; reg = <0 0xfeb00000 0 0x80000>;
/* placeholder */ reg-names = "du";
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 721>;
clock-names = "du.0", "du.1", "du.3";
status = "disabled";
vsps = <&vspd0 0 &vspd1 0 &vspd0 1>;
ports { ports {
#address-cells = <1>; #address-cells = <1>;
...@@ -779,6 +1597,7 @@ du_out_rgb: endpoint { ...@@ -779,6 +1597,7 @@ du_out_rgb: endpoint {
port@1 { port@1 {
reg = <1>; reg = <1>;
du_out_hdmi0: endpoint { du_out_hdmi0: endpoint {
remote-endpoint = <&dw_hdmi0_in>;
}; };
}; };
port@2 { port@2 {
...@@ -789,90 +1608,74 @@ du_out_lvds0: endpoint { ...@@ -789,90 +1608,74 @@ du_out_lvds0: endpoint {
}; };
}; };
hsusb: usb@e6590000 { prr: chipid@fff00044 {
reg = <0 0xe6590000 0 0x100>; compatible = "renesas,prr";
/* placeholder */ reg = <0 0xfff00044 0 4>;
};
pciec0: pcie@fe000000 {
reg = <0 0xfe000000 0 0x80000>;
/* placeholder */
};
pciec1: pcie@ee800000 {
reg = <0 0xee800000 0 0x80000>;
/* placeholder */
}; };
};
rcar_sound: sound@ec500000 { timer {
reg = <0 0xec500000 0 0x1000>, /* SCU */ compatible = "arm,armv8-timer";
<0 0xec5a0000 0 0x100>, /* ADG */ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<0 0xec540000 0 0x1000>, /* SSIU */ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<0 0xec541000 0 0x280>, /* SSI */ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
/* placeholder */ };
rcar_sound,dvc { thermal-zones {
dvc0: dvc-0 { sensor_thermal1: sensor-thermal1 {
}; polling-delay-passive = <250>;
dvc1: dvc-1 { polling-delay = <1000>;
thermal-sensors = <&tsc 0>;
trips {
sensor1_crit: sensor1-crit {
temperature = <120000>;
hysteresis = <1000>;
type = "critical";
}; };
}; };
};
rcar_sound,src { sensor_thermal2: sensor-thermal2 {
src0: src-0 { polling-delay-passive = <250>;
}; polling-delay = <1000>;
src1: src-1 { thermal-sensors = <&tsc 1>;
};
};
rcar_sound,ssi { trips {
ssi0: ssi-0 { sensor2_crit: sensor2-crit {
}; temperature = <120000>;
ssi1: ssi-1 { hysteresis = <1000>;
type = "critical";
}; };
}; };
}; };
sdhi0: sd@ee100000 { sensor_thermal3: sensor-thermal3 {
reg = <0 0xee100000 0 0x2000>; polling-delay-passive = <250>;
/* placeholder */ polling-delay = <1000>;
}; thermal-sensors = <&tsc 2>;
sdhi1: sd@ee120000 {
reg = <0 0xee120000 0 0x2000>;
/* placeholder */
};
sdhi2: sd@ee140000 { trips {
reg = <0 0xee140000 0 0x2000>; sensor3_crit: sensor3-crit {
/* placeholder */ temperature = <120000>;
}; hysteresis = <1000>;
type = "critical";
sdhi3: sd@ee160000 { };
reg = <0 0xee160000 0 0x2000>; };
/* placeholder */
};
usb3_phy0: usb-phy@e65ee000 {
reg = <0 0xe65ee000 0 0x90>;
#phy-cells = <0>;
/* placeholder */
};
usb3_peri0: usb@ee020000 {
reg = <0 0xee020000 0 0x400>;
/* placeholder */
}; };
};
xhci0: usb@ee000000 { /* External USB clocks - can be overridden by the board */
reg = <0 0xee000000 0 0xc00>; usb3s0_clk: usb3s0 {
/* placeholder */ compatible = "fixed-clock";
}; #clock-cells = <0>;
clock-frequency = <0>;
};
wdt0: watchdog@e6020000 { usb_extal_clk: usb_extal {
reg = <0 0xe6020000 0 0x0c>; compatible = "fixed-clock";
/* placeholder */ #clock-cells = <0>;
}; clock-frequency = <0>;
}; };
}; };
arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
View file @ 171d429a
...@@ -31,9 +31,57 @@ memory@48000000 { ...@@ -31,9 +31,57 @@ memory@48000000 {
/* first 128MB is reserved for secure area. */ /* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>; reg = <0x0 0x48000000 0x0 0x38000000>;
}; };
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_out: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
d3p3: regulator-fixed {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
lvds-decoder {
compatible = "thine,thc63lvd1024";
vcc-supply = <&d3p3>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
thc63lvd1024_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
port@2 {
reg = <2>;
thc63lvd1024_out: endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
}; };
&avb { &avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
renesas,no-ether-link; renesas,no-ether-link;
phy-handle = <&phy0>; phy-handle = <&phy0>;
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
...@@ -47,6 +95,16 @@ phy0: ethernet-phy@0 { ...@@ -47,6 +95,16 @@ phy0: ethernet-phy@0 {
}; };
}; };
&canfd {
pinctrl-0 = <&canfd0_pins>;
pinctrl-names = "default";
status = "okay";
channel0 {
status = "okay";
};
};
&extal_clk { &extal_clk {
clock-frequency = <16666666>; clock-frequency = <16666666>;
}; };
...@@ -68,9 +126,51 @@ io_expander: gpio@20 { ...@@ -68,9 +126,51 @@ io_expander: gpio@20 {
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
}; };
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&gpio1>;
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&thc63lvd1024_out>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con_out>;
};
};
};
};
}; };
&pfc { &pfc {
avb_pins: avb0 {
groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
function = "avb0";
};
canfd0_pins: canfd0 {
groups = "canfd0_data_a";
function = "canfd0";
};
i2c0_pins: i2c0 { i2c0_pins: i2c0 {
groups = "i2c0"; groups = "i2c0";
function = "i2c0"; function = "i2c0";
...@@ -93,3 +193,19 @@ &scif0 { ...@@ -93,3 +193,19 @@ &scif0 {
status = "okay"; status = "okay";
}; };
&du {
status = "okay";
};
&lvds0 {
status = "okay";
ports {
port@1 {
lvds0_out: endpoint {
remote-endpoint = <&thc63lvd1024_in>;
};
};
};
};
arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
View file @ 171d429a
...@@ -29,9 +29,71 @@ memory@48000000 { ...@@ -29,9 +29,71 @@ memory@48000000 {
/* first 128MB is reserved for secure area. */ /* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>; reg = <0x0 0x48000000 0x0 0x38000000>;
}; };
osc5_clk: osc5-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <148500000>;
};
vcc_d1_8v: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "VCC_D1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
vcc_d3_3v: regulator-1 {
compatible = "regulator-fixed";
regulator-name = "VCC_D3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
lvds-decoder {
compatible = "thine,thc63lvd1024";
vcc-supply = <&vcc_d3_3v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
thc63lvd1024_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
port@2 {
reg = <2>;
thc63lvd1024_out: endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
}; };
&avb { &avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
renesas,no-ether-link; renesas,no-ether-link;
phy-handle = <&phy0>; phy-handle = <&phy0>;
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
...@@ -43,6 +105,13 @@ phy0: ethernet-phy@0 { ...@@ -43,6 +105,13 @@ phy0: ethernet-phy@0 {
}; };
}; };
&du {
clocks = <&cpg CPG_MOD 724>,
<&osc5_clk>;
clock-names = "du.0", "dclkin.0";
status = "okay";
};
&extal_clk { &extal_clk {
clock-frequency = <16666666>; clock-frequency = <16666666>;
}; };
...@@ -52,12 +121,80 @@ &extalr_clk { ...@@ -52,12 +121,80 @@ &extalr_clk {
}; };
&pfc { &pfc {
avb_pins: avb0 {
groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
function = "avb0";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
scif0_pins: scif0 { scif0_pins: scif0 {
groups = "scif0_data"; groups = "scif0_data";
function = "scif0"; function = "scif0";
}; };
}; };
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
hdmi@39{
compatible = "adi,adv7511w";
#sound-dai-cells = <0>;
reg = <0x39>;
interrupt-parent = <&gpio1>;
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
avdd-supply = <&vcc_d1_8v>;
dvdd-supply = <&vcc_d1_8v>;
pvdd-supply = <&vcc_d1_8v>;
bgvdd-supply = <&vcc_d1_8v>;
dvdd-3v-supply = <&vcc_d3_3v>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&thc63lvd1024_out>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
};
&lvds0 {
status = "okay";
ports {
port@1 {
lvds0_out: endpoint {
remote-endpoint = <&thc63lvd1024_in>;
};
};
};
};
&scif0 { &scif0 {
pinctrl-0 = <&scif0_pins>; pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
......
arch/arm64/boot/dts/renesas/r8a77970.dtsi
View file @ 171d429a
...@@ -41,6 +41,16 @@ a53_0: cpu@0 { ...@@ -41,6 +41,16 @@ a53_0: cpu@0 {
enable-method = "psci"; enable-method = "psci";
}; };
a53_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <1>;
clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
power-domains = <&sysc R8A77970_PD_CA53_CPU1>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
};
L2_CA53: cache-controller { L2_CA53: cache-controller {
compatible = "cache"; compatible = "cache";
power-domains = <&sysc R8A77970_PD_CA53_SCU>; power-domains = <&sysc R8A77970_PD_CA53_SCU>;
...@@ -63,11 +73,25 @@ extalr_clk: extalr { ...@@ -63,11 +73,25 @@ extalr_clk: extalr {
clock-frequency = <0>; clock-frequency = <0>;
}; };
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a53_0>, <&a53_1>;
};
psci { psci {
compatible = "arm,psci-1.0", "arm,psci-0.2"; compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc"; method = "smc";
}; };
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
/* External SCIF clock - to be overridden by boards that provide it */ /* External SCIF clock - to be overridden by boards that provide it */
scif_clk: scif { scif_clk: scif {
compatible = "fixed-clock"; compatible = "fixed-clock";
...@@ -83,23 +107,6 @@ soc { ...@@ -83,23 +107,6 @@ soc {
#size-cells = <2>; #size-cells = <2>;
ranges; ranges;
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0 0xf1010000 0 0x1000>,
<0 0xf1020000 0 0x20000>,
<0 0xf1040000 0 0x20000>,
<0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 408>;
};
rwdt: watchdog@e6020000 { rwdt: watchdog@e6020000 {
compatible = "renesas,r8a77970-wdt", compatible = "renesas,r8a77970-wdt",
"renesas,rcar-gen3-wdt"; "renesas,rcar-gen3-wdt";
...@@ -110,75 +117,6 @@ rwdt: watchdog@e6020000 { ...@@ -110,75 +117,6 @@ rwdt: watchdog@e6020000 {
status = "disabled"; status = "disabled";
}; };
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a77970-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
clocks = <&extal_clk>, <&extalr_clk>;
clock-names = "extal", "extalr";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};
rst: reset-controller@e6160000 {
compatible = "renesas,r8a77970-rst";
reg = <0 0xe6160000 0 0x200>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a77970-sysc";
reg = <0 0xe6180000 0 0x440>;
#power-domain-cells = <1>;
};
ipmmu_vi0: mmu@febd0000 {
compatible = "renesas,ipmmu-r8a77970";
reg = <0 0xfebd0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 9>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_ir: mmu@ff8b0000 {
compatible = "renesas,ipmmu-r8a77970";
reg = <0 0xff8b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 3>;
power-domains = <&sysc R8A77970_PD_A3IR>;
#iommu-cells = <1>;
status = "disabled";
};
ipmmu_rt: mmu@ffc80000 {
compatible = "renesas,ipmmu-r8a77970";
reg = <0 0xffc80000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 7>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_ds1: mmu@e7740000 {
compatible = "renesas,ipmmu-r8a77970";
reg = <0 0xe7740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 1>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_mm: mmu@e67b0000 {
compatible = "renesas,ipmmu-r8a77970";
reg = <0 0xe67b0000 0 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a77970";
reg = <0 0xe6060000 0 0x504>;
};
gpio0: gpio@e6050000 { gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a77970", compatible = "renesas,gpio-r8a77970",
"renesas,rcar-gen3-gpio"; "renesas,rcar-gen3-gpio";
...@@ -269,6 +207,32 @@ gpio5: gpio@e6055000 { ...@@ -269,6 +207,32 @@ gpio5: gpio@e6055000 {
resets = <&cpg 907>; resets = <&cpg 907>;
}; };
pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a77970";
reg = <0 0xe6060000 0 0x504>;
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a77970-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
clocks = <&extal_clk>, <&extalr_clk>;
clock-names = "extal", "extalr";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};
rst: reset-controller@e6160000 {
compatible = "renesas,r8a77970-rst";
reg = <0 0xe6160000 0 0x200>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a77970-sysc";
reg = <0 0xe6180000 0 0x440>;
#power-domain-cells = <1>;
};
intc_ex: interrupt-controller@e61c0000 { intc_ex: interrupt-controller@e61c0000 {
compatible = "renesas,intc-ex-r8a77970", "renesas,irqc"; compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
#interrupt-cells = <2>; #interrupt-cells = <2>;
...@@ -285,67 +249,6 @@ GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH ...@@ -285,67 +249,6 @@ GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
resets = <&cpg 407>; resets = <&cpg 407>;
}; };
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
};
dmac1: dma-controller@e7300000 {
compatible = "renesas,dmac-r8a77970",
"renesas,rcar-dmac";
reg = <0 0xe7300000 0 0x10000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7";
clocks = <&cpg CPG_MOD 218>;
clock-names = "fck";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 218>;
#dma-cells = <1>;
dma-channels = <8>;
iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
<&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
<&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
<&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
};
dmac2: dma-controller@e7310000 {
compatible = "renesas,dmac-r8a77970",
"renesas,rcar-dmac";
reg = <0 0xe7310000 0 0x10000>;
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7";
clocks = <&cpg CPG_MOD 217>;
clock-names = "fck";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 217>;
#dma-cells = <1>;
dma-channels = <8>;
iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
<&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
<&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
<&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
};
i2c0: i2c@e6500000 { i2c0: i2c@e6500000 {
compatible = "renesas,i2c-r8a77970", compatible = "renesas,i2c-r8a77970",
"renesas,rcar-gen3-i2c"; "renesas,rcar-gen3-i2c";
...@@ -502,6 +405,77 @@ hscif3: serial@e66a0000 { ...@@ -502,6 +405,77 @@ hscif3: serial@e66a0000 {
status = "disabled"; status = "disabled";
}; };
canfd: can@e66c0000 {
compatible = "renesas,r8a77970-canfd",
"renesas,rcar-gen3-canfd";
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A77970_CLK_CANFD>,
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A77970_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";
channel0 {
status = "disabled";
};
channel1 {
status = "disabled";
};
};
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a77970",
"renesas,etheravb-rcar-gen3";
reg = <0 0xe6800000 0 0x800>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15",
"ch16", "ch17", "ch18", "ch19",
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
iommus = <&ipmmu_rt 3>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
scif0: serial@e6e60000 { scif0: serial@e6e60000 {
compatible = "renesas,scif-r8a77970", compatible = "renesas,scif-r8a77970",
"renesas,rcar-gen3-scif", "renesas,rcar-gen3-scif",
...@@ -573,57 +547,358 @@ scif4: serial@e6c40000 { ...@@ -573,57 +547,358 @@ scif4: serial@e6c40000 {
status = "disabled"; status = "disabled";
}; };
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a77970", vin0: video@e6ef0000 {
"renesas,etheravb-rcar-gen3"; compatible = "renesas,vin-r8a77970";
reg = <0 0xe6800000 0 0x800>; reg = <0 0xe6ef0000 0 0x1000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, clocks = <&cpg CPG_MOD 811>;
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15",
"ch16", "ch17", "ch18", "ch19",
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 812>; resets = <&cpg 811>;
phy-mode = "rgmii"; renesas,id = <0>;
iommus = <&ipmmu_rt 3>; status = "disabled";
#address-cells = <1>;
#size-cells = <0>; ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin0csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin0>;
};
};
};
};
vin1: video@e6ef1000 {
compatible = "renesas,vin-r8a77970";
reg = <0 0xe6ef1000 0 0x1000>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 810>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 810>;
renesas,id = <1>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin1csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin1>;
};
};
};
};
vin2: video@e6ef2000 {
compatible = "renesas,vin-r8a77970";
reg = <0 0xe6ef2000 0 0x1000>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 809>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 809>;
renesas,id = <2>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin2csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin2>;
};
};
};
};
vin3: video@e6ef3000 {
compatible = "renesas,vin-r8a77970";
reg = <0 0xe6ef3000 0 0x1000>;
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 808>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 808>;
renesas,id = <3>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
vin3csi40: endpoint@2 {
reg = <2>;
remote-endpoint= <&csi40vin3>;
};
};
};
};
dmac1: dma-controller@e7300000 {
compatible = "renesas,dmac-r8a77970",
"renesas,rcar-dmac";
reg = <0 0xe7300000 0 0x10000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7";
clocks = <&cpg CPG_MOD 218>;
clock-names = "fck";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 218>;
#dma-cells = <1>;
dma-channels = <8>;
iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
<&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
<&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
<&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
};
dmac2: dma-controller@e7310000 {
compatible = "renesas,dmac-r8a77970",
"renesas,rcar-dmac";
reg = <0 0xe7310000 0 0x10000>;
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7";
clocks = <&cpg CPG_MOD 217>;
clock-names = "fck";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 217>;
#dma-cells = <1>;
dma-channels = <8>;
iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
<&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
<&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
<&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
};
ipmmu_ds1: mmu@e7740000 {
compatible = "renesas,ipmmu-r8a77970";
reg = <0 0xe7740000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 0>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_ir: mmu@ff8b0000 {
compatible = "renesas,ipmmu-r8a77970";
reg = <0 0xff8b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 3>;
power-domains = <&sysc R8A77970_PD_A3IR>;
#iommu-cells = <1>;
};
ipmmu_mm: mmu@e67b0000 {
compatible = "renesas,ipmmu-r8a77970";
reg = <0 0xe67b0000 0 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_rt: mmu@ffc80000 {
compatible = "renesas,ipmmu-r8a77970";
reg = <0 0xffc80000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 7>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
ipmmu_vi0: mmu@febd0000 {
compatible = "renesas,ipmmu-r8a77970";
reg = <0 0xfebd0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 9>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0 0xf1010000 0 0x1000>,
<0 0xf1020000 0 0x20000>,
<0 0xf1040000 0 0x20000>,
<0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 408>;
};
vspd0: vsp@fea20000 {
compatible = "renesas,vsp2";
reg = <0 0xfea20000 0 0x8000>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 623>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 623>;
renesas,fcp = <&fcpvd0>;
};
fcpvd0: fcp@fea27000 {
compatible = "renesas,fcpv";
reg = <0 0xfea27000 0 0x200>;
clocks = <&cpg CPG_MOD 603>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 603>;
};
csi40: csi2@feaa0000 {
compatible = "renesas,r8a77970-csi2";
reg = <0 0xfeaa0000 0 0x10000>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 716>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 716>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
csi40vin0: endpoint@0 {
reg = <0>;
remote-endpoint = <&vin0csi40>;
};
csi40vin1: endpoint@1 {
reg = <1>;
remote-endpoint = <&vin1csi40>;
};
csi40vin2: endpoint@2 {
reg = <2>;
remote-endpoint = <&vin2csi40>;
};
csi40vin3: endpoint@3 {
reg = <3>;
remote-endpoint = <&vin3csi40>;
};
};
};
};
du: display@feb00000 {
compatible = "renesas,du-r8a77970";
reg = <0 0xfeb00000 0 0x80000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>;
clock-names = "du.0";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 724>;
vsps = <&vspd0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
du_out_rgb: endpoint {
};
};
port@1 {
reg = <1>;
du_out_lvds0: endpoint {
remote-endpoint = <&lvds0_in>;
};
};
};
};
lvds0: lvds-encoder@feb90000 {
compatible = "renesas,r8a77970-lvds";
reg = <0 0xfeb90000 0 0x14>;
clocks = <&cpg CPG_MOD 727>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 727>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds0_in: endpoint {
remote-endpoint =
<&du_out_lvds0>;
};
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
}; };
}; };
timer { timer {
compatible = "arm,armv8-timer"; compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
}; };
}; };
arch/arm64/boot/dts/renesas/r8a77980-condor.dts
View file @ 171d429a
...@@ -27,9 +27,30 @@ memory@48000000 { ...@@ -27,9 +27,30 @@ memory@48000000 {
/* first 128MB is reserved for secure area. */ /* first 128MB is reserved for secure area. */
reg = <0 0x48000000 0 0x78000000>; reg = <0 0x48000000 0 0x78000000>;
}; };
d3_3v: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "D3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vddq_vin01: regulator-1 {
compatible = "regulator-fixed";
regulator-name = "VDDQ_VIN01";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
}; };
&avb { &avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
phy-handle = <&phy0>; phy-handle = <&phy0>;
renesas,no-ether-link; renesas,no-ether-link;
...@@ -41,6 +62,16 @@ phy0: ethernet-phy@0 { ...@@ -41,6 +62,16 @@ phy0: ethernet-phy@0 {
}; };
}; };
&canfd {
pinctrl-0 = <&canfd0_pins>;
pinctrl-names = "default";
status = "okay";
channel0 {
status = "okay";
};
};
&extal_clk { &extal_clk {
clock-frequency = <16666666>; clock-frequency = <16666666>;
}; };
...@@ -49,7 +80,57 @@ &extalr_clk { ...@@ -49,7 +80,57 @@ &extalr_clk {
clock-frequency = <32768>; clock-frequency = <32768>;
}; };
&mmc0 {
pinctrl-0 = <&mmc_pins>;
pinctrl-1 = <&mmc_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&d3_3v>;
vqmmc-supply = <&vddq_vin01>;
mmc-hs200-1_8v;
bus-width = <8>;
non-removable;
status = "okay";
};
&pfc {
avb_pins: avb {
groups = "avb_mdio", "avb_rgmii";
function = "avb";
};
canfd0_pins: canfd0 {
groups = "canfd0_data_a";
function = "canfd0";
};
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
power-source = <3300>;
};
mmc_pins_uhs: mmc_uhs {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
power-source = <1800>;
};
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_b";
function = "scif_clk";
};
};
&scif0 { &scif0 {
pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
pinctrl-names = "default";
status = "okay"; status = "okay";
}; };
......
arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts 0 → 100644
View file @ 171d429a
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the V3H Starter Kit board
*
* Copyright (C) 2018 Renesas Electronics Corp.
* Copyright (C) 2018 Cogent Embedded, Inc.
*/
/dts-v1/;
#include "r8a77980.dtsi"
/ {
model = "Renesas V3H Starter Kit board";
compatible = "renesas,v3hsk", "renesas,r8a77980";
aliases {
serial0 = &scif0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0 0x48000000 0 0x78000000>;
};
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&pfc {
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_b";
function = "scif_clk";
};
};
&scif0 {
pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
};
arch/arm64/boot/dts/renesas/r8a77980.dtsi
View file @ 171d429a
...@@ -6,9 +6,10 @@ ...@@ -6,9 +6,10 @@
* Copyright (C) 2018 Cogent Embedded, Inc. * Copyright (C) 2018 Cogent Embedded, Inc.
*/ */
#include <dt-bindings/clock/r8a77980-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/renesas-cpg-mssr.h> #include <dt-bindings/power/r8a77980-sysc.h>
/ { / {
compatible = "renesas,r8a77980"; compatible = "renesas,r8a77980";
...@@ -23,20 +24,27 @@ a53_0: cpu@0 { ...@@ -23,20 +24,27 @@ a53_0: cpu@0 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8"; compatible = "arm,cortex-a53", "arm,armv8";
reg = <0>; reg = <0>;
clocks = <&cpg CPG_CORE 0>; clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
power-domains = <&sysc 5>; power-domains = <&sysc R8A77980_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>; next-level-cache = <&L2_CA53>;
enable-method = "psci"; enable-method = "psci";
}; };
L2_CA53: cache-controller { L2_CA53: cache-controller {
compatible = "cache"; compatible = "cache";
power-domains = <&sysc 21>; power-domains = <&sysc R8A77980_PD_CA53_SCU>;
cache-unified; cache-unified;
cache-level = <2>; cache-level = <2>;
}; };
}; };
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
extal_clk: extal { extal_clk: extal {
compatible = "fixed-clock"; compatible = "fixed-clock";
#clock-cells = <0>; #clock-cells = <0>;
...@@ -71,6 +79,11 @@ soc { ...@@ -71,6 +79,11 @@ soc {
#size-cells = <2>; #size-cells = <2>;
ranges; ranges;
pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a77980";
reg = <0 0xe6060000 0 0x50c>;
};
cpg: clock-controller@e6150000 { cpg: clock-controller@e6150000 {
compatible = "renesas,r8a77980-cpg-mssr"; compatible = "renesas,r8a77980-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>; reg = <0 0xe6150000 0 0x1000>;
...@@ -99,13 +112,13 @@ hscif0: serial@e6540000 { ...@@ -99,13 +112,13 @@ hscif0: serial@e6540000 {
reg = <0 0xe6540000 0 0x60>; reg = <0 0xe6540000 0 0x60>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 520>, clocks = <&cpg CPG_MOD 520>,
<&cpg CPG_CORE 19>, <&cpg CPG_CORE R8A77980_CLK_S3D1>,
<&scif_clk>; <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x31>, <&dmac1 0x30>, dmas = <&dmac1 0x31>, <&dmac1 0x30>,
<&dmac2 0x31>, <&dmac2 0x30>; <&dmac2 0x31>, <&dmac2 0x30>;
dma-names = "tx", "rx", "tx", "rx"; dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 520>; resets = <&cpg 520>;
status = "disabled"; status = "disabled";
}; };
...@@ -117,13 +130,13 @@ hscif1: serial@e6550000 { ...@@ -117,13 +130,13 @@ hscif1: serial@e6550000 {
reg = <0 0xe6550000 0 0x60>; reg = <0 0xe6550000 0 0x60>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 519>, clocks = <&cpg CPG_MOD 519>,
<&cpg CPG_CORE 19>, <&cpg CPG_CORE R8A77980_CLK_S3D1>,
<&scif_clk>; <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x33>, <&dmac1 0x32>, dmas = <&dmac1 0x33>, <&dmac1 0x32>,
<&dmac2 0x33>, <&dmac2 0x32>; <&dmac2 0x33>, <&dmac2 0x32>;
dma-names = "tx", "rx", "tx", "rx"; dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 519>; resets = <&cpg 519>;
status = "disabled"; status = "disabled";
}; };
...@@ -135,13 +148,13 @@ hscif2: serial@e6560000 { ...@@ -135,13 +148,13 @@ hscif2: serial@e6560000 {
reg = <0 0xe6560000 0 0x60>; reg = <0 0xe6560000 0 0x60>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 518>, clocks = <&cpg CPG_MOD 518>,
<&cpg CPG_CORE 19>, <&cpg CPG_CORE R8A77980_CLK_S3D1>,
<&scif_clk>; <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x35>, <&dmac1 0x34>, dmas = <&dmac1 0x35>, <&dmac1 0x34>,
<&dmac2 0x35>, <&dmac2 0x34>; <&dmac2 0x35>, <&dmac2 0x34>;
dma-names = "tx", "rx", "tx", "rx"; dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 518>; resets = <&cpg 518>;
status = "disabled"; status = "disabled";
}; };
...@@ -153,17 +166,42 @@ hscif3: serial@e66a0000 { ...@@ -153,17 +166,42 @@ hscif3: serial@e66a0000 {
reg = <0 0xe66a0000 0 0x60>; reg = <0 0xe66a0000 0 0x60>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 517>, clocks = <&cpg CPG_MOD 517>,
<&cpg CPG_CORE 19>, <&cpg CPG_CORE R8A77980_CLK_S3D1>,
<&scif_clk>; <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x37>, <&dmac1 0x36>, dmas = <&dmac1 0x37>, <&dmac1 0x36>,
<&dmac2 0x37>, <&dmac2 0x36>; <&dmac2 0x37>, <&dmac2 0x36>;
dma-names = "tx", "rx", "tx", "rx"; dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 517>; resets = <&cpg 517>;
status = "disabled"; status = "disabled";
}; };
canfd: can@e66c0000 {
compatible = "renesas,r8a77980-canfd",
"renesas,rcar-gen3-canfd";
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A77980_CLK_CANFD>,
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";
channel0 {
status = "disabled";
};
channel1 {
status = "disabled";
};
};
avb: ethernet@e6800000 { avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a77980", compatible = "renesas,etheravb-r8a77980",
"renesas,etheravb-rcar-gen3"; "renesas,etheravb-rcar-gen3";
...@@ -201,11 +239,12 @@ avb: ethernet@e6800000 { ...@@ -201,11 +239,12 @@ avb: ethernet@e6800000 {
"ch20", "ch21", "ch22", "ch23", "ch20", "ch21", "ch22", "ch23",
"ch24"; "ch24";
clocks = <&cpg CPG_MOD 812>; clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc 32>; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 812>; resets = <&cpg 812>;
phy-mode = "rgmii"; phy-mode = "rgmii";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
status = "disabled";
}; };
scif0: serial@e6e60000 { scif0: serial@e6e60000 {
...@@ -215,13 +254,13 @@ scif0: serial@e6e60000 { ...@@ -215,13 +254,13 @@ scif0: serial@e6e60000 {
reg = <0 0xe6e60000 0 0x40>; reg = <0 0xe6e60000 0 0x40>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 207>, clocks = <&cpg CPG_MOD 207>,
<&cpg CPG_CORE 19>, <&cpg CPG_CORE R8A77980_CLK_S3D1>,
<&scif_clk>; <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x51>, <&dmac1 0x50>, dmas = <&dmac1 0x51>, <&dmac1 0x50>,
<&dmac2 0x51>, <&dmac2 0x50>; <&dmac2 0x51>, <&dmac2 0x50>;
dma-names = "tx", "rx", "tx", "rx"; dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 207>; resets = <&cpg 207>;
status = "disabled"; status = "disabled";
}; };
...@@ -233,13 +272,13 @@ scif1: serial@e6e68000 { ...@@ -233,13 +272,13 @@ scif1: serial@e6e68000 {
reg = <0 0xe6e68000 0 0x40>; reg = <0 0xe6e68000 0 0x40>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 206>, clocks = <&cpg CPG_MOD 206>,
<&cpg CPG_CORE 19>, <&cpg CPG_CORE R8A77980_CLK_S3D1>,
<&scif_clk>; <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x53>, <&dmac1 0x52>, dmas = <&dmac1 0x53>, <&dmac1 0x52>,
<&dmac2 0x53>, <&dmac2 0x52>; <&dmac2 0x53>, <&dmac2 0x52>;
dma-names = "tx", "rx", "tx", "rx"; dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 206>; resets = <&cpg 206>;
status = "disabled"; status = "disabled";
}; };
...@@ -251,13 +290,13 @@ scif3: serial@e6c50000 { ...@@ -251,13 +290,13 @@ scif3: serial@e6c50000 {
reg = <0 0xe6c50000 0 0x40>; reg = <0 0xe6c50000 0 0x40>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 204>, clocks = <&cpg CPG_MOD 204>,
<&cpg CPG_CORE 19>, <&cpg CPG_CORE R8A77980_CLK_S3D1>,
<&scif_clk>; <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x57>, <&dmac1 0x56>, dmas = <&dmac1 0x57>, <&dmac1 0x56>,
<&dmac2 0x57>, <&dmac2 0x56>; <&dmac2 0x57>, <&dmac2 0x56>;
dma-names = "tx", "rx", "tx", "rx"; dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 204>; resets = <&cpg 204>;
status = "disabled"; status = "disabled";
}; };
...@@ -269,13 +308,13 @@ scif4: serial@e6c40000 { ...@@ -269,13 +308,13 @@ scif4: serial@e6c40000 {
reg = <0 0xe6c40000 0 0x40>; reg = <0 0xe6c40000 0 0x40>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 203>, clocks = <&cpg CPG_MOD 203>,
<&cpg CPG_CORE 19>, <&cpg CPG_CORE R8A77980_CLK_S3D1>,
<&scif_clk>; <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x59>, <&dmac1 0x58>, dmas = <&dmac1 0x59>, <&dmac1 0x58>,
<&dmac2 0x59>, <&dmac2 0x58>; <&dmac2 0x59>, <&dmac2 0x58>;
dma-names = "tx", "rx", "tx", "rx"; dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 203>; resets = <&cpg 203>;
status = "disabled"; status = "disabled";
}; };
...@@ -308,7 +347,7 @@ GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH ...@@ -308,7 +347,7 @@ GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH
"ch12", "ch13", "ch14", "ch15"; "ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 218>; clocks = <&cpg CPG_MOD 218>;
clock-names = "fck"; clock-names = "fck";
power-domains = <&sysc 32>; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 218>; resets = <&cpg 218>;
#dma-cells = <1>; #dma-cells = <1>;
dma-channels = <16>; dma-channels = <16>;
...@@ -342,12 +381,24 @@ GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH ...@@ -342,12 +381,24 @@ GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH
"ch12", "ch13", "ch14", "ch15"; "ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD 217>; clocks = <&cpg CPG_MOD 217>;
clock-names = "fck"; clock-names = "fck";
power-domains = <&sysc 32>; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 217>; resets = <&cpg 217>;
#dma-cells = <1>; #dma-cells = <1>;
dma-channels = <16>; dma-channels = <16>;
}; };
mmc0: mmc@ee140000 {
compatible = "renesas,sdhi-r8a77980",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 314>;
max-frequency = <200000000>;
status = "disabled";
};
gic: interrupt-controller@f1010000 { gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400"; compatible = "arm,gic-400";
#interrupt-cells = <3>; #interrupt-cells = <3>;
...@@ -361,7 +412,7 @@ gic: interrupt-controller@f1010000 { ...@@ -361,7 +412,7 @@ gic: interrupt-controller@f1010000 {
IRQ_TYPE_LEVEL_HIGH)>; IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>; clocks = <&cpg CPG_MOD 408>;
clock-names = "clk"; clock-names = "clk";
power-domains = <&sysc 32>; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 408>; resets = <&cpg 408>;
}; };
......
arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts 0 → 100644
View file @ 171d429a
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Device Tree Source for the ebisu board
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a77990.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Renesas Ebisu board based on r8a77990";
compatible = "renesas,ebisu", "renesas,r8a77990";
aliases {
serial0 = &scif2;
ethernet0 = &avb;
};
chosen {
bootargs = "ignore_loglevel";
stdout-path = "serial0:115200n8";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
phy-mode = "rgmii-txid";
status = "okay";
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
};
};
&extal_clk {
clock-frequency = <48000000>;
};
&pfc {
avb_pins: avb {
mux {
groups = "avb_link", "avb_mii";
function = "avb";
};
};
};
&scif2 {
status = "okay";
};
arch/arm64/boot/dts/renesas/r8a77990.dtsi 0 → 100644
View file @ 171d429a
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Device Tree Source for the r8a77990 SoC
*
* Copyright (C) 2018 Renesas Electronics Corp.
*/
#include <dt-bindings/clock/renesas-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "renesas,r8a77990";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
/* 1 core only at this point */
a53_0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0>;
device_type = "cpu";
power-domains = <&sysc 5>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
};
L2_CA53: cache-controller-0 {
compatible = "cache";
power-domains = <&sysc 21>;
cache-unified;
cache-level = <2>;
};
};
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&a53_0>;
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a77990",
"renesas,rcar-gen3-gpio";
reg = <0 0xe6050000 0 0x50>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 0 18>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 912>;
power-domains = <&sysc 32>;
resets = <&cpg 912>;
};
gpio1: gpio@e6051000 {
compatible = "renesas,gpio-r8a77990",
"renesas,rcar-gen3-gpio";
reg = <0 0xe6051000 0 0x50>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 32 23>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 911>;
power-domains = <&sysc 32>;
resets = <&cpg 911>;
};
gpio2: gpio@e6052000 {
compatible = "renesas,gpio-r8a77990",
"renesas,rcar-gen3-gpio";
reg = <0 0xe6052000 0 0x50>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 64 26>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 910>;
power-domains = <&sysc 32>;
resets = <&cpg 910>;
};
gpio3: gpio@e6053000 {
compatible = "renesas,gpio-r8a77990",
"renesas,rcar-gen3-gpio";
reg = <0 0xe6053000 0 0x50>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 96 16>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 909>;
power-domains = <&sysc 32>;
resets = <&cpg 909>;
};
gpio4: gpio@e6054000 {
compatible = "renesas,gpio-r8a77990",
"renesas,rcar-gen3-gpio";
reg = <0 0xe6054000 0 0x50>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 128 11>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 908>;
power-domains = <&sysc 32>;
resets = <&cpg 908>;
};
gpio5: gpio@e6055000 {
compatible = "renesas,gpio-r8a77990",
"renesas,rcar-gen3-gpio";
reg = <0 0xe6055000 0 0x50>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 160 20>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 907>;
power-domains = <&sysc 32>;
resets = <&cpg 907>;
};
gpio6: gpio@e6055400 {
compatible = "renesas,gpio-r8a77990",
"renesas,rcar-gen3-gpio";
reg = <0 0xe6055400 0 0x50>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 192 18>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 906>;
power-domains = <&sysc 32>;
resets = <&cpg 906>;
};
pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a77990";
reg = <0 0xe6060000 0 0x508>;
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a77990-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
clocks = <&extal_clk>;
clock-names = "extal";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};
rst: reset-controller@e6160000 {
compatible = "renesas,r8a77990-rst";
reg = <0 0xe6160000 0 0x0200>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a77990-sysc";
reg = <0 0xe6180000 0 0x0400>;
#power-domain-cells = <1>;
};
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a77990",
"renesas,etheravb-rcar-gen3";
reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15",
"ch16", "ch17", "ch18", "ch19",
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc 32>;
resets = <&cpg 812>;
phy-mode = "rgmii";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
scif2: serial@e6e88000 {
compatible = "renesas,scif-r8a77990",
"renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6e88000 0 64>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 310>;
clock-names = "fck";
power-domains = <&sysc 32>;
resets = <&cpg 310>;
status = "disabled";
};
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xf1010000 0 0x1000>,
<0x0 0xf1020000 0 0x20000>,
<0x0 0xf1040000 0 0x20000>,
<0x0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc 32>;
resets = <&cpg 408>;
};
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
};
arch/arm64/boot/dts/renesas/r8a77995-draak.dts
View file @ 171d429a
...@@ -91,7 +91,7 @@ &extal_clk { ...@@ -91,7 +91,7 @@ &extal_clk {
&pfc { &pfc {
avb0_pins: avb { avb0_pins: avb {
mux { mux {
groups = "avb0_link", "avb0_mdc", "avb0_mii"; groups = "avb0_link", "avb0_mdio", "avb0_mii";
function = "avb0"; function = "avb0";
}; };
}; };
......
arch/arm64/boot/dts/renesas/r8a77995.dtsi
View file @ 171d429a
...@@ -18,9 +18,11 @@ / { ...@@ -18,9 +18,11 @@ / {
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
psci { /* External CAN clock - to be overridden by boards that provide it */
compatible = "arm,psci-1.0", "arm,psci-0.2"; can_clk: can {
method = "smc"; compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
}; };
cpus { cpus {
...@@ -51,18 +53,16 @@ extal_clk: extal { ...@@ -51,18 +53,16 @@ extal_clk: extal {
clock-frequency = <0>; clock-frequency = <0>;
}; };
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
pmu_a53 { pmu_a53 {
compatible = "arm,cortex-a53-pmu"; compatible = "arm,cortex-a53-pmu";
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
}; };
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
scif_clk: scif { scif_clk: scif {
compatible = "fixed-clock"; compatible = "fixed-clock";
#clock-cells = <0>; #clock-cells = <0>;
...@@ -76,23 +76,6 @@ soc { ...@@ -76,23 +76,6 @@ soc {
#size-cells = <2>; #size-cells = <2>;
ranges; ranges;
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xf1010000 0 0x1000>,
<0x0 0xf1020000 0 0x20000>,
<0x0 0xf1040000 0 0x20000>,
<0x0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 408>;
};
rwdt: watchdog@e6020000 { rwdt: watchdog@e6020000 {
compatible = "renesas,r8a77995-wdt", compatible = "renesas,r8a77995-wdt",
"renesas,rcar-gen3-wdt"; "renesas,rcar-gen3-wdt";
...@@ -103,88 +86,123 @@ rwdt: watchdog@e6020000 { ...@@ -103,88 +86,123 @@ rwdt: watchdog@e6020000 {
status = "disabled"; status = "disabled";
}; };
ipmmu_vi0: mmu@febd0000 { gpio0: gpio@e6050000 {
compatible = "renesas,ipmmu-r8a77995"; compatible = "renesas,gpio-r8a77995",
reg = <0 0xfebd0000 0 0x1000>; "renesas,rcar-gen3-gpio",
renesas,ipmmu-main = <&ipmmu_mm 14>; "renesas,gpio-rcar";
#iommu-cells = <1>; reg = <0 0xe6050000 0 0x50>;
status = "disabled"; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
}; #gpio-cells = <2>;
gpio-controller;
ipmmu_vp0: mmu@fe990000 { gpio-ranges = <&pfc 0 0 9>;
compatible = "renesas,ipmmu-r8a77995"; #interrupt-cells = <2>;
reg = <0 0xfe990000 0 0x1000>; interrupt-controller;
renesas,ipmmu-main = <&ipmmu_mm 16>; clocks = <&cpg CPG_MOD 912>;
#iommu-cells = <1>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
status = "disabled"; resets = <&cpg 912>;
};
ipmmu_vc0: mmu@fe6b0000 {
compatible = "renesas,ipmmu-r8a77995";
reg = <0 0xfe6b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 12>;
#iommu-cells = <1>;
status = "disabled";
}; };
ipmmu_pv0: mmu@fd800000 { gpio1: gpio@e6051000 {
compatible = "renesas,ipmmu-r8a77995"; compatible = "renesas,gpio-r8a77995",
reg = <0 0xfd800000 0 0x1000>; "renesas,rcar-gen3-gpio",
renesas,ipmmu-main = <&ipmmu_mm 6>; "renesas,gpio-rcar";
#iommu-cells = <1>; reg = <0 0xe6051000 0 0x50>;
status = "disabled"; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 32 32>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 911>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 911>;
}; };
ipmmu_hc: mmu@e6570000 { gpio2: gpio@e6052000 {
compatible = "renesas,ipmmu-r8a77995"; compatible = "renesas,gpio-r8a77995",
reg = <0 0xe6570000 0 0x1000>; "renesas,rcar-gen3-gpio",
renesas,ipmmu-main = <&ipmmu_mm 2>; "renesas,gpio-rcar";
#iommu-cells = <1>; reg = <0 0xe6052000 0 0x50>;
status = "disabled"; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 64 32>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 910>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 910>;
}; };
ipmmu_rt: mmu@ffc80000 { gpio3: gpio@e6053000 {
compatible = "renesas,ipmmu-r8a77995"; compatible = "renesas,gpio-r8a77995",
reg = <0 0xffc80000 0 0x1000>; "renesas,rcar-gen3-gpio",
renesas,ipmmu-main = <&ipmmu_mm 10>; "renesas,gpio-rcar";
#iommu-cells = <1>; reg = <0 0xe6053000 0 0x50>;
status = "disabled"; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 96 10>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 909>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 909>;
}; };
ipmmu_mp: mmu@ec670000 { gpio4: gpio@e6054000 {
compatible = "renesas,ipmmu-r8a77995"; compatible = "renesas,gpio-r8a77995",
reg = <0 0xec670000 0 0x1000>; "renesas,rcar-gen3-gpio",
renesas,ipmmu-main = <&ipmmu_mm 4>; "renesas,gpio-rcar";
#iommu-cells = <1>; reg = <0 0xe6054000 0 0x50>;
status = "disabled"; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 128 32>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 908>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 908>;
}; };
ipmmu_ds0: mmu@e6740000 { gpio5: gpio@e6055000 {
compatible = "renesas,ipmmu-r8a77995"; compatible = "renesas,gpio-r8a77995",
reg = <0 0xe6740000 0 0x1000>; "renesas,rcar-gen3-gpio",
renesas,ipmmu-main = <&ipmmu_mm 0>; "renesas,gpio-rcar";
#iommu-cells = <1>; reg = <0 0xe6055000 0 0x50>;
status = "disabled"; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 160 21>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 907>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 907>;
}; };
ipmmu_ds1: mmu@e7740000 { gpio6: gpio@e6055400 {
compatible = "renesas,ipmmu-r8a77995"; compatible = "renesas,gpio-r8a77995",
reg = <0 0xe7740000 0 0x1000>; "renesas,rcar-gen3-gpio",
renesas,ipmmu-main = <&ipmmu_mm 1>; "renesas,gpio-rcar";
#iommu-cells = <1>; reg = <0 0xe6055400 0 0x50>;
status = "disabled"; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 192 14>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 906>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 906>;
}; };
ipmmu_mm: mmu@e67b0000 { pfc: pin-controller@e6060000 {
compatible = "renesas,ipmmu-r8a77995"; compatible = "renesas,pfc-r8a77995";
reg = <0 0xe67b0000 0 0x1000>; reg = <0 0xe6060000 0 0x508>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
status = "disabled";
}; };
cpg: clock-controller@e6150000 { cpg: clock-controller@e6150000 {
compatible = "renesas,r8a77995-cpg-mssr"; compatible = "renesas,r8a77995-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>; reg = <0 0xe6150000 0 0x1000>;
...@@ -200,16 +218,6 @@ rst: reset-controller@e6160000 { ...@@ -200,16 +218,6 @@ rst: reset-controller@e6160000 {
reg = <0 0xe6160000 0 0x0200>; reg = <0 0xe6160000 0 0x0200>;
}; };
pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a77995";
reg = <0 0xe6060000 0 0x508>;
};
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
};
sysc: system-controller@e6180000 { sysc: system-controller@e6180000 {
compatible = "renesas,r8a77995-sysc"; compatible = "renesas,r8a77995-sysc";
reg = <0 0xe6180000 0 0x0400>; reg = <0 0xe6180000 0 0x0400>;
...@@ -232,6 +240,98 @@ GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH ...@@ -232,6 +240,98 @@ GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
resets = <&cpg 407>; resets = <&cpg 407>;
}; };
i2c0: i2c@e6500000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a77995",
"renesas,rcar-gen3-i2c";
reg = <0 0xe6500000 0 0x40>;
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 931>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 931>;
dmas = <&dmac1 0x91>, <&dmac1 0x90>,
<&dmac2 0x91>, <&dmac2 0x90>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c1: i2c@e6508000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a77995",
"renesas,rcar-gen3-i2c";
reg = <0 0xe6508000 0 0x40>;
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 930>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 930>;
dmas = <&dmac1 0x93>, <&dmac1 0x92>,
<&dmac2 0x93>, <&dmac2 0x92>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c2: i2c@e6510000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a77995",
"renesas,rcar-gen3-i2c";
reg = <0 0xe6510000 0 0x40>;
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 929>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 929>;
dmas = <&dmac1 0x95>, <&dmac1 0x94>,
<&dmac2 0x95>, <&dmac2 0x94>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c3: i2c@e66d0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a77995",
"renesas,rcar-gen3-i2c";
reg = <0 0xe66d0000 0 0x40>;
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 928>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 928>;
dmas = <&dmac0 0x97>, <&dmac0 0x96>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
canfd: can@e66c0000 {
compatible = "renesas,r8a77995-canfd",
"renesas,rcar-gen3-canfd";
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A77995_CLK_CANFD>,
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";
channel0 {
status = "disabled";
};
channel1 {
status = "disabled";
};
};
dmac0: dma-controller@e6700000 { dmac0: dma-controller@e6700000 {
compatible = "renesas,dmac-r8a77995", compatible = "renesas,dmac-r8a77995",
"renesas,rcar-dmac"; "renesas,rcar-dmac";
...@@ -304,173 +404,75 @@ GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH ...@@ -304,173 +404,75 @@ GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
dma-channels = <8>; dma-channels = <8>;
}; };
gpio0: gpio@e6050000 { ipmmu_ds0: mmu@e6740000 {
compatible = "renesas,gpio-r8a77995", compatible = "renesas,ipmmu-r8a77995";
"renesas,rcar-gen3-gpio", reg = <0 0xe6740000 0 0x1000>;
"renesas,gpio-rcar"; renesas,ipmmu-main = <&ipmmu_mm 0>;
reg = <0 0xe6050000 0 0x50>; #iommu-cells = <1>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 0 9>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 912>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 912>;
};
gpio1: gpio@e6051000 {
compatible = "renesas,gpio-r8a77995",
"renesas,rcar-gen3-gpio",
"renesas,gpio-rcar";
reg = <0 0xe6051000 0 0x50>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 32 32>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 911>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 911>;
};
gpio2: gpio@e6052000 {
compatible = "renesas,gpio-r8a77995",
"renesas,rcar-gen3-gpio",
"renesas,gpio-rcar";
reg = <0 0xe6052000 0 0x50>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 64 32>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 910>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 910>;
};
gpio3: gpio@e6053000 {
compatible = "renesas,gpio-r8a77995",
"renesas,rcar-gen3-gpio",
"renesas,gpio-rcar";
reg = <0 0xe6053000 0 0x50>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 96 10>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 909>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 909>;
}; };
gpio4: gpio@e6054000 { ipmmu_ds1: mmu@e7740000 {
compatible = "renesas,gpio-r8a77995", compatible = "renesas,ipmmu-r8a77995";
"renesas,rcar-gen3-gpio", reg = <0 0xe7740000 0 0x1000>;
"renesas,gpio-rcar"; renesas,ipmmu-main = <&ipmmu_mm 1>;
reg = <0 0xe6054000 0 0x50>; #iommu-cells = <1>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 128 32>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 908>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 908>;
}; };
gpio5: gpio@e6055000 { ipmmu_hc: mmu@e6570000 {
compatible = "renesas,gpio-r8a77995", compatible = "renesas,ipmmu-r8a77995";
"renesas,rcar-gen3-gpio", reg = <0 0xe6570000 0 0x1000>;
"renesas,gpio-rcar"; renesas,ipmmu-main = <&ipmmu_mm 2>;
reg = <0 0xe6055000 0 0x50>; #iommu-cells = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 160 21>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 907>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 907>;
}; };
gpio6: gpio@e6055400 { ipmmu_mm: mmu@e67b0000 {
compatible = "renesas,gpio-r8a77995", compatible = "renesas,ipmmu-r8a77995";
"renesas,rcar-gen3-gpio", reg = <0 0xe67b0000 0 0x1000>;
"renesas,gpio-rcar"; interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
reg = <0 0xe6055400 0 0x50>; <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; #iommu-cells = <1>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 192 14>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 906>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 906>;
}; };
can0: can@e6c30000 { ipmmu_mp: mmu@ec670000 {
compatible = "renesas,can-r8a77995", compatible = "renesas,ipmmu-r8a77995";
"renesas,rcar-gen3-can"; reg = <0 0xec670000 0 0x1000>;
reg = <0 0xe6c30000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 4>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; #iommu-cells = <1>;
clocks = <&cpg CPG_MOD 916>,
<&cpg CPG_CORE R8A77995_CLK_CANFD>,
<&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 916>;
status = "disabled";
}; };
can1: can@e6c38000 { ipmmu_pv0: mmu@fd800000 {
compatible = "renesas,can-r8a77995", compatible = "renesas,ipmmu-r8a77995";
"renesas,rcar-gen3-can"; reg = <0 0xfd800000 0 0x1000>;
reg = <0 0xe6c38000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 6>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; #iommu-cells = <1>;
clocks = <&cpg CPG_MOD 915>,
<&cpg CPG_CORE R8A77995_CLK_CANFD>,
<&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 915>;
status = "disabled";
}; };
canfd: can@e66c0000 { ipmmu_rt: mmu@ffc80000 {
compatible = "renesas,r8a77995-canfd", compatible = "renesas,ipmmu-r8a77995";
"renesas,rcar-gen3-canfd"; reg = <0 0xffc80000 0 0x1000>;
reg = <0 0xe66c0000 0 0x8000>; renesas,ipmmu-main = <&ipmmu_mm 10>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, #iommu-cells = <1>;
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; };
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A77995_CLK_CANFD>,
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";
channel0 { ipmmu_vc0: mmu@fe6b0000 {
status = "disabled"; compatible = "renesas,ipmmu-r8a77995";
}; reg = <0 0xfe6b0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 12>;
#iommu-cells = <1>;
};
channel1 { ipmmu_vi0: mmu@febd0000 {
status = "disabled"; compatible = "renesas,ipmmu-r8a77995";
}; reg = <0 0xfebd0000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 14>;
#iommu-cells = <1>;
};
ipmmu_vp0: mmu@fe990000 {
compatible = "renesas,ipmmu-r8a77995";
reg = <0 0xfe990000 0 0x1000>;
renesas,ipmmu-main = <&ipmmu_mm 16>;
#iommu-cells = <1>;
}; };
avb: ethernet@e6800000 { avb: ethernet@e6800000 {
...@@ -519,87 +521,35 @@ avb: ethernet@e6800000 { ...@@ -519,87 +521,35 @@ avb: ethernet@e6800000 {
status = "disabled"; status = "disabled";
}; };
scif2: serial@e6e88000 { can0: can@e6c30000 {
compatible = "renesas,scif-r8a77995", compatible = "renesas,can-r8a77995",
"renesas,rcar-gen3-scif", "renesas,scif"; "renesas,rcar-gen3-can";
reg = <0 0xe6e88000 0 64>; reg = <0 0xe6c30000 0 0x1000>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 310>, clocks = <&cpg CPG_MOD 916>,
<&cpg CPG_CORE R8A77995_CLK_S3D1C>, <&cpg CPG_CORE R8A77995_CLK_CANFD>,
<&scif_clk>; <&can_clk>;
clock-names = "fck", "brg_int", "scif_clk"; clock-names = "clkp1", "clkp2", "can_clk";
dmas = <&dmac1 0x13>, <&dmac1 0x12>, assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
<&dmac2 0x13>, <&dmac2 0x12>; assigned-clock-rates = <40000000>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 310>;
status = "disabled";
};
i2c0: i2c@e6500000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a77995",
"renesas,rcar-gen3-i2c";
reg = <0 0xe6500000 0 0x40>;
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 931>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 931>;
dmas = <&dmac1 0x91>, <&dmac1 0x90>,
<&dmac2 0x91>, <&dmac2 0x90>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c1: i2c@e6508000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a77995",
"renesas,rcar-gen3-i2c";
reg = <0 0xe6508000 0 0x40>;
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 930>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 930>;
dmas = <&dmac1 0x93>, <&dmac1 0x92>,
<&dmac2 0x93>, <&dmac2 0x92>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c2: i2c@e6510000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a77995",
"renesas,rcar-gen3-i2c";
reg = <0 0xe6510000 0 0x40>;
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 929>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 929>; resets = <&cpg 916>;
dmas = <&dmac1 0x95>, <&dmac1 0x94>,
<&dmac2 0x95>, <&dmac2 0x94>;
dma-names = "tx", "rx", "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled"; status = "disabled";
}; };
i2c3: i2c@e66d0000 { can1: can@e6c38000 {
#address-cells = <1>; compatible = "renesas,can-r8a77995",
#size-cells = <0>; "renesas,rcar-gen3-can";
compatible = "renesas,i2c-r8a77995", reg = <0 0xe6c38000 0 0x1000>;
"renesas,rcar-gen3-i2c"; interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0xe66d0000 0 0x40>; clocks = <&cpg CPG_MOD 915>,
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; <&cpg CPG_CORE R8A77995_CLK_CANFD>,
clocks = <&cpg CPG_MOD 928>; <&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 928>; resets = <&cpg 915>;
dmas = <&dmac0 0x97>, <&dmac0 0x96>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <6>;
status = "disabled"; status = "disabled";
}; };
...@@ -643,38 +593,54 @@ pwm3: pwm@e6e33000 { ...@@ -643,38 +593,54 @@ pwm3: pwm@e6e33000 {
status = "disabled"; status = "disabled";
}; };
sdhi2: sd@ee140000 { scif2: serial@e6e88000 {
compatible = "renesas,sdhi-r8a77995", compatible = "renesas,scif-r8a77995",
"renesas,rcar-gen3-sdhi"; "renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xee140000 0 0x2000>; reg = <0 0xe6e88000 0 64>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>; clocks = <&cpg CPG_MOD 310>,
max-frequency = <200000000>; <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x13>, <&dmac1 0x12>,
<&dmac2 0x13>, <&dmac2 0x12>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 312>; resets = <&cpg 310>;
status = "disabled"; status = "disabled";
}; };
ehci0: usb@ee080100 { vin4: video@e6ef4000 {
compatible = "generic-ehci"; compatible = "renesas,vin-r8a77995";
reg = <0 0xee080100 0 0x100>; reg = <0 0xe6ef4000 0 0x1000>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 807>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 807>;
renesas,id = <4>;
status = "disabled";
};
ohci0: usb@ee080000 {
compatible = "generic-ohci";
reg = <0 0xee080000 0 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>; clocks = <&cpg CPG_MOD 703>;
phys = <&usb2_phy0>; phys = <&usb2_phy0>;
phy-names = "usb"; phy-names = "usb";
companion = <&ohci0>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 703>; resets = <&cpg 703>;
status = "disabled"; status = "disabled";
}; };
ohci0: usb@ee080000 { ehci0: usb@ee080100 {
compatible = "generic-ohci"; compatible = "generic-ehci";
reg = <0 0xee080000 0 0x100>; reg = <0 0xee080100 0 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>; clocks = <&cpg CPG_MOD 703>;
phys = <&usb2_phy0>; phys = <&usb2_phy0>;
phy-names = "usb"; phy-names = "usb";
companion = <&ohci0>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 703>; resets = <&cpg 703>;
status = "disabled"; status = "disabled";
...@@ -692,6 +658,35 @@ usb2_phy0: usb-phy@ee080200 { ...@@ -692,6 +658,35 @@ usb2_phy0: usb-phy@ee080200 {
status = "disabled"; status = "disabled";
}; };
sdhi2: sd@ee140000 {
compatible = "renesas,sdhi-r8a77995",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
max-frequency = <200000000>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 312>;
status = "disabled";
};
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xf1010000 0 0x1000>,
<0x0 0xf1020000 0 0x20000>,
<0x0 0xf1040000 0 0x20000>,
<0x0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 408>;
};
vspbs: vsp@fe960000 { vspbs: vsp@fe960000 {
compatible = "renesas,vsp2"; compatible = "renesas,vsp2";
reg = <0 0xfe960000 0 0x8000>; reg = <0 0xfe960000 0 0x8000>;
...@@ -702,15 +697,6 @@ vspbs: vsp@fe960000 { ...@@ -702,15 +697,6 @@ vspbs: vsp@fe960000 {
renesas,fcp = <&fcpvb0>; renesas,fcp = <&fcpvb0>;
}; };
fcpvb0: fcp@fe96f000 {
compatible = "renesas,fcpv";
reg = <0 0xfe96f000 0 0x200>;
clocks = <&cpg CPG_MOD 607>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 607>;
iommus = <&ipmmu_vp0 5>;
};
vspd0: vsp@fea20000 { vspd0: vsp@fea20000 {
compatible = "renesas,vsp2"; compatible = "renesas,vsp2";
reg = <0 0xfea20000 0 0x8000>; reg = <0 0xfea20000 0 0x8000>;
...@@ -721,15 +707,6 @@ vspd0: vsp@fea20000 { ...@@ -721,15 +707,6 @@ vspd0: vsp@fea20000 {
renesas,fcp = <&fcpvd0>; renesas,fcp = <&fcpvd0>;
}; };
fcpvd0: fcp@fea27000 {
compatible = "renesas,fcpv";
reg = <0 0xfea27000 0 0x200>;
clocks = <&cpg CPG_MOD 603>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 603>;
iommus = <&ipmmu_vi0 8>;
};
vspd1: vsp@fea28000 { vspd1: vsp@fea28000 {
compatible = "renesas,vsp2"; compatible = "renesas,vsp2";
reg = <0 0xfea28000 0 0x8000>; reg = <0 0xfea28000 0 0x8000>;
...@@ -740,6 +717,24 @@ vspd1: vsp@fea28000 { ...@@ -740,6 +717,24 @@ vspd1: vsp@fea28000 {
renesas,fcp = <&fcpvd1>; renesas,fcp = <&fcpvd1>;
}; };
fcpvb0: fcp@fe96f000 {
compatible = "renesas,fcpv";
reg = <0 0xfe96f000 0 0x200>;
clocks = <&cpg CPG_MOD 607>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 607>;
iommus = <&ipmmu_vp0 5>;
};
fcpvd0: fcp@fea27000 {
compatible = "renesas,fcpv";
reg = <0 0xfea27000 0 0x200>;
clocks = <&cpg CPG_MOD 603>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 603>;
iommus = <&ipmmu_vi0 8>;
};
fcpvd1: fcp@fea2f000 { fcpvd1: fcp@fea2f000 {
compatible = "renesas,fcpv"; compatible = "renesas,fcpv";
reg = <0 0xfea2f000 0 0x200>; reg = <0 0xfea2f000 0 0x200>;
...@@ -783,6 +778,11 @@ du_out_lvds1: endpoint { ...@@ -783,6 +778,11 @@ du_out_lvds1: endpoint {
}; };
}; };
}; };
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
};
}; };
timer { timer {
......
arch/arm64/boot/dts/renesas/salvator-common.dtsi
View file @ 171d429a
...@@ -66,6 +66,29 @@ backlight: backlight { ...@@ -66,6 +66,29 @@ backlight: backlight {
enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; enable-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
}; };
cvbs-in {
compatible = "composite-video-connector";
label = "CVBS IN";
port {
cvbs_con: endpoint {
remote-endpoint = <&adv7482_ain7>;
};
};
};
hdmi-in {
compatible = "hdmi-connector";
label = "HDMI IN";
type = "a";
port {
hdmi_in_con: endpoint {
remote-endpoint = <&adv7482_hdmi>;
};
};
};
reg_1p8v: regulator0 { reg_1p8v: regulator0 {
compatible = "regulator-fixed"; compatible = "regulator-fixed";
regulator-name = "fixed-1.8V"; regulator-name = "fixed-1.8V";
...@@ -93,20 +116,12 @@ reg_12v: regulator2 { ...@@ -93,20 +116,12 @@ reg_12v: regulator2 {
regulator-always-on; regulator-always-on;
}; };
rsnd_ak4613: sound { sound_card: sound {
compatible = "simple-audio-card"; compatible = "audio-graph-card";
simple-audio-card,format = "left_j";
simple-audio-card,bitclock-master = <&sndcpu>;
simple-audio-card,frame-master = <&sndcpu>;
sndcpu: simple-audio-card,cpu { label = "rcar-sound";
sound-dai = <&rcar_sound>;
};
sndcodec: simple-audio-card,codec { dais = <&rsnd_port0>;
sound-dai = <&ak4613>;
};
}; };
vbus0_usb2: regulator-vbus0-usb2 { vbus0_usb2: regulator-vbus0-usb2 {
...@@ -268,6 +283,37 @@ phy0: ethernet-phy@0 { ...@@ -268,6 +283,37 @@ phy0: ethernet-phy@0 {
}; };
}; };
&csi20 {
status = "okay";
ports {
port@0 {
reg = <0>;
csi20_in: endpoint {
clock-lanes = <0>;
data-lanes = <1>;
remote-endpoint = <&adv7482_txb>;
};
};
};
};
&csi40 {
status = "okay";
ports {
port@0 {
reg = <0>;
csi40_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&adv7482_txa>;
};
};
};
};
&du { &du {
pinctrl-0 = <&du_pins>; pinctrl-0 = <&du_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
...@@ -322,6 +368,12 @@ ak4613: codec@10 { ...@@ -322,6 +368,12 @@ ak4613: codec@10 {
asahi-kasei,out4-single-end; asahi-kasei,out4-single-end;
asahi-kasei,out5-single-end; asahi-kasei,out5-single-end;
asahi-kasei,out6-single-end; asahi-kasei,out6-single-end;
port {
ak4613_endpoint: endpoint {
remote-endpoint = <&rsnd_endpoint0>;
};
};
}; };
cs2000: clk_multiplier@4f { cs2000: clk_multiplier@4f {
...@@ -359,6 +411,55 @@ csa_dvfs: adc@7f { ...@@ -359,6 +411,55 @@ csa_dvfs: adc@7f {
shunt-resistor-micro-ohms = <5000>; shunt-resistor-micro-ohms = <5000>;
}; };
video-receiver@70 {
compatible = "adi,adv7482";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&gpio6>;
interrupt-names = "intrq1", "intrq2";
interrupts = <30 IRQ_TYPE_LEVEL_LOW>,
<31 IRQ_TYPE_LEVEL_LOW>;
port@7 {
reg = <7>;
adv7482_ain7: endpoint {
remote-endpoint = <&cvbs_con>;
};
};
port@8 {
reg = <8>;
adv7482_hdmi: endpoint {
remote-endpoint = <&hdmi_in_con>;
};
};
port@10 {
reg = <10>;
adv7482_txa: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csi40_in>;
};
};
port@11 {
reg = <11>;
adv7482_txb: endpoint {
clock-lanes = <0>;
data-lanes = <1>;
remote-endpoint = <&csi20_in>;
};
};
};
}; };
&i2c_dvfs { &i2c_dvfs {
...@@ -376,6 +477,8 @@ pmic: pmic@30 { ...@@ -376,6 +477,8 @@ pmic: pmic@30 {
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
rohm,ddr-backup-power = <0xf>;
rohm,rstbmode-level;
regulators { regulators {
dvfs: dvfs { dvfs: dvfs {
...@@ -387,6 +490,12 @@ dvfs: dvfs { ...@@ -387,6 +490,12 @@ dvfs: dvfs {
}; };
}; };
}; };
eeprom@50 {
compatible = "rohm,br24t01", "atmel,24c01";
reg = <0x50>;
pagesize = <8>;
};
}; };
&ohci0 { &ohci0 {
...@@ -416,12 +525,12 @@ &pfc { ...@@ -416,12 +525,12 @@ &pfc {
avb_pins: avb { avb_pins: avb {
mux { mux {
groups = "avb_link", "avb_mdc", "avb_mii"; groups = "avb_link", "avb_mdio", "avb_mii";
function = "avb"; function = "avb";
}; };
pins_mdc { pins_mdio {
groups = "avb_mdc"; groups = "avb_mdio";
drive-strength = <24>; drive-strength = <24>;
}; };
...@@ -581,10 +690,18 @@ &rcar_sound { ...@@ -581,10 +690,18 @@ &rcar_sound {
<&audio_clk_c>, <&audio_clk_c>,
<&cpg CPG_CORE CPG_AUDIO_CLK_I>; <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
rcar_sound,dai { ports {
dai0 { rsnd_port0: port@0 {
playback = <&ssi0 &src0 &dvc0>; rsnd_endpoint0: endpoint {
capture = <&ssi1 &src1 &dvc1>; remote-endpoint = <&ak4613_endpoint>;
dai-format = "left_j";
bitclock-master = <&rsnd_endpoint0>;
frame-master = <&rsnd_endpoint0>;
playback = <&ssi0 &src0 &dvc0>;
capture = <&ssi1 &src1 &dvc1>;
};
}; };
}; };
}; };
...@@ -689,6 +806,38 @@ &usb3s0_clk { ...@@ -689,6 +806,38 @@ &usb3s0_clk {
clock-frequency = <100000000>; clock-frequency = <100000000>;
}; };
&vin0 {
status = "okay";
};
&vin1 {
status = "okay";
};
&vin2 {
status = "okay";
};
&vin3 {
status = "okay";
};
&vin4 {
status = "okay";
};
&vin5 {
status = "okay";
};
&vin6 {
status = "okay";
};
&vin7 {
status = "okay";
};
&wdt0 { &wdt0 {
timeout-sec = <60>; timeout-sec = <60>;
status = "okay"; status = "okay";
......
arch/arm64/boot/dts/renesas/ulcb.dtsi
View file @ 171d429a
...@@ -243,6 +243,32 @@ versaclock5: clock-generator@6a { ...@@ -243,6 +243,32 @@ versaclock5: clock-generator@6a {
&i2c_dvfs { &i2c_dvfs {
status = "okay"; status = "okay";
pmic: pmic@30 {
pinctrl-0 = <&irq0_pins>;
pinctrl-names = "default";
compatible = "rohm,bd9571mwv";
reg = <0x30>;
interrupt-parent = <&intc_ex>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
rohm,ddr-backup-power = <0xf>;
rohm,rstbmode-pulse;
regulators {
dvfs: dvfs {
regulator-name = "dvfs";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1030000>;
regulator-boot-on;
regulator-always-on;
};
};
};
}; };
&ohci1 { &ohci1 {
...@@ -255,12 +281,12 @@ &pfc { ...@@ -255,12 +281,12 @@ &pfc {
avb_pins: avb { avb_pins: avb {
mux { mux {
groups = "avb_link", "avb_mdc", "avb_mii"; groups = "avb_link", "avb_mdio", "avb_mii";
function = "avb"; function = "avb";
}; };
pins_mdc { pins_mdio {
groups = "avb_mdc"; groups = "avb_mdio";
drive-strength = <24>; drive-strength = <24>;
}; };
...@@ -276,6 +302,11 @@ i2c2_pins: i2c2 { ...@@ -276,6 +302,11 @@ i2c2_pins: i2c2 {
function = "i2c2"; function = "i2c2";
}; };
irq0_pins: irq0 {
groups = "intc_ex_irq0";
function = "intc_ex";
};
scif2_pins: scif2 { scif2_pins: scif2 {
groups = "scif2_data_a"; groups = "scif2_data_a";
function = "scif2"; function = "scif2";
......
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