Commit 179e5a61 authored by Andy Shevchenko's avatar Andy Shevchenko

pinctrl: intel: Remove default Interrupt Status offset

Since some of the GPIO controllers use different Interrupt Status offset,
it make sense to provide it explicitly in the drivers.
Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
parent 3b1e9188
...@@ -29,7 +29,6 @@ ...@@ -29,7 +29,6 @@
#define REVID_MASK GENMASK(31, 16) #define REVID_MASK GENMASK(31, 16)
#define PADBAR 0x00c #define PADBAR 0x00c
#define GPI_IS 0x100
#define PADOWN_BITS 4 #define PADOWN_BITS 4
#define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS) #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
...@@ -1342,9 +1341,6 @@ static int intel_pinctrl_probe(struct platform_device *pdev, ...@@ -1342,9 +1341,6 @@ static int intel_pinctrl_probe(struct platform_device *pdev,
community->regs = regs; community->regs = regs;
community->pad_regs = regs + padbar; community->pad_regs = regs + padbar;
if (!community->is_offset)
community->is_offset = GPI_IS;
ret = intel_pinctrl_add_padgroups(pctrl, community); ret = intel_pinctrl_add_padgroups(pctrl, community);
if (ret) if (ret)
return ret; return ret;
......
...@@ -75,8 +75,7 @@ struct intel_padgroup { ...@@ -75,8 +75,7 @@ struct intel_padgroup {
* @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it
* is assumed that the host owns the pin (rather than * is assumed that the host owns the pin (rather than
* ACPI). * ACPI).
* @is_offset: Register offset of GPI_IS from @regs. If %0 then uses the * @is_offset: Register offset of GPI_IS from @regs.
* default (%0x100).
* @ie_offset: Register offset of GPI_IE from @regs. * @ie_offset: Register offset of GPI_IE from @regs.
* @pin_base: Starting pin of pins in this community * @pin_base: Starting pin of pins in this community
* @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK, * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
......
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