Commit 17a60345 authored by Fengguang Wu's avatar Fengguang Wu Committed by Ingo Molnar

perf/x86/uncore: Fix coccinelle warnings

  arch/x86/kernel/cpu/perf_event_intel_uncore_nhmex.c:961:2-3: Unneeded semicolon
  arch/x86/kernel/cpu/perf_event_intel_uncore_nhmex.c:1100:2-3: Unneeded semicolon
  arch/x86/kernel/cpu/perf_event_intel_uncore_nhmex.c:1138:2-3: Unneeded semicolon

Remove unneeded semicolon.

Generated by: scripts/coccinelle/misc/semicolon.cocci
Signed-off-by: default avatarFengguang Wu <fengguang.wu@intel.com>
Signed-off-by: default avatarPeter Zijlstra <peterz@infradead.org>
Cc: Yan, Zheng <zheng.z.yan@intel.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Link: http://lkml.kernel.org/n/tip-ovfvr4nbqjo7nzc16y2lpjy9@git.kernel.orgSigned-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent c1e46580
...@@ -958,7 +958,7 @@ static void nhmex_rbox_alter_er(struct intel_uncore_box *box, struct perf_event ...@@ -958,7 +958,7 @@ static void nhmex_rbox_alter_er(struct intel_uncore_box *box, struct perf_event
/* shift the 0~7 bits to the 8~15 bits */ /* shift the 0~7 bits to the 8~15 bits */
reg1->config <<= 8; reg1->config <<= 8;
break; break;
}; }
} }
/* /*
...@@ -1097,7 +1097,7 @@ static int nhmex_rbox_hw_config(struct intel_uncore_box *box, struct perf_event ...@@ -1097,7 +1097,7 @@ static int nhmex_rbox_hw_config(struct intel_uncore_box *box, struct perf_event
hwc->config |= event->attr.config & (~0ULL << 32); hwc->config |= event->attr.config & (~0ULL << 32);
reg2->config = event->attr.config2; reg2->config = event->attr.config2;
break; break;
}; }
return 0; return 0;
} }
...@@ -1135,7 +1135,7 @@ static void nhmex_rbox_msr_enable_event(struct intel_uncore_box *box, struct per ...@@ -1135,7 +1135,7 @@ static void nhmex_rbox_msr_enable_event(struct intel_uncore_box *box, struct per
wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MATCH(port), reg1->config); wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MATCH(port), reg1->config);
wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MASK(port), reg2->config); wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MASK(port), reg2->config);
break; break;
}; }
wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 | wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 |
(hwc->config & NHMEX_R_PMON_CTL_EV_SEL_MASK)); (hwc->config & NHMEX_R_PMON_CTL_EV_SEL_MASK));
......
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