Commit 18b94f66 authored by Aravind Gopalakrishnan's avatar Aravind Gopalakrishnan Committed by Borislav Petkov

amd64_edac: Add ECC decoding support for newer F15h models

On newer models, support has been included for upto 4 DCT's, however,
only DCT0 and DCT3 are currently configured (cf BKDG Section 2.10).
Also, the routing DRAM Requests algorithm is different for F15h M30h.
Thus it is cleaner to use a brand new function rather than adding quirks
to the more generic f1x_match_to_this_node(). Refer to "2.10.5 DRAM
Routing Requests" in the BKDG for further info.

Tested on Fam15h M30h with ECC turned on using mce_amd_inj facility and
verified to be functionally correct.

While at it, verify if erratum workarounds for E505 and E637 still hold.
From email conversations within AMD, the current status of the errata
is:

      * Erratum 505: fixed in model 0x1, stepping 0x1 and later.
      * Erratum 637: not fixed.
Signed-off-by: default avatarAravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
[ Cleanups, corrections ]
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
parent 7d64ac64
This diff is collapsed.
...@@ -170,6 +170,8 @@ ...@@ -170,6 +170,8 @@
/* /*
* PCI-defined configuration space registers * PCI-defined configuration space registers
*/ */
#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b
#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c
#define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601 #define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601
#define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602 #define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602
#define PCI_DEVICE_ID_AMD_16H_NB_F1 0x1531 #define PCI_DEVICE_ID_AMD_16H_NB_F1 0x1531
...@@ -181,13 +183,22 @@ ...@@ -181,13 +183,22 @@
#define DRAM_BASE_LO 0x40 #define DRAM_BASE_LO 0x40
#define DRAM_LIMIT_LO 0x44 #define DRAM_LIMIT_LO 0x44
#define dram_intlv_en(pvt, i) ((u8)((pvt->ranges[i].base.lo >> 8) & 0x7)) /*
* F15 M30h D18F1x2[1C:00]
*/
#define DRAM_CONT_BASE 0x200
#define DRAM_CONT_LIMIT 0x204
/*
* F15 M30h D18F1x2[4C:40]
*/
#define DRAM_CONT_HIGH_OFF 0x240
#define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3)) #define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3))
#define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7)) #define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
#define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7)) #define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7))
#define DHAR 0xf0 #define DHAR 0xf0
#define dhar_valid(pvt) ((pvt)->dhar & BIT(0))
#define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1)) #define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1))
#define dhar_base(pvt) ((pvt)->dhar & 0xff000000) #define dhar_base(pvt) ((pvt)->dhar & 0xff000000)
#define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16) #define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16)
...@@ -234,8 +245,6 @@ ...@@ -234,8 +245,6 @@
#define DDR3_MODE BIT(8) #define DDR3_MODE BIT(8)
#define DCT_SEL_LO 0x110 #define DCT_SEL_LO 0x110
#define dct_sel_baseaddr(pvt) ((pvt)->dct_sel_lo & 0xFFFFF800)
#define dct_sel_interleave_addr(pvt) (((pvt)->dct_sel_lo >> 6) & 0x3)
#define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0)) #define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0))
#define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2)) #define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2))
...@@ -297,6 +306,7 @@ enum amd_families { ...@@ -297,6 +306,7 @@ enum amd_families {
K8_CPUS = 0, K8_CPUS = 0,
F10_CPUS, F10_CPUS,
F15_CPUS, F15_CPUS,
F15_M30H_CPUS,
F16_CPUS, F16_CPUS,
NUM_FAMILIES, NUM_FAMILIES,
}; };
...@@ -337,6 +347,8 @@ struct amd64_pvt { ...@@ -337,6 +347,8 @@ struct amd64_pvt {
struct pci_dev *F1, *F2, *F3; struct pci_dev *F1, *F2, *F3;
u16 mc_node_id; /* MC index of this MC node */ u16 mc_node_id; /* MC index of this MC node */
u8 fam; /* CPU family */
u8 model; /* CPU model */
int ext_model; /* extended model value of this node */ int ext_model; /* extended model value of this node */
int channel_count; int channel_count;
...@@ -414,6 +426,14 @@ static inline u16 extract_syndrome(u64 status) ...@@ -414,6 +426,14 @@ static inline u16 extract_syndrome(u64 status)
return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00); return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00);
} }
static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt)
{
if (pvt->fam == 0x15 && pvt->model >= 0x30)
return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) |
((pvt->dct_sel_lo >> 6) & 0x3);
return ((pvt)->dct_sel_lo >> 6) & 0x3;
}
/* /*
* per-node ECC settings descriptor * per-node ECC settings descriptor
*/ */
...@@ -504,3 +524,33 @@ static inline void enable_caches(void *dummy) ...@@ -504,3 +524,33 @@ static inline void enable_caches(void *dummy)
{ {
write_cr0(read_cr0() & ~X86_CR0_CD); write_cr0(read_cr0() & ~X86_CR0_CD);
} }
static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i)
{
if (pvt->fam == 0x15 && pvt->model >= 0x30) {
u32 tmp;
amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp);
return (u8) tmp & 0xF;
}
return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7;
}
static inline u8 dhar_valid(struct amd64_pvt *pvt)
{
if (pvt->fam == 0x15 && pvt->model >= 0x30) {
u32 tmp;
amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
return (tmp >> 1) & BIT(0);
}
return (pvt)->dhar & BIT(0);
}
static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt)
{
if (pvt->fam == 0x15 && pvt->model >= 0x30) {
u32 tmp;
amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
return (tmp >> 11) & 0x1FFF;
}
return (pvt)->dct_sel_lo & 0xFFFFF800;
}
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