Commit 18fee453 authored by Pankaj Dev's avatar Pankaj Dev Committed by Stephen Boyd

drivers: clk: st: Add CLK_GET_RATE_NOCACHE flag to clocks

Add the CLK_GET_RATE_NOCACHE flag to all the clocks with recalc ops,
so that they reflect Hw rate after CPS wake-up when a clk_get_rate()
is called
Signed-off-by: default avatarPankaj Dev <pankaj.dev@st.com>
Signed-off-by: default avatarGabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 0f4f2afd
...@@ -190,7 +190,7 @@ static struct clk *clk_register_flexgen(const char *name, ...@@ -190,7 +190,7 @@ static struct clk *clk_register_flexgen(const char *name,
init.name = name; init.name = name;
init.ops = &flexgen_ops; init.ops = &flexgen_ops;
init.flags = CLK_IS_BASIC | flexgen_flags; init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE | flexgen_flags;
init.parent_names = parent_names; init.parent_names = parent_names;
init.num_parents = num_parents; init.num_parents = num_parents;
......
...@@ -635,7 +635,7 @@ static struct clk * __init st_clk_register_quadfs_pll( ...@@ -635,7 +635,7 @@ static struct clk * __init st_clk_register_quadfs_pll(
init.name = name; init.name = name;
init.ops = quadfs->pll_ops; init.ops = quadfs->pll_ops;
init.flags = CLK_IS_BASIC; init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE;
init.parent_names = &parent_name; init.parent_names = &parent_name;
init.num_parents = 1; init.num_parents = 1;
......
...@@ -237,7 +237,7 @@ static struct clk *clk_register_genamux(const char *name, ...@@ -237,7 +237,7 @@ static struct clk *clk_register_genamux(const char *name,
init.name = name; init.name = name;
init.ops = &clkgena_divmux_ops; init.ops = &clkgena_divmux_ops;
init.flags = CLK_IS_BASIC; init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE;
init.parent_names = parent_names; init.parent_names = parent_names;
init.num_parents = num_parents; init.num_parents = num_parents;
...@@ -513,7 +513,8 @@ static void __init st_of_clkgena_prediv_setup(struct device_node *np) ...@@ -513,7 +513,8 @@ static void __init st_of_clkgena_prediv_setup(struct device_node *np)
0, &clk_name)) 0, &clk_name))
return; return;
clk = clk_register_divider_table(NULL, clk_name, parent_name, 0, clk = clk_register_divider_table(NULL, clk_name, parent_name,
CLK_GET_RATE_NOCACHE,
reg + data->offset, data->shift, 1, reg + data->offset, data->shift, 1,
0, data->table, NULL); 0, data->table, NULL);
if (IS_ERR(clk)) if (IS_ERR(clk))
...@@ -786,7 +787,8 @@ static void __init st_of_clkgen_vcc_setup(struct device_node *np) ...@@ -786,7 +787,8 @@ static void __init st_of_clkgen_vcc_setup(struct device_node *np)
&mux->hw, &clk_mux_ops, &mux->hw, &clk_mux_ops,
&div->hw, &clk_divider_ops, &div->hw, &clk_divider_ops,
&gate->hw, &clk_gate_ops, &gate->hw, &clk_gate_ops,
data->clk_flags); data->clk_flags |
CLK_GET_RATE_NOCACHE);
if (IS_ERR(clk)) { if (IS_ERR(clk)) {
kfree(gate); kfree(gate);
kfree(div); kfree(div);
......
...@@ -406,7 +406,7 @@ static struct clk * __init clkgen_pll_register(const char *parent_name, ...@@ -406,7 +406,7 @@ static struct clk * __init clkgen_pll_register(const char *parent_name,
init.name = clk_name; init.name = clk_name;
init.ops = pll_data->ops; init.ops = pll_data->ops;
init.flags = CLK_IS_BASIC; init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE;
init.parent_names = &parent_name; init.parent_names = &parent_name;
init.num_parents = 1; init.num_parents = 1;
......
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