Commit 1922c356 authored by Markos Chandras's avatar Markos Chandras

MIPS: asm: futex: Set the appropriate ISA level for MIPS R6

MIPS R6 changed the opcodes for LL/SC instructions so we need to set
the appropriate ISA level.

Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
parent 87a927ef
...@@ -53,11 +53,11 @@ ...@@ -53,11 +53,11 @@
__asm__ __volatile__( \ __asm__ __volatile__( \
" .set push \n" \ " .set push \n" \
" .set noat \n" \ " .set noat \n" \
" .set arch=r4000 \n" \ " .set "MIPS_ISA_ARCH_LEVEL" \n" \
"1: "user_ll("%1", "%4")" # __futex_atomic_op\n" \ "1: "user_ll("%1", "%4")" # __futex_atomic_op\n" \
" .set mips0 \n" \ " .set mips0 \n" \
" " insn " \n" \ " " insn " \n" \
" .set arch=r4000 \n" \ " .set "MIPS_ISA_ARCH_LEVEL" \n" \
"2: "user_sc("$1", "%2")" \n" \ "2: "user_sc("$1", "%2")" \n" \
" beqz $1, 1b \n" \ " beqz $1, 1b \n" \
__WEAK_LLSC_MB \ __WEAK_LLSC_MB \
...@@ -183,12 +183,12 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, ...@@ -183,12 +183,12 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
"# futex_atomic_cmpxchg_inatomic \n" "# futex_atomic_cmpxchg_inatomic \n"
" .set push \n" " .set push \n"
" .set noat \n" " .set noat \n"
" .set arch=r4000 \n" " .set "MIPS_ISA_ARCH_LEVEL" \n"
"1: "user_ll("%1", "%3")" \n" "1: "user_ll("%1", "%3")" \n"
" bne %1, %z4, 3f \n" " bne %1, %z4, 3f \n"
" .set mips0 \n" " .set mips0 \n"
" move $1, %z5 \n" " move $1, %z5 \n"
" .set arch=r4000 \n" " .set "MIPS_ISA_ARCH_LEVEL" \n"
"2: "user_sc("$1", "%2")" \n" "2: "user_sc("$1", "%2")" \n"
" beqz $1, 1b \n" " beqz $1, 1b \n"
__WEAK_LLSC_MB __WEAK_LLSC_MB
......
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