Commit 1955f107 authored by Alex Deucher's avatar Alex Deucher

drm/radeon: rework CI dpm thermal setup

In preparation for fan control.
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2271e2e2
...@@ -814,7 +814,7 @@ static void ci_apply_state_adjust_rules(struct radeon_device *rdev, ...@@ -814,7 +814,7 @@ static void ci_apply_state_adjust_rules(struct radeon_device *rdev,
} }
} }
static int ci_set_thermal_temperature_range(struct radeon_device *rdev, static int ci_thermal_set_temperature_range(struct radeon_device *rdev,
int min_temp, int max_temp) int min_temp, int max_temp)
{ {
int low_temp = 0 * 1000; int low_temp = 0 * 1000;
...@@ -850,6 +850,35 @@ static int ci_set_thermal_temperature_range(struct radeon_device *rdev, ...@@ -850,6 +850,35 @@ static int ci_set_thermal_temperature_range(struct radeon_device *rdev,
return 0; return 0;
} }
static int ci_thermal_enable_alert(struct radeon_device *rdev,
bool enable)
{
u32 thermal_int = RREG32_SMC(CG_THERMAL_INT);
PPSMC_Result result;
if (enable) {
thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
rdev->irq.dpm_thermal = false;
result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Enable);
if (result != PPSMC_Result_OK) {
DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
return -EINVAL;
}
} else {
thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
rdev->irq.dpm_thermal = true;
result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Disable);
if (result != PPSMC_Result_OK) {
DRM_DEBUG_KMS("Could not disable thermal interrupts.\n");
return -EINVAL;
}
}
WREG32_SMC(CG_THERMAL_INT, thermal_int);
return 0;
}
#if 0 #if 0
static int ci_read_smc_soft_register(struct radeon_device *rdev, static int ci_read_smc_soft_register(struct radeon_device *rdev,
u16 reg_offset, u32 *value) u16 reg_offset, u32 *value)
...@@ -4682,29 +4711,30 @@ int ci_dpm_enable(struct radeon_device *rdev) ...@@ -4682,29 +4711,30 @@ int ci_dpm_enable(struct radeon_device *rdev)
return 0; return 0;
} }
int ci_dpm_late_enable(struct radeon_device *rdev) static int ci_set_temperature_range(struct radeon_device *rdev)
{ {
int ret; int ret;
if (rdev->irq.installed && ret = ci_thermal_enable_alert(rdev, false);
r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { if (ret)
#if 0 return ret;
PPSMC_Result result; ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
#endif if (ret)
ret = ci_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); return ret;
if (ret) { ret = ci_thermal_enable_alert(rdev, true);
DRM_ERROR("ci_set_thermal_temperature_range failed\n"); if (ret)
return ret; return ret;
}
rdev->irq.dpm_thermal = true;
radeon_irq_set(rdev);
#if 0
result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
if (result != PPSMC_Result_OK) return ret;
DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); }
#endif
} int ci_dpm_late_enable(struct radeon_device *rdev)
{
int ret;
ret = ci_set_temperature_range(rdev);
if (ret)
return ret;
ci_dpm_powergate_uvd(rdev, true); ci_dpm_powergate_uvd(rdev, true);
......
...@@ -106,6 +106,7 @@ typedef uint8_t PPSMC_Result; ...@@ -106,6 +106,7 @@ typedef uint8_t PPSMC_Result;
#define PPSMC_MSG_SAMUDPM_SetEnabledMask ((uint16_t) 0x130) #define PPSMC_MSG_SAMUDPM_SetEnabledMask ((uint16_t) 0x130)
#define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131) #define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131)
#define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132) #define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132)
#define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0x133)
#define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135) #define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135)
#define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136) #define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136)
#define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d) #define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d)
...@@ -157,10 +158,11 @@ typedef uint8_t PPSMC_Result; ...@@ -157,10 +158,11 @@ typedef uint8_t PPSMC_Result;
#define PPSMC_MSG_DPM_Config ((uint32_t) 0x102) #define PPSMC_MSG_DPM_Config ((uint32_t) 0x102)
#define PPSMC_MSG_DPM_ForceState ((uint32_t) 0x104) #define PPSMC_MSG_DPM_ForceState ((uint32_t) 0x104)
#define PPSMC_MSG_PG_SIMD_Config ((uint32_t) 0x108) #define PPSMC_MSG_PG_SIMD_Config ((uint32_t) 0x108)
#define PPSMC_MSG_DPM_N_LevelsDisabled ((uint32_t) 0x112) #define PPSMC_MSG_Thermal_Cntl_Enable ((uint32_t) 0x10a)
#define PPSMC_MSG_Voltage_Cntl_Enable ((uint32_t) 0x109) #define PPSMC_MSG_Voltage_Cntl_Enable ((uint32_t) 0x109)
#define PPSMC_MSG_VCEPowerOFF ((uint32_t) 0x10e) #define PPSMC_MSG_VCEPowerOFF ((uint32_t) 0x10e)
#define PPSMC_MSG_VCEPowerON ((uint32_t) 0x10f) #define PPSMC_MSG_VCEPowerON ((uint32_t) 0x10f)
#define PPSMC_MSG_DPM_N_LevelsDisabled ((uint32_t) 0x112)
#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint32_t) 0x11d) #define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint32_t) 0x11d)
#define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint32_t) 0x11e) #define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint32_t) 0x11e)
#define PPSMC_MSG_EnableBAPM ((uint32_t) 0x120) #define PPSMC_MSG_EnableBAPM ((uint32_t) 0x120)
......
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