Commit 1a70db4b authored by Emil Tantilov's avatar Emil Tantilov Committed by Jeff Kirsher

ixgbe: cleanup some register reads

Remove duplicate inc of hwstats->ruc
Introduce separate loops for 8 and 16 register reads.
Consolidate mac checks under one case.
Make sure registers are cleared on read.
Reported-by: default avatarJonathan Lynch <jonathan.lynch@thenowfactory.com>
Signed-off-by: default avatarEmil Tantilov <emil.s.tantilov@intel.com>
CC: Jonathan Lynch <jonathan.lynch@thenowfactory.com>
Tested-by: default avatarPhil Schmitt <phillip.j.schmitt@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 919e78a6
...@@ -5463,20 +5463,21 @@ void ixgbe_update_stats(struct ixgbe_adapter *adapter) ...@@ -5463,20 +5463,21 @@ void ixgbe_update_stats(struct ixgbe_adapter *adapter)
netdev->stats.tx_packets = packets; netdev->stats.tx_packets = packets;
hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
/* 8 register reads */
for (i = 0; i < 8; i++) { for (i = 0; i < 8; i++) {
/* for packet buffers not used, the register should read 0 */ /* for packet buffers not used, the register should read 0 */
mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
missed_rx += mpc; missed_rx += mpc;
hwstats->mpc[i] += mpc; hwstats->mpc[i] += mpc;
total_mpc += hwstats->mpc[i]; total_mpc += hwstats->mpc[i];
if (hw->mac.type == ixgbe_mac_82598EB) hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
switch (hw->mac.type) { switch (hw->mac.type) {
case ixgbe_mac_82598EB: case ixgbe_mac_82598EB:
hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
hwstats->pxonrxc[i] += hwstats->pxonrxc[i] +=
IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
break; break;
...@@ -5488,9 +5489,21 @@ void ixgbe_update_stats(struct ixgbe_adapter *adapter) ...@@ -5488,9 +5489,21 @@ void ixgbe_update_stats(struct ixgbe_adapter *adapter)
default: default:
break; break;
} }
hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
} }
/*16 register reads */
for (i = 0; i < 16; i++) {
hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
if ((hw->mac.type == ixgbe_mac_82599EB) ||
(hw->mac.type == ixgbe_mac_X540)) {
hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
}
}
hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
/* work around hardware counting issue */ /* work around hardware counting issue */
hwstats->gprc -= missed_rx; hwstats->gprc -= missed_rx;
...@@ -5550,7 +5563,6 @@ void ixgbe_update_stats(struct ixgbe_adapter *adapter) ...@@ -5550,7 +5563,6 @@ void ixgbe_update_stats(struct ixgbe_adapter *adapter)
hwstats->lxontxc += lxon; hwstats->lxontxc += lxon;
lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
hwstats->lxofftxc += lxoff; hwstats->lxofftxc += lxoff;
hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
/* /*
......
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