Commit 1b45adcd authored by Peter Zijlstra's avatar Peter Zijlstra Committed by Ingo Molnar

perf/x86/amd: Rework AMD PMU init code

Josh reported that his QEMU is a bad hardware emulator and trips a
WARN in the AMD PMU init code. He requested the WARN be turned into a
pr_err() or similar.

While there, rework the code a little.
Reported-by: default avatarJosh Boyer <jwboyer@redhat.com>
Acked-by: default avatarRobert Richter <rric@kernel.org>
Acked-by: default avatarJacob Shin <jacob.shin@amd.com>
Cc: Stephane Eranian <eranian@google.com>
Signed-off-by: default avatarPeter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/20130521110537.GG26912@twins.programming.kicks-ass.netSigned-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 2b923c8f
...@@ -648,48 +648,48 @@ static __initconst const struct x86_pmu amd_pmu = { ...@@ -648,48 +648,48 @@ static __initconst const struct x86_pmu amd_pmu = {
.cpu_dead = amd_pmu_cpu_dead, .cpu_dead = amd_pmu_cpu_dead,
}; };
static int setup_event_constraints(void) static int __init amd_core_pmu_init(void)
{ {
if (boot_cpu_data.x86 == 0x15) if (!cpu_has_perfctr_core)
return 0;
switch (boot_cpu_data.x86) {
case 0x15:
pr_cont("Fam15h ");
x86_pmu.get_event_constraints = amd_get_event_constraints_f15h; x86_pmu.get_event_constraints = amd_get_event_constraints_f15h;
return 0; break;
}
static int setup_perfctr_core(void) default:
{ pr_err("core perfctr but no constraints; unknown hardware!\n");
if (!cpu_has_perfctr_core) {
WARN(x86_pmu.get_event_constraints == amd_get_event_constraints_f15h,
KERN_ERR "Odd, counter constraints enabled but no core perfctrs detected!");
return -ENODEV; return -ENODEV;
} }
WARN(x86_pmu.get_event_constraints == amd_get_event_constraints,
KERN_ERR "hw perf events core counters need constraints handler!");
/* /*
* If core performance counter extensions exists, we must use * If core performance counter extensions exists, we must use
* MSR_F15H_PERF_CTL/MSR_F15H_PERF_CTR msrs. See also * MSR_F15H_PERF_CTL/MSR_F15H_PERF_CTR msrs. See also
* x86_pmu_addr_offset(). * amd_pmu_addr_offset().
*/ */
x86_pmu.eventsel = MSR_F15H_PERF_CTL; x86_pmu.eventsel = MSR_F15H_PERF_CTL;
x86_pmu.perfctr = MSR_F15H_PERF_CTR; x86_pmu.perfctr = MSR_F15H_PERF_CTR;
x86_pmu.num_counters = AMD64_NUM_COUNTERS_CORE; x86_pmu.num_counters = AMD64_NUM_COUNTERS_CORE;
printk(KERN_INFO "perf: AMD core performance counters detected\n"); pr_cont("core perfctr, ");
return 0; return 0;
} }
__init int amd_pmu_init(void) __init int amd_pmu_init(void)
{ {
int ret;
/* Performance-monitoring supported from K7 and later: */ /* Performance-monitoring supported from K7 and later: */
if (boot_cpu_data.x86 < 6) if (boot_cpu_data.x86 < 6)
return -ENODEV; return -ENODEV;
x86_pmu = amd_pmu; x86_pmu = amd_pmu;
setup_event_constraints(); ret = amd_core_pmu_init();
setup_perfctr_core(); if (ret)
return ret;
/* Events are common for all AMDs */ /* Events are common for all AMDs */
memcpy(hw_cache_event_ids, amd_hw_cache_event_ids, memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
......
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