Commit 1bfa3eaa authored by Shengjiu Wang's avatar Shengjiu Wang Committed by Mark Brown

ASoC: fsl_spdif: Add support for higher sample rates

Add 88200Hz and 176400Hz sample rates support for TX.
Add 88200Hz, 176400Hz, 192000Hz sample rates support for RX.
Signed-off-by: default avatarViorel Suman <viorel.suman@nxp.com>
Signed-off-by: default avatarShengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: default avatarNicolin Chen <nicoleotsuka@gmail.com>
Reviewed-by: default avatarDaniel Baluta <daniel.baluta@nxp.com>
Link: https://lore.kernel.org/r/1602557360-18795-1-git-send-email-shengjiu.wang@nxp.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent 516232e3
...@@ -459,10 +459,18 @@ static int spdif_set_sample_rate(struct snd_pcm_substream *substream, ...@@ -459,10 +459,18 @@ static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
rate = SPDIF_TXRATE_48000; rate = SPDIF_TXRATE_48000;
csfs = IEC958_AES3_CON_FS_48000; csfs = IEC958_AES3_CON_FS_48000;
break; break;
case 88200:
rate = SPDIF_TXRATE_88200;
csfs = IEC958_AES3_CON_FS_88200;
break;
case 96000: case 96000:
rate = SPDIF_TXRATE_96000; rate = SPDIF_TXRATE_96000;
csfs = IEC958_AES3_CON_FS_96000; csfs = IEC958_AES3_CON_FS_96000;
break; break;
case 176400:
rate = SPDIF_TXRATE_176400;
csfs = IEC958_AES3_CON_FS_176400;
break;
case 192000: case 192000:
rate = SPDIF_TXRATE_192000; rate = SPDIF_TXRATE_192000;
csfs = IEC958_AES3_CON_FS_192000; csfs = IEC958_AES3_CON_FS_192000;
...@@ -857,7 +865,7 @@ static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol, ...@@ -857,7 +865,7 @@ static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol,
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
uinfo->count = 1; uinfo->count = 1;
uinfo->value.integer.min = 16000; uinfo->value.integer.min = 16000;
uinfo->value.integer.max = 96000; uinfo->value.integer.max = 192000;
return 0; return 0;
} }
...@@ -1175,7 +1183,8 @@ static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv, ...@@ -1175,7 +1183,8 @@ static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv,
struct clk *clk, u64 savesub, struct clk *clk, u64 savesub,
enum spdif_txrate index, bool round) enum spdif_txrate index, bool round)
{ {
static const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 }; static const u32 rate[] = { 32000, 44100, 48000, 88200, 96000, 176400,
192000, };
bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk); bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk);
u64 rate_ideal, rate_actual, sub; u64 rate_ideal, rate_actual, sub;
u32 arate; u32 arate;
...@@ -1235,7 +1244,8 @@ static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv, ...@@ -1235,7 +1244,8 @@ static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv,
static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv, static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv,
enum spdif_txrate index) enum spdif_txrate index)
{ {
static const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 }; static const u32 rate[] = { 32000, 44100, 48000, 88200, 96000, 176400,
192000, };
struct platform_device *pdev = spdif_priv->pdev; struct platform_device *pdev = spdif_priv->pdev;
struct device *dev = &pdev->dev; struct device *dev = &pdev->dev;
u64 savesub = 100000, ret; u64 savesub = 100000, ret;
......
...@@ -163,7 +163,9 @@ enum spdif_txrate { ...@@ -163,7 +163,9 @@ enum spdif_txrate {
SPDIF_TXRATE_32000 = 0, SPDIF_TXRATE_32000 = 0,
SPDIF_TXRATE_44100, SPDIF_TXRATE_44100,
SPDIF_TXRATE_48000, SPDIF_TXRATE_48000,
SPDIF_TXRATE_88200,
SPDIF_TXRATE_96000, SPDIF_TXRATE_96000,
SPDIF_TXRATE_176400,
SPDIF_TXRATE_192000, SPDIF_TXRATE_192000,
}; };
#define SPDIF_TXRATE_MAX (SPDIF_TXRATE_192000 + 1) #define SPDIF_TXRATE_MAX (SPDIF_TXRATE_192000 + 1)
...@@ -177,15 +179,20 @@ enum spdif_txrate { ...@@ -177,15 +179,20 @@ enum spdif_txrate {
#define FSL_SPDIF_RATES_PLAYBACK (SNDRV_PCM_RATE_32000 | \ #define FSL_SPDIF_RATES_PLAYBACK (SNDRV_PCM_RATE_32000 | \
SNDRV_PCM_RATE_44100 | \ SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000 | \ SNDRV_PCM_RATE_48000 | \
SNDRV_PCM_RATE_88200 | \
SNDRV_PCM_RATE_96000 | \ SNDRV_PCM_RATE_96000 | \
SNDRV_PCM_RATE_176400 | \
SNDRV_PCM_RATE_192000) SNDRV_PCM_RATE_192000)
#define FSL_SPDIF_RATES_CAPTURE (SNDRV_PCM_RATE_16000 | \ #define FSL_SPDIF_RATES_CAPTURE (SNDRV_PCM_RATE_16000 | \
SNDRV_PCM_RATE_32000 | \ SNDRV_PCM_RATE_32000 | \
SNDRV_PCM_RATE_44100 | \ SNDRV_PCM_RATE_44100 | \
SNDRV_PCM_RATE_48000 | \ SNDRV_PCM_RATE_48000 | \
SNDRV_PCM_RATE_88200 | \
SNDRV_PCM_RATE_64000 | \ SNDRV_PCM_RATE_64000 | \
SNDRV_PCM_RATE_96000) SNDRV_PCM_RATE_96000 | \
SNDRV_PCM_RATE_176400 | \
SNDRV_PCM_RATE_192000)
#define FSL_SPDIF_FORMATS_PLAYBACK (SNDRV_PCM_FMTBIT_S16_LE | \ #define FSL_SPDIF_FORMATS_PLAYBACK (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S20_3LE | \ SNDRV_PCM_FMTBIT_S20_3LE | \
......
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