Commit 1c278f8e authored by Arnd Bergmann's avatar Arnd Bergmann

Merge tag 'qcom-dts-fixes-for-6.4' of...

Merge tag 'qcom-dts-fixes-for-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes

Qualcomm ARM32 fix for 6.4

A range of 32-bit Qualcomm platforms are missing cache-unified, which is
now required by the binding, this is now corrected.

* tag 'qcom-dts-fixes-for-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  ARM: dts: qcom: add missing cache properties

Link: https://lore.kernel.org/r/20230601140347.2245680-1-andersson@kernel.orgSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 7877cb91 925a80af
...@@ -83,6 +83,7 @@ CPU3: cpu@3 { ...@@ -83,6 +83,7 @@ CPU3: cpu@3 {
L2: l2-cache { L2: l2-cache {
compatible = "cache"; compatible = "cache";
cache-level = <2>; cache-level = <2>;
cache-unified;
}; };
idle-states { idle-states {
......
...@@ -74,6 +74,7 @@ cpu@3 { ...@@ -74,6 +74,7 @@ cpu@3 {
L2: l2-cache { L2: l2-cache {
compatible = "cache"; compatible = "cache";
cache-level = <2>; cache-level = <2>;
cache-unified;
qcom,saw = <&saw_l2>; qcom,saw = <&saw_l2>;
}; };
......
...@@ -102,6 +102,7 @@ cpu@3 { ...@@ -102,6 +102,7 @@ cpu@3 {
L2: l2-cache { L2: l2-cache {
compatible = "cache"; compatible = "cache";
cache-level = <2>; cache-level = <2>;
cache-unified;
qcom,saw = <&saw_l2>; qcom,saw = <&saw_l2>;
}; };
}; };
......
...@@ -45,6 +45,7 @@ cpu1: cpu@1 { ...@@ -45,6 +45,7 @@ cpu1: cpu@1 {
L2: l2-cache { L2: l2-cache {
compatible = "cache"; compatible = "cache";
cache-level = <2>; cache-level = <2>;
cache-unified;
}; };
}; };
......
...@@ -36,6 +36,7 @@ cpu@1 { ...@@ -36,6 +36,7 @@ cpu@1 {
L2: l2-cache { L2: l2-cache {
compatible = "cache"; compatible = "cache";
cache-level = <2>; cache-level = <2>;
cache-unified;
}; };
}; };
......
...@@ -42,6 +42,7 @@ cpu@1 { ...@@ -42,6 +42,7 @@ cpu@1 {
L2: l2-cache { L2: l2-cache {
compatible = "cache"; compatible = "cache";
cache-level = <2>; cache-level = <2>;
cache-unified;
}; };
}; };
......
...@@ -80,6 +80,7 @@ CPU3: cpu@3 { ...@@ -80,6 +80,7 @@ CPU3: cpu@3 {
L2: l2-cache { L2: l2-cache {
compatible = "cache"; compatible = "cache";
cache-level = <2>; cache-level = <2>;
cache-unified;
qcom,saw = <&saw_l2>; qcom,saw = <&saw_l2>;
}; };
......
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