Commit 1c2a7eb7 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Simon Horman

ARM: shmobile: r8a73a4: Add IRQC clock to device tree

Link the external IRQ controllers irqc0 and irqc1 to the IRQC module
clock, so they can be power managed using that clock.
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
[horms: corrected typo in changelog to refer to r8a73a4]
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent dfaac7b7
...@@ -163,6 +163,7 @@ irqc0: interrupt-controller@e61c0000 { ...@@ -163,6 +163,7 @@ irqc0: interrupt-controller@e61c0000 {
<0 29 IRQ_TYPE_LEVEL_HIGH>, <0 29 IRQ_TYPE_LEVEL_HIGH>,
<0 30 IRQ_TYPE_LEVEL_HIGH>, <0 30 IRQ_TYPE_LEVEL_HIGH>,
<0 31 IRQ_TYPE_LEVEL_HIGH>; <0 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
power-domains = <&pd_c4>; power-domains = <&pd_c4>;
}; };
...@@ -197,6 +198,7 @@ irqc1: interrupt-controller@e61c0200 { ...@@ -197,6 +198,7 @@ irqc1: interrupt-controller@e61c0200 {
<0 55 IRQ_TYPE_LEVEL_HIGH>, <0 55 IRQ_TYPE_LEVEL_HIGH>,
<0 56 IRQ_TYPE_LEVEL_HIGH>, <0 56 IRQ_TYPE_LEVEL_HIGH>,
<0 57 IRQ_TYPE_LEVEL_HIGH>; <0 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
power-domains = <&pd_c4>; power-domains = <&pd_c4>;
}; };
...@@ -724,15 +726,16 @@ R8A73A4_CLK_CMT1 ...@@ -724,15 +726,16 @@ R8A73A4_CLK_CMT1
mstp4_clks: mstp4_clks@e6150140 { mstp4_clks: mstp4_clks@e6150140 {
compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_HP>, clocks = <&main_div2_clk>, <&main_div2_clk>,
<&cpg_clocks R8A73A4_CLK_HP>,
<&cpg_clocks R8A73A4_CLK_HP>; <&cpg_clocks R8A73A4_CLK_HP>;
#clock-cells = <1>; #clock-cells = <1>;
clock-indices = < clock-indices = <
R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4 R8A73A4_CLK_IRQC R8A73A4_CLK_IIC5
R8A73A4_CLK_IIC3 R8A73A4_CLK_IIC4 R8A73A4_CLK_IIC3
>; >;
clock-output-names = clock-output-names =
"iic5", "iic4", "iic3"; "irqc", "iic5", "iic4", "iic3";
}; };
mstp5_clks: mstp5_clks@e6150144 { mstp5_clks: mstp5_clks@e6150144 {
compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
......
...@@ -54,6 +54,7 @@ ...@@ -54,6 +54,7 @@
#define R8A73A4_CLK_IIC3 11 #define R8A73A4_CLK_IIC3 11
#define R8A73A4_CLK_IIC4 10 #define R8A73A4_CLK_IIC4 10
#define R8A73A4_CLK_IIC5 9 #define R8A73A4_CLK_IIC5 9
#define R8A73A4_CLK_IRQC 7
/* MSTP5 */ /* MSTP5 */
#define R8A73A4_CLK_THERMAL 22 #define R8A73A4_CLK_THERMAL 22
......
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