Commit 1d3361f6 authored by Tomi Valkeinen's avatar Tomi Valkeinen

ARM: dts: set 'ti,set-rate-parent' for dpll4_m4 path

Set 'ti,set-rate-parent' property for clocks in the dpll4_m4 clock
path, which is used for DSS functional clock. This fixes DSS driver's
clock rate configuration, which needs the rate to be propagated properly
to the divider node (dpll4_m4_ck).
Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
Tested-by: default avatarChristoph Fritz <chf.fritz@googlemail.com>
Tested-by: default avatarMarek Belisko <marek@goldelico.com>
Acked-by: default avatarTony Lindgren <tony@atomide.com>
parent c368dbe2
...@@ -429,6 +429,7 @@ dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck { ...@@ -429,6 +429,7 @@ dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
clocks = <&dpll4_m4_ck>; clocks = <&dpll4_m4_ck>;
ti,clock-mult = <2>; ti,clock-mult = <2>;
ti,clock-div = <1>; ti,clock-div = <1>;
ti,set-rate-parent;
}; };
dpll4_m4x2_ck: dpll4_m4x2_ck { dpll4_m4x2_ck: dpll4_m4x2_ck {
...@@ -438,6 +439,7 @@ dpll4_m4x2_ck: dpll4_m4x2_ck { ...@@ -438,6 +439,7 @@ dpll4_m4x2_ck: dpll4_m4x2_ck {
ti,bit-shift = <0x1d>; ti,bit-shift = <0x1d>;
reg = <0x0d00>; reg = <0x0d00>;
ti,set-bit-to-disable; ti,set-bit-to-disable;
ti,set-rate-parent;
}; };
dpll4_m5_ck: dpll4_m5_ck { dpll4_m5_ck: dpll4_m5_ck {
......
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