Merge samba.org:/home/anton/ppc64/linux-2.5

into samba.org:/home/anton/ppc64/for-linus-ppc64

arch/ppc64/kernel/head.S

@@ -937,7 +937,6 @@ _GLOBAL(do_stab_bolted)
 	mfspr	r20,SPRG2
 	mfspr	r21,SPRG1
 	rfid
-_TRACEBACK(do_stab_bolted)
 
 /*
  * r20 points to the PACA, r21 to the exception frame,
@@ -1052,7 +1051,6 @@ SLB_NUM_ENTRIES = 64
 	mfspr	r20,SPRG2
 	mfspr	r21,SPRG1
 	rfid
-_TRACEBACK(do_slb_bolted)
 
 _GLOBAL(do_stab_SI)
 	mflr	r21			/* Save LR in r21 */

arch/ppc64/kernel/idle.c

@@ -84,8 +84,6 @@ int cpu_idle(void)
 	lpaca = get_paca();
 
 	while (1) {
-		irq_stat[smp_processor_id()].idle_timestamp = jiffies;
-
 		if (lpaca->xLpPaca.xSharedProc) {
 			if (ItLpQueue_isLpIntPending(lpaca->lpQueuePtr))
 				process_iSeries_events();
@@ -125,7 +123,6 @@ int cpu_idle(void)
 	long oldval;
 
 	while (1) {
-		irq_stat[smp_processor_id()].idle_timestamp = jiffies;
 		oldval = test_and_clear_thread_flag(TIF_NEED_RESCHED);
 
 		if (!oldval) {

arch/ppc64/kernel/irq.c

@@ -273,7 +273,9 @@ EXPORT_SYMBOL(free_irq);
  
 void disable_irq(unsigned int irq)
 {
+	irq_desc_t *desc = irq_desc + irq;
 	disable_irq_nosync(irq);
+	if (desc->action)
 		synchronize_irq(irq);
 }
 

arch/ppc64/kernel/misc.S

@@ -359,7 +359,7 @@ _GLOBAL(_outsl)
 	bdnz	00b
 	blr	
 
-_GLOBAL(ide_insw)
+/* _GLOBAL(ide_insw) now in drivers/ide/ide-iops.c */
 _GLOBAL(_insw_ns)
 	cmpwi	0,r5,0
 	mtctr	r5
@@ -371,7 +371,7 @@ _GLOBAL(_insw_ns)
 	bdnz	00b
 	blr
 
-_GLOBAL(ide_outsw)
+/* _GLOBAL(ide_outsw) now in drivers/ide/ide-iops.c */
 _GLOBAL(_outsw_ns)
 	cmpwi	0,r5,0
 	mtctr	r5

arch/ppc64/kernel/pci_dma.c

@@ -98,7 +98,7 @@ void free_tce_range_nolock(struct TceTable *,
 			   unsigned order );
 
 /* allocates a range of tces and sets them to the pages  */
-static inline dma_addr_t get_tces( struct TceTable *, 
+inline dma_addr_t get_tces( struct TceTable *, 
 				   unsigned order, 
 				   void *page, 
 				   unsigned numPages,
@@ -210,7 +210,7 @@ static void tce_build_pSeries(struct TceTable *tbl, long tcenum,
  * Build a TceTable structure.  This contains a multi-level bit map which
  * is used to manage allocation of the tce space.
  */
-static struct TceTable *build_tce_table( struct TceTable * tbl )
+struct TceTable *build_tce_table( struct TceTable * tbl )
 {
 	unsigned long bits, bytes, totalBytes;
 	unsigned long numBits[NUM_TCE_LEVELS], numBytes[NUM_TCE_LEVELS];
@@ -518,7 +518,7 @@ static long test_tce_range( struct TceTable *tbl, long tcenum, unsigned order )
 	return retval;
 }
 
-static inline dma_addr_t get_tces( struct TceTable *tbl, unsigned order, void *page, unsigned numPages, int direction )
+inline dma_addr_t get_tces( struct TceTable *tbl, unsigned order, void *page, unsigned numPages, int direction )
 {
 	long tcenum;
 	unsigned long uaddr;
@@ -581,7 +581,7 @@ static void tce_free_one_pSeries( struct TceTable *tbl, long tcenum )
 }
 #endif
 
-static void tce_free(struct TceTable *tbl, dma_addr_t dma_addr, 
+void tce_free(struct TceTable *tbl, dma_addr_t dma_addr, 
 			     unsigned order, unsigned num_pages)
 {
 	long tcenum, total_tces, free_tce;

arch/ppc64/kernel/ppc_ksyms.c

@@ -227,3 +227,4 @@ EXPORT_SYMBOL(debugger_fault_handler);
 #endif
 
 EXPORT_SYMBOL(tb_ticks_per_usec);
+EXPORT_SYMBOL(paca);

arch/ppc64/mm/hugetlbpage.c

@@ -507,14 +507,21 @@ int hugetlb_prefault(struct address_space *mapping, struct vm_area_struct *vma)
 			+ (vma->vm_pgoff >> (HPAGE_SHIFT - PAGE_SHIFT));
 		page = find_get_page(mapping, idx);
 		if (!page) {
+			/* charge the fs quota first */
+			if (hugetlb_get_quota(mapping)) {
+				ret = -ENOMEM;
+				goto out;
+			}
 			page = alloc_hugetlb_page();
 			if (!page) {
+				hugetlb_put_quota(mapping);
 				ret = -ENOMEM;
 				goto out;
 			}
 			ret = add_to_page_cache(page, mapping, idx, GFP_ATOMIC);
 			unlock_page(page);
 			if (ret) {
+				hugetlb_put_quota(mapping);
 				free_huge_page(page);
 				goto out;
 			}

arch/ppc64/mm/init.c

@@ -726,3 +726,22 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long ea,
 	__hash_page(ea, pte_val(pte) & (_PAGE_USER|_PAGE_RW), vsid, ptep,
 		    0x300, local);
 }
+
+kmem_cache_t *zero_cache;
+
+static void zero_ctor(void *pte, kmem_cache_t *cache, unsigned long flags)
+{
+	memset(pte, 0, PAGE_SIZE);
+}
+
+void pgtable_cache_init(void)
+{
+	zero_cache = kmem_cache_create("zero",
+				PAGE_SIZE,
+				0,
+				SLAB_HWCACHE_ALIGN | SLAB_MUST_HWCACHE_ALIGN,
+				zero_ctor,
+				NULL);
+	if (!zero_cache)
+		panic("pgtable_cache_init(): could not create zero_cache!\n");
+}

arch/ppc64/mm/numa.c

@@ -13,6 +13,7 @@
 #include <linux/init.h>
 #include <linux/mm.h>
 #include <linux/mmzone.h>
+#include <linux/module.h>
 #include <asm/lmb.h>
 
 #if 1
@@ -306,6 +307,7 @@ void __init paging_init(void)
 {
 	unsigned long zones_size[MAX_NR_ZONES];
 	int i, nid;
+	struct page *node_mem_map; 
 
 	for (i = 1; i < MAX_NR_ZONES; i++)
 		zones_size[i] = 0;
@@ -314,16 +316,24 @@ void __init paging_init(void)
 		unsigned long start_pfn;
 		unsigned long end_pfn;
 
-		if (node_data[nid].node_spanned_pages == 0)
-			continue;
-
 		start_pfn = plat_node_bdata[nid].node_boot_start >> PAGE_SHIFT;
 		end_pfn = plat_node_bdata[nid].node_low_pfn;
 
 		zones_size[ZONE_DMA] = end_pfn - start_pfn;
 		dbg("free_area_init node %d %lx %lx\n", nid,
 				zones_size[ZONE_DMA], start_pfn);
-		free_area_init_node(nid, NODE_DATA(nid), NULL, zones_size,
-				    start_pfn, NULL);
+
+		/* 
+		 * Give this empty node a dummy struct page to avoid
+		 * us from trying to allocate a node local mem_map
+		 * in free_area_init_node (which will fail).
+		 */
+		if (!node_data[nid].node_spanned_pages)
+			node_mem_map = alloc_bootmem(sizeof(struct page));
+		else
+			node_mem_map = NULL;
+
+		free_area_init_node(nid, NODE_DATA(nid), node_mem_map,
+				    zones_size, start_pfn, NULL);
 	}
 }

include/asm-ppc64/cputable.h

@@ -30,7 +30,7 @@
 #ifndef __ASSEMBLY__
 
 /* This structure can grow, it's real size is used by head.S code
- * via the mkdefs mecanism.
+ * via the mkdefs mechanism.
  */
 struct cpu_spec;
 

include/asm-ppc64/hardirq.h

@@ -15,9 +15,7 @@
 
 typedef struct {
 	unsigned int __softirq_pending;
-	unsigned int __syscall_count;
 	struct task_struct * __ksoftirqd_task;
-	unsigned long idle_timestamp;
 } ____cacheline_aligned irq_cpustat_t;
 
 #include <linux/irq_cpustat.h>	/* Standard mappings for irq_cpustat_t above */

include/asm-ppc64/io.h

@@ -17,6 +17,12 @@
 #include <asm/memory.h>
 #include <asm/delay.h>
 
+#define __ide_mm_insw(p, a, c) _insw_ns((volatile u16 *)(p), (a), (c))
+#define __ide_mm_insl(p, a, c) _insl_ns((volatile u32 *)(p), (a), (c))
+#define __ide_mm_outsw(p, a, c) _outsw_ns((volatile u16 *)(p), (a), (c))
+#define __ide_mm_outsl(p, a, c) _outsl_ns((volatile u32 *)(p), (a), (c))
+
+
 #define SIO_CONFIG_RA	0x398
 #define SIO_CONFIG_RD	0x399
 
@@ -93,7 +99,7 @@ extern void _outsl_ns(volatile u32 *port, const void *buf, int nl);
 #define inw_p(port)             inw(port)
 #define outw_p(val, port)       (udelay(1), outw((val), (port)))
 #define inl_p(port)             inl(port)
-#define outl_p(val, port)       (udelay(1), outl((val, (port)))
+#define outl_p(val, port)       (udelay(1), outl((val), (port)))
 
 /*
  * The *_ns versions below don't do byte-swapping.

include/asm-ppc64/memory.h

@@ -58,7 +58,7 @@ static inline void isync(void)
 
 #define HMT_LOW
 #define HMT_MEDIUM
-#define HMT_LOW
+#define HMT_HIGH
 #endif
 
 #endif

include/asm-ppc64/pgalloc.h

@@ -2,8 +2,11 @@
 #define _PPC64_PGALLOC_H
 
 #include <linux/mm.h>
+#include <linux/slab.h>
 #include <asm/processor.h>
 
+extern kmem_cache_t *zero_cache;
+
 /*
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -14,16 +17,13 @@
 static inline pgd_t *
 pgd_alloc(struct mm_struct *mm)
 {
-	pgd_t *pgd = (pgd_t *)__get_free_page(GFP_KERNEL);
-	if (pgd != NULL)
-		clear_page(pgd);
-	return pgd;
+	return kmem_cache_alloc(zero_cache, GFP_KERNEL);
 }
 
 static inline void
 pgd_free(pgd_t *pgd)
 {
-	free_page((unsigned long)pgd);
+	kmem_cache_free(zero_cache, pgd);
 }
 
 #define pgd_populate(MM, PGD, PMD)	pgd_set(PGD, PMD)
@@ -31,18 +31,13 @@ pgd_free(pgd_t *pgd)
 static inline pmd_t *
 pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
 {
-	pmd_t *pmd;
-
-	pmd = (pmd_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT);
-	if (pmd)
-		clear_page(pmd);
-	return pmd;
+	return kmem_cache_alloc(zero_cache, GFP_KERNEL|__GFP_REPEAT);
 }
 
 static inline void
 pmd_free(pmd_t *pmd)
 {
-	free_page((unsigned long)pmd);
+	kmem_cache_free(zero_cache, pmd);
 }
 
 #define __pmd_free_tlb(tlb, pmd)	pmd_free(pmd)
@@ -54,12 +49,7 @@ pmd_free(pmd_t *pmd)
 static inline pte_t *
 pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr)
 {
-	pte_t *pte;
-
-	pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT);
-	if (pte)
-		clear_page(pte);
-	return pte;
+	return kmem_cache_alloc(zero_cache, GFP_KERNEL|__GFP_REPEAT);
 }
 
 static inline struct page *
@@ -76,7 +66,7 @@ pte_alloc_one(struct mm_struct *mm, unsigned long address)
 static inline void
 pte_free_kernel(pte_t *pte)
 {
-	free_page((unsigned long)pte);
+	kmem_cache_free(zero_cache, pte);
 }
 
 #define pte_free(pte_page)	pte_free_kernel(page_address(pte_page))

include/asm-ppc64/pgtable.h

@@ -394,10 +394,7 @@ extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
 
 #define io_remap_page_range remap_page_range 
 
-/*
- * No page table caches to initialise
- */
-#define pgtable_cache_init()	do { } while (0)
+void pgtable_cache_init(void);
 
 extern void hpte_init_pSeries(void);
 extern void hpte_init_iSeries(void);

include/asm-ppc64/processor.h

@@ -128,14 +128,6 @@
 #define	SPRN_DAC1	0x3F6	/* Data Address Compare 1 */
 #define	SPRN_DAC2	0x3F7	/* Data Address Compare 2 */
 #define	SPRN_DAR	0x013	/* Data Address Register */
-#define	SPRN_DBAT0L	0x219	/* Data BAT 0 Lower Register */
-#define	SPRN_DBAT0U	0x218	/* Data BAT 0 Upper Register */
-#define	SPRN_DBAT1L	0x21B	/* Data BAT 1 Lower Register */
-#define	SPRN_DBAT1U	0x21A	/* Data BAT 1 Upper Register */
-#define	SPRN_DBAT2L	0x21D	/* Data BAT 2 Lower Register */
-#define	SPRN_DBAT2U	0x21C	/* Data BAT 2 Upper Register */
-#define	SPRN_DBAT3L	0x21F	/* Data BAT 3 Lower Register */
-#define	SPRN_DBAT3U	0x21E	/* Data BAT 3 Upper Register */
 #define	SPRN_DBCR	0x3F2	/* Debug Control Regsiter */
 #define	  DBCR_EDM	0x80000000
 #define	  DBCR_IDM	0x40000000
@@ -229,14 +221,6 @@
 #define	SPRN_TST 	0x3FC	/* Thread switch timeout */
 #define	SPRN_IAC1	0x3F4	/* Instruction Address Compare 1 */
 #define	SPRN_IAC2	0x3F5	/* Instruction Address Compare 2 */
-#define	SPRN_IBAT0L	0x211	/* Instruction BAT 0 Lower Register */
-#define	SPRN_IBAT0U	0x210	/* Instruction BAT 0 Upper Register */
-#define	SPRN_IBAT1L	0x213	/* Instruction BAT 1 Lower Register */
-#define	SPRN_IBAT1U	0x212	/* Instruction BAT 1 Upper Register */
-#define	SPRN_IBAT2L	0x215	/* Instruction BAT 2 Lower Register */
-#define	SPRN_IBAT2U	0x214	/* Instruction BAT 2 Upper Register */
-#define	SPRN_IBAT3L	0x217	/* Instruction BAT 3 Lower Register */
-#define	SPRN_IBAT3U	0x216	/* Instruction BAT 3 Upper Register */
 #define	SPRN_ICCR	0x3FB	/* Instruction Cache Cacheability Register */
 #define	  ICCR_NOCACHE		0	/* Noncacheable */
 #define	  ICCR_CACHE		1	/* Cacheable */
@@ -333,14 +317,6 @@
 #define	CTR	SPRN_CTR	/* Counter Register */
 #define	DAR	SPRN_DAR	/* Data Address Register */
 #define	DABR	SPRN_DABR	/* Data Address Breakpoint Register */
-#define	DBAT0L	SPRN_DBAT0L	/* Data BAT 0 Lower Register */
-#define	DBAT0U	SPRN_DBAT0U	/* Data BAT 0 Upper Register */
-#define	DBAT1L	SPRN_DBAT1L	/* Data BAT 1 Lower Register */
-#define	DBAT1U	SPRN_DBAT1U	/* Data BAT 1 Upper Register */
-#define	DBAT2L	SPRN_DBAT2L	/* Data BAT 2 Lower Register */
-#define	DBAT2U	SPRN_DBAT2U	/* Data BAT 2 Upper Register */
-#define	DBAT3L	SPRN_DBAT3L	/* Data BAT 3 Lower Register */
-#define	DBAT3U	SPRN_DBAT3U	/* Data BAT 3 Upper Register */
 #define	DCMP	SPRN_DCMP      	/* Data TLB Compare Register */
 #define	DEC	SPRN_DEC       	/* Decrement Register */
 #define	DMISS	SPRN_DMISS     	/* Data TLB Miss Register */
@@ -354,14 +330,6 @@
 #define	TSC    	SPRN_TSC 	/* Thread switch control */
 #define	TST    	SPRN_TST 	/* Thread switch timeout */
 #define	IABR	SPRN_IABR      	/* Instruction Address Breakpoint Register */
-#define	IBAT0L	SPRN_IBAT0L	/* Instruction BAT 0 Lower Register */
-#define	IBAT0U	SPRN_IBAT0U	/* Instruction BAT 0 Upper Register */
-#define	IBAT1L	SPRN_IBAT1L	/* Instruction BAT 1 Lower Register */
-#define	IBAT1U	SPRN_IBAT1U	/* Instruction BAT 1 Upper Register */
-#define	IBAT2L	SPRN_IBAT2L	/* Instruction BAT 2 Lower Register */
-#define	IBAT2U	SPRN_IBAT2U	/* Instruction BAT 2 Upper Register */
-#define	IBAT3L	SPRN_IBAT3L	/* Instruction BAT 3 Lower Register */
-#define	IBAT3U	SPRN_IBAT3U	/* Instruction BAT 3 Upper Register */
 #define	ICMP	SPRN_ICMP	/* Instruction TLB Compare Register */
 #define	IMISS	SPRN_IMISS	/* Instruction TLB Miss Register */
 #define	IMMR	SPRN_IMMR      	/* PPC 860/821 Internal Memory Map Register */
@@ -391,84 +359,6 @@
 #define	THRM3	SPRN_THRM3	/* Thermal Management Register 3 */
 #define	XER	SPRN_XER
 
-
-/* Device Control Registers */
-
-#define	DCRN_BEAR	0x090	/* Bus Error Address Register */
-#define	DCRN_BESR	0x091	/* Bus Error Syndrome Register */
-#define	  BESR_DSES    	0x80000000	/* Data-Side Error Status */
-#define	  BESR_DMES	0x40000000	/* DMA Error Status */
-#define	  BESR_RWS	0x20000000	/* Read/Write Status */
-#define	  BESR_ETMASK	0x1C000000	/* Error Type */
-#define	    ET_PROT	0
-#define	    ET_PARITY	1
-#define	    ET_NCFG	2
-#define	    ET_BUSERR	4
-#define	    ET_BUSTO	6
-#define	DCRN_DMACC0	0x0C4	/* DMA Chained Count Register 0 */
-#define	DCRN_DMACC1	0x0CC	/* DMA Chained Count Register 1 */
-#define	DCRN_DMACC2	0x0D4	/* DMA Chained Count Register 2 */
-#define	DCRN_DMACC3	0x0DC    /* DMA Chained Count Register 3 */
-#define	DCRN_DMACR0	0x0C0    /* DMA Channel Control Register 0 */
-#define	DCRN_DMACR1	0x0C8    /* DMA Channel Control Register 1 */
-#define	DCRN_DMACR2	0x0D0    /* DMA Channel Control Register 2 */
-#define	DCRN_DMACR3	0x0D8    /* DMA Channel Control Register 3 */
-#define	DCRN_DMACT0	0x0C1    /* DMA Count Register 0 */
-#define	DCRN_DMACT1	0x0C9    /* DMA Count Register 1 */
-#define	DCRN_DMACT2	0x0D1    /* DMA Count Register 2 */
-#define	DCRN_DMACT3	0x0D9    /* DMA Count Register 3 */
-#define	DCRN_DMADA0	0x0C2    /* DMA Destination Address Register 0 */
-#define	DCRN_DMADA1	0x0CA    /* DMA Destination Address Register 1 */
-#define	DCRN_DMADA2	0x0D2    /* DMA Destination Address Register 2 */
-#define	DCRN_DMADA3	0x0DA    /* DMA Destination Address Register 3 */
-#define	DCRN_DMASA0	0x0C3    /* DMA Source Address Register 0 */
-#define	DCRN_DMASA1	0x0CB    /* DMA Source Address Register 1 */
-#define	DCRN_DMASA2	0x0D3    /* DMA Source Address Register 2 */
-#define	DCRN_DMASA3	0x0DB    /* DMA Source Address Register 3 */
-#define	DCRN_DMASR	0x0E0    /* DMA Status Register */
-#define	DCRN_EXIER	0x042    /* External Interrupt Enable Register */
-#define	  EXIER_CIE	0x80000000	/* Critical Interrupt Enable */
-#define	  EXIER_SRIE	0x08000000	/* Serial Port Rx Int. Enable */
-#define	  EXIER_STIE	0x04000000	/* Serial Port Tx Int. Enable */
-#define	  EXIER_JRIE	0x02000000	/* JTAG Serial Port Rx Int. Enable */
-#define	  EXIER_JTIE	0x01000000	/* JTAG Serial Port Tx Int. Enable */
-#define	  EXIER_D0IE	0x00800000	/* DMA Channel 0 Interrupt Enable */
-#define	  EXIER_D1IE	0x00400000	/* DMA Channel 1 Interrupt Enable */
-#define	  EXIER_D2IE	0x00200000	/* DMA Channel 2 Interrupt Enable */
-#define	  EXIER_D3IE	0x00100000	/* DMA Channel 3 Interrupt Enable */
-#define	  EXIER_E0IE	0x00000010	/* External Interrupt 0 Enable */
-#define	  EXIER_E1IE	0x00000008	/* External Interrupt 1 Enable */
-#define	  EXIER_E2IE	0x00000004	/* External Interrupt 2 Enable */
-#define	  EXIER_E3IE	0x00000002	/* External Interrupt 3 Enable */
-#define	  EXIER_E4IE	0x00000001	/* External Interrupt 4 Enable */
-#define	DCRN_EXISR	0x040    /* External Interrupt Status Register */
-#define	DCRN_IOCR	0x0A0    /* Input/Output Configuration Register */
-#define	  IOCR_E0TE	0x80000000
-#define	  IOCR_E0LP	0x40000000
-#define	  IOCR_E1TE	0x20000000
-#define	  IOCR_E1LP	0x10000000
-#define	  IOCR_E2TE	0x08000000
-#define	  IOCR_E2LP	0x04000000
-#define	  IOCR_E3TE	0x02000000
-#define	  IOCR_E3LP	0x01000000
-#define	  IOCR_E4TE	0x00800000
-#define	  IOCR_E4LP	0x00400000
-#define	  IOCR_EDT     	0x00080000
-#define	  IOCR_SOR     	0x00040000
-#define	  IOCR_EDO	0x00008000
-#define	  IOCR_2XC	0x00004000
-#define	  IOCR_ATC	0x00002000
-#define	  IOCR_SPD	0x00001000
-#define	  IOCR_BEM	0x00000800
-#define	  IOCR_PTD	0x00000400
-#define	  IOCR_ARE	0x00000080
-#define	  IOCR_DRC	0x00000020
-#define	  IOCR_RDM(x)	(((x) & 0x3) << 3)
-#define	  IOCR_TCS	0x00000004
-#define	  IOCR_SCS	0x00000002
-#define	  IOCR_SPC	0x00000001
-
-
 /* Processor Version Register (PVR) field extraction */
 
 #define	PVR_VER(pvr)  (((pvr) >>  16) & 0xFFFF)	/* Version field */
@@ -499,26 +389,6 @@
 #define XGLUE(a,b) a##b
 #define GLUE(a,b) XGLUE(a,b)
 
-/*
- * Begining of traceback info work for asm functions.
- */
-#define TB_ASM		0x000C000000000000
-#define TB_GLOBALLINK	0x0000800000000000
-#define TB_IS_EPROL	0x0000400000000000
-#define TB_HAS_TBOFF	0x0000200000000000
-#define TB_INT_PROC	0x0000100000000000
-#define TB_HAS_CTL	0x0000080000000000
-#define TB_TOCLESS	0x0000040000000000
-#define TB_FP_PRESENT	0x0000020000000000
-#define TB_LOG_ABORT	0x0000010000000000
-#define TB_INT_HNDL	0x0000008000000000
-#define TB_NAME_PRESENT	0x0000004000000000
-#define TB_SAVES_CR	0x0000000200000000
-#define TB_SAVES_LR	0x0000000100000000
-#define TB_STORES_BC	0x0000000080000000
-#define TB_PARMINFO	0x000000000000FFFF
-#define TB_DEFAULT	TB_ASM | TB_HAS_TBOFF | TB_NAME_PRESENT
-
 #ifdef __ASSEMBLY__
 
 #define _GLOBAL(name) \
@@ -547,16 +417,6 @@ name: \
 	.type GLUE(.,name),@function; \
 GLUE(.,name):
 
-#define _TRACEBACK(NAME) \
-GLUE(.LT,NAME): ;\
-	.long 0 ;\
-	.llong TB_DEFAULT ;\
-	.long GLUE(.LT,NAME)-GLUE(.,NAME) ;\
-	.short GLUE(GLUE(.LT,NAME),_procname_end)-GLUE(GLUE(.LT,NAME),_procname_start) ;\
-GLUE(GLUE(.LT,NAME),_procname_start): ;\
-	.ascii __stringify(NAME) ;\
-GLUE(GLUE(.LT,NAME),_procname_end):
-
 #endif /* __ASSEMBLY__ */
 
 

include/asm-ppc64/siginfo.h

@@ -8,7 +8,7 @@
  * 2 of the License, or (at your option) any later version.
  */
 
-#define SI_PAD_SIZE    ((SI_MAX_SIZE/sizeof(int)) - 4)
+#define __ARCH_SI_PREAMBLE_SIZE	(4 * sizeof(int))
 #define SI_PAD_SIZE32		((SI_MAX_SIZE/sizeof(int)) - 3)
 
 #include <asm-generic/siginfo.h>