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Commit 1ea7c8b6 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'omap-for-v4.7/dt-part1' of... 

Merge tag 'omap-for-v4.7/dt-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt

Merge "First set of device tree changes for omaps for v4.7 merge window" from Tony Lindgren:

- Two sets of name and unit address check fixes for dts files.

- DMA, McASP, and timer and regulator related dts changes for dra7

- Add more devices for Nokia N9/N950

- Initial support for am335x ICEv2

- Initial support for am572x-IDK

- Pinctrl changes for am335x-baltos-ir5221

- Initial support for Amazon Kindle Fire (first generation)

- A series of changes to add GPIO controller support for the
  GPMC driver. The driver changes will be merged separately.

- Support for am43xx clkout1

- Pinctrl and RTC changes for am335x-chili

- Add support for dra72-evm rev C (SR2.0)

* tag 'omap-for-v4.7/dt-part1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (61 commits)
  ARM: dts: Add support for dra72-evm rev C (SR2.0)
  ARM: dts: am335x-chilisom: Enable poweroff PMIC sequence using RTC signal
  ARM: dts: am335x-chili*: Move Ethernet MAC description from SOM to board
  ARM: dts: am335x-chili*: Move uart0 description from SOM to board
  ARM: dts: am43xx: add support for clkout1 clock
  ARM: dts: omap3-beagle: Provide NAND ready pin
  ARM: dts: am335x: Provide NAND ready pin
  ARM: dts: am437x: Provide NAND ready pin
  ARM: dts: dra7x-evm: Provide NAND ready pin
  ARM: dts: dm816x: Enable gpio controller for GPMC
  ARM: dts: dm814x: Enable gpio controller for GPMC
  ARM: dts: omap3: Enable gpio controller for GPMC
  ARM: dts: am4372: Enable gpio controller for GPMC
  ARM: dts: am335x: Enable gpio controller for GPMC
  ARM: dts: dra7: Enable gpio controller for GPMC
  ARM: dts: omap5: Enable gpio and interrupt controller for GPMC
  ARM: dts: omap4: Enable gpio and interrupt controller for GPMC
  ARM: dts: omap24xx: Enable gpio and interrupt controller for GPMC
  ARM: dts: omap4-kc1: Power off support
  ARM: dts: omap4-kc1: LEDs support
  ...
parents c2499d68 a4240d3a
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Documentation/devicetree/bindings/arm/omap/omap.txt
View file @ 1ea7c8b6
......@@ -133,6 +133,9 @@ Boards:
- AM335X Bone : Low cost community board
compatible = "ti,am335x-bone", "ti,am33xx", "ti,omap3"
- AM3359 ICEv2 : Low cost Industrial Communication Engine EVM.
compatible = "ti,am3359-icev2", "ti,am33xx", "ti,omap3"
- AM335X OrionLXm : Substation Automation Platform
compatible = "novatech,am335x-lxm", "ti,am33xx"
......@@ -169,6 +172,9 @@ Boards:
- AM57XX SBC-AM57x
compatible = "compulab,sbc-am57x", "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
- AM5728 IDK
compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
- DRA742 EVM: Software Development Board for DRA742
compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"
......
Documentation/devicetree/bindings/vendor-prefixes.txt
View file @ 1ea7c8b6
......@@ -16,6 +16,7 @@ al Annapurna Labs
allwinner Allwinner Technology Co., Ltd.
alphascale AlphaScale Integrated Circuits Systems, Inc.
altr Altera Corp.
amazon Amazon.com, Inc.
amcc Applied Micro Circuits Corporation (APM, formally AMCC)
amd Advanced Micro Devices (AMD), Inc.
amlogic Amlogic, Inc.
......
arch/arm/boot/dts/Makefile
View file @ 1ea7c8b6
......@@ -511,6 +511,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \
am335x-cm-t335.dtb \
am335x-evm.dtb \
am335x-evmsk.dtb \
am335x-icev2.dtb \
am335x-lxm.dtb \
am335x-nano.dtb \
am335x-pepper.dtb \
......@@ -520,6 +521,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \
am335x-wega-rdk.dtb
dtb-$(CONFIG_ARCH_OMAP4) += \
omap4-duovero-parlor.dtb \
omap4-kc1.dtb \
omap4-panda.dtb \
omap4-panda-a4.dtb \
omap4-panda-es.dtb \
......@@ -543,8 +545,10 @@ dtb-$(CONFIG_SOC_DRA7XX) += \
am57xx-beagle-x15.dtb \
am57xx-cl-som-am57x.dtb \
am57xx-sbc-am57x.dtb \
am572x-idk.dtb \
dra7-evm.dtb \
dra72-evm.dtb
dra72-evm.dtb \
dra72-evm-revc.dtb
dtb-$(CONFIG_ARCH_ORION5X) += \
orion5x-kuroboxpro.dtb \
orion5x-lacie-d2-network.dtb \
......
arch/arm/boot/dts/am335x-baltos-ir5221.dts
View file @ 1ea7c8b6
......@@ -109,8 +109,8 @@ uart1_pins: pinmux_uart1_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0) /* uart1_rxd */
AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE0) /* uart1_txd */
AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_ctsn, INPUT | MODE0 */
AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_rtsn, OUTPUT | MODE0 */
AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart1_ctsn */
AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn */
AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */
AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */
AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */
......@@ -122,8 +122,8 @@ uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd_mux3 */
AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd_mux3 */
AM33XX_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE7) /* i2c0_sda.uart2_ctsn_mux0 */
AM33XX_IOPAD(0x98c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* i2c0_scl.uart2_rtsn_mux0 */
AM33XX_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE2) /* i2c0_sda.uart2_ctsn_mux0 */
AM33XX_IOPAD(0x98c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* i2c0_scl.uart2_rtsn_mux0 */
AM33XX_IOPAD(0x830, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */
AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.gpio1[13] DSR */
AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.gpio1[14] DCD */
......@@ -241,6 +241,7 @@ nand@0,0 {
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
nand-bus-width = <8>;
ti,nand-ecc-opt = "bch8";
ti,nand-xfer-type = "polled";
......@@ -287,8 +288,6 @@ &uart1 {
dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
cts-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
rts-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
status = "okay";
};
......@@ -300,8 +299,6 @@ &uart2 {
dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
status = "okay";
};
......
arch/arm/boot/dts/am335x-chiliboard.dts
View file @ 1ea7c8b6
......@@ -35,6 +35,59 @@ led1 {
};
&am33xx_pinmux {
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */
AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii_ref_clk */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* mdio_data.mdio_data */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
/* mdio_clk.mdio_clk */
AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
usb1_drvvbus: usb1_drvvbus {
pinctrl-single,pins = <
AM33XX_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */
......@@ -61,12 +114,34 @@ AM33XX_IOPAD(0x9e8, PIN_OUTPUT | MUX_MODE7) /* emu1.gpio3_8 */
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&ldo4_reg {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
/* Ethernet */
&mac {
slaves = <1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rmii";
......
arch/arm/boot/dts/am335x-chilisom.dtsi
View file @ 1ea7c8b6
......@@ -35,59 +35,6 @@ AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */
AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii_ref_clk */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* mdio_data.mdio_data */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)
/* mdio_clk.mdio_clk */
AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
nandflash_pins: nandflash_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
......@@ -109,13 +56,6 @@ AM33XX_IOPAD(0x89c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cl
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
......@@ -182,20 +122,8 @@ ldo4_reg: regulator@6 {
};
};
/* Ethernet MAC */
&mac {
slaves = <1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
&rtc {
system-power-controller;
};
/* NAND Flash */
......@@ -214,6 +142,7 @@ nand@0,0 {
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
......
arch/arm/boot/dts/am335x-cm-t335.dts
View file @ 1ea7c8b6
......@@ -411,6 +411,7 @@ nand@0,0 {
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
......
arch/arm/boot/dts/am335x-evm.dts
View file @ 1ea7c8b6
......@@ -524,6 +524,7 @@ nand@0,0 {
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
......
arch/arm/boot/dts/am335x-icev2.dts 0 → 100644
View file @ 1ea7c8b6
/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/*
* AM335x ICE V2 board
* http://www.ti.com/tool/tmdsice3359
*/
/dts-v1/;
#include "am33xx.dtsi"
/ {
model = "TI AM3359 ICE-V2";
compatible = "ti,am3359-icev2", "ti,am33xx";
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
vbat: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "vbat";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
};
vtt_fixed: fixedregulator@1 {
compatible = "regulator-fixed";
regulator-name = "vtt";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>;
regulator-always-on;
regulator-boot-on;
enable-active-high;
};
leds@0 {
compatible = "gpio-leds";
led@0 {
label = "out0";
gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@1 {
label = "out1";
gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@2 {
label = "out2";
gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@3 {
label = "out3";
gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@4 {
label = "out4";
gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@5 {
label = "out5";
gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@6 {
label = "out6";
gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@7 {
label = "out7";
gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
/* Tricolor status LEDs */
leds@1 {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&user_leds>;
led@0 {
label = "status0:red:cpu0";
gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "cpu0";
};
led@1 {
label = "status0:green:usr";
gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@2 {
label = "status0:yellow:usr";
gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@3 {
label = "status1:red:mmc0";
gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "mmc0";
};
led@4 {
label = "status1:green:usr";
gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led@5 {
label = "status1:yellow:usr";
gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
};
&am33xx_pinmux {
user_leds: user_leds {
pinctrl-single,pins = <
AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */
AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */
AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */
AM33XX_IOPAD(0x9b4, PIN_OUTPUT | MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */
AM33XX_IOPAD(0x880, PIN_OUTPUT | MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */
AM33XX_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */
>;
};
mmc0_pins_default: mmc0_pins_default {
pinctrl-single,pins = <
AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */
AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */
AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */
AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */
AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */
AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */
AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE5) /* (C15) spi0_cs1.mmc0_sdcd */
>;
};
i2c0_pins_default: i2c0_pins_default {
pinctrl-single,pins = <
AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */
AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */
>;
};
spi0_pins_default: spi0_pins_default {
pinctrl-single,pins = <
AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */
AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */
AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */
AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */
>;
};
uart3_pins_default: uart3_pins_default {
pinctrl-single,pins = <
AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */
AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLUP | MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */
>;
};
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_default>;
status = "okay";
clock-frequency = <400000>;
tps: power-controller@2d {
reg = <0x2d>;
};
tpic2810: gpio@60 {
compatible = "ti,tpic2810";
reg = <0x60>;
gpio-controller;
#gpio-cells = <2>;
};
};
#include "tps65910.dtsi"
&tps {
vcc1-supply = <&vbat>;
vcc2-supply = <&vbat>;
vcc3-supply = <&vbat>;
vcc4-supply = <&vbat>;
vcc5-supply = <&vbat>;
vcc6-supply = <&vbat>;
vcc7-supply = <&vbat>;
vccio-supply = <&vbat>;
regulators {
vrtc_reg: regulator@0 {
regulator-always-on;
};
vio_reg: regulator@1 {
regulator-always-on;
};
vdd1_reg: regulator@2 {
regulator-name = "vdd_mpu";
regulator-min-microvolt = <912500>;
regulator-max-microvolt = <1326000>;
regulator-boot-on;
regulator-always-on;
};
vdd2_reg: regulator@3 {
regulator-name = "vdd_core";
regulator-min-microvolt = <912500>;
regulator-max-microvolt = <1144000>;
regulator-boot-on;
regulator-always-on;
};
vdd3_reg: regulator@4 {
regulator-always-on;
};
vdig1_reg: regulator@5 {
regulator-always-on;
};
vdig2_reg: regulator@6 {
regulator-always-on;
};
vpll_reg: regulator@7 {
regulator-always-on;
};
vdac_reg: regulator@8 {
regulator-always-on;
};
vaux1_reg: regulator@9 {
regulator-always-on;
};
vaux2_reg: regulator@10 {
regulator-always-on;
};
vaux33_reg: regulator@11 {
regulator-always-on;
};
vmmc_reg: regulator@12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
&mmc1 {
status = "okay";
vmmc-supply = <&vmmc_reg>;
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_default>;
};
&gpio0 {
/* Do not idle the GPIO used for holding the VTT regulator */
ti,no-reset-on-init;
ti,no-idle-on-init;
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins_default>;
status = "okay";
};
arch/arm/boot/dts/am335x-igep0033.dtsi
View file @ 1ea7c8b6
......@@ -135,6 +135,7 @@ nand@0,0 {
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
nand-bus-width = <8>;
ti,nand-ecc-opt = "bch8";
gpmc,device-width = <1>;
......
arch/arm/boot/dts/am335x-phycore-som.dtsi
View file @ 1ea7c8b6
......@@ -171,6 +171,7 @@ nandflash: nand@0,0 {
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
nand-bus-width = <8>;
ti,nand-ecc-opt = "bch8";
gpmc,device-nand = "true";
......
arch/arm/boot/dts/am335x-shc.dts
View file @ 1ea7c8b6
......@@ -138,7 +138,7 @@ ethernetphy0: ethernet-phy@0 {
&epwmss1 {
status = "okay";
ehrpwm1: ehrpwm@48302200 {
ehrpwm1: pwm@48302200 {
pinctrl-names = "default";
pinctrl-0 = <&ehrpwm1_pins>;
status = "okay";
......
arch/arm/boot/dts/am33xx-clocks.dtsi
View file @ 1ea7c8b6
......@@ -8,7 +8,7 @@
* published by the Free Software Foundation.
*/
&scm_clocks {
sys_clkin_ck: sys_clkin_ck {
sys_clkin_ck: sys_clkin_ck@40 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
......@@ -163,7 +163,7 @@ tclkin_ck: tclkin_ck {
clock-frequency = <12000000>;
};
dpll_core_ck: dpll_core_ck {
dpll_core_ck: dpll_core_ck@490 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-core-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
......@@ -176,7 +176,7 @@ dpll_core_x2_ck: dpll_core_x2_ck {
clocks = <&dpll_core_ck>;
};
dpll_core_m4_ck: dpll_core_m4_ck {
dpll_core_m4_ck: dpll_core_m4_ck@480 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
......@@ -185,7 +185,7 @@ dpll_core_m4_ck: dpll_core_m4_ck {
ti,index-starts-at-one;
};
dpll_core_m5_ck: dpll_core_m5_ck {
dpll_core_m5_ck: dpll_core_m5_ck@484 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
......@@ -194,7 +194,7 @@ dpll_core_m5_ck: dpll_core_m5_ck {
ti,index-starts-at-one;
};
dpll_core_m6_ck: dpll_core_m6_ck {
dpll_core_m6_ck: dpll_core_m6_ck@4d8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
......@@ -203,14 +203,14 @@ dpll_core_m6_ck: dpll_core_m6_ck {
ti,index-starts-at-one;
};
dpll_mpu_ck: dpll_mpu_ck {
dpll_mpu_ck: dpll_mpu_ck@488 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0488>, <0x0420>, <0x042c>;
};
dpll_mpu_m2_ck: dpll_mpu_m2_ck {
dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_mpu_ck>;
......@@ -219,14 +219,14 @@ dpll_mpu_m2_ck: dpll_mpu_m2_ck {
ti,index-starts-at-one;
};
dpll_ddr_ck: dpll_ddr_ck {
dpll_ddr_ck: dpll_ddr_ck@494 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0494>, <0x0434>, <0x0440>;
};
dpll_ddr_m2_ck: dpll_ddr_m2_ck {
dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_ddr_ck>;
......@@ -243,14 +243,14 @@ dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
clock-div = <2>;
};
dpll_disp_ck: dpll_disp_ck {
dpll_disp_ck: dpll_disp_ck@498 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0498>, <0x0448>, <0x0454>;
};
dpll_disp_m2_ck: dpll_disp_m2_ck {
dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_disp_ck>;
......@@ -260,14 +260,14 @@ dpll_disp_m2_ck: dpll_disp_m2_ck {
ti,set-rate-parent;
};
dpll_per_ck: dpll_per_ck {
dpll_per_ck: dpll_per_ck@48c {
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-j-type-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x048c>, <0x0470>, <0x049c>;
};
dpll_per_m2_ck: dpll_per_m2_ck {
dpll_per_m2_ck: dpll_per_m2_ck@4ac {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_ck>;
......@@ -292,7 +292,7 @@ dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
clock-div = <4>;
};
cefuse_fck: cefuse_fck {
cefuse_fck: cefuse_fck@a20 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_clkin_ck>;
......@@ -316,7 +316,7 @@ clkdiv32k_ck: clkdiv32k_ck {
clock-div = <732>;
};
clkdiv32k_ick: clkdiv32k_ick {
clkdiv32k_ick: clkdiv32k_ick@14c {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ck>;
......@@ -332,14 +332,14 @@ l3_gclk: l3_gclk {
clock-div = <1>;
};
pruss_ocp_gclk: pruss_ocp_gclk {
pruss_ocp_gclk: pruss_ocp_gclk@530 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
reg = <0x0530>;
};
mmu_fck: mmu_fck {
mmu_fck: mmu_fck@914 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_core_m4_ck>;
......@@ -347,56 +347,56 @@ mmu_fck: mmu_fck {
reg = <0x0914>;
};
timer1_fck: timer1_fck {
timer1_fck: timer1_fck@528 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
reg = <0x0528>;
};
timer2_fck: timer2_fck {
timer2_fck: timer2_fck@508 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
reg = <0x0508>;
};
timer3_fck: timer3_fck {
timer3_fck: timer3_fck@50c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
reg = <0x050c>;
};
timer4_fck: timer4_fck {
timer4_fck: timer4_fck@510 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
reg = <0x0510>;
};
timer5_fck: timer5_fck {
timer5_fck: timer5_fck@518 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
reg = <0x0518>;
};
timer6_fck: timer6_fck {
timer6_fck: timer6_fck@51c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
reg = <0x051c>;
};
timer7_fck: timer7_fck {
timer7_fck: timer7_fck@504 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
reg = <0x0504>;
};
usbotg_fck: usbotg_fck {
usbotg_fck: usbotg_fck@47c {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_ck>;
......@@ -412,7 +412,7 @@ dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
clock-div = <2>;
};
ieee5000_fck: ieee5000_fck {
ieee5000_fck: ieee5000_fck@e4 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_core_m4_div2_ck>;
......@@ -420,7 +420,7 @@ ieee5000_fck: ieee5000_fck {
reg = <0x00e4>;
};
wdt1_fck: wdt1_fck {
wdt1_fck: wdt1_fck@538 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
......@@ -483,21 +483,21 @@ cpsw_125mhz_gclk: cpsw_125mhz_gclk {
clock-div = <2>;
};
cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
reg = <0x0520>;
};
gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>;
reg = <0x053c>;
};
gpio0_dbclk: gpio0_dbclk {
gpio0_dbclk: gpio0_dbclk@408 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&gpio0_dbclk_mux_ck>;
......@@ -505,7 +505,7 @@ gpio0_dbclk: gpio0_dbclk {
reg = <0x0408>;
};
gpio1_dbclk: gpio1_dbclk {
gpio1_dbclk: gpio1_dbclk@ac {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
......@@ -513,7 +513,7 @@ gpio1_dbclk: gpio1_dbclk {
reg = <0x00ac>;
};
gpio2_dbclk: gpio2_dbclk {
gpio2_dbclk: gpio2_dbclk@b0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
......@@ -521,7 +521,7 @@ gpio2_dbclk: gpio2_dbclk {
reg = <0x00b0>;
};
gpio3_dbclk: gpio3_dbclk {
gpio3_dbclk: gpio3_dbclk@b4 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
......@@ -529,7 +529,7 @@ gpio3_dbclk: gpio3_dbclk {
reg = <0x00b4>;
};
lcd_gclk: lcd_gclk {
lcd_gclk: lcd_gclk@534 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
......@@ -545,7 +545,7 @@ mmc_clk: mmc_clk {
clock-div = <2>;
};
gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@52c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
......@@ -553,7 +553,7 @@ gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
reg = <0x052c>;
};
gfx_fck_div_ck: gfx_fck_div_ck {
gfx_fck_div_ck: gfx_fck_div_ck@52c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&gfx_fclk_clksel_ck>;
......@@ -561,14 +561,14 @@ gfx_fck_div_ck: gfx_fck_div_ck {
ti,max-div = <2>;
};
sysclkout_pre_ck: sysclkout_pre_ck {
sysclkout_pre_ck: sysclkout_pre_ck@700 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
reg = <0x0700>;
};
clkout2_div_ck: clkout2_div_ck {
clkout2_div_ck: clkout2_div_ck@700 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sysclkout_pre_ck>;
......@@ -577,7 +577,7 @@ clkout2_div_ck: clkout2_div_ck {
reg = <0x0700>;
};
dbg_sysclk_ck: dbg_sysclk_ck {
dbg_sysclk_ck: dbg_sysclk_ck@414 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_clkin_ck>;
......@@ -585,7 +585,7 @@ dbg_sysclk_ck: dbg_sysclk_ck {
reg = <0x0414>;
};
dbg_clka_ck: dbg_clka_ck {
dbg_clka_ck: dbg_clka_ck@414 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_core_m4_ck>;
......@@ -593,7 +593,7 @@ dbg_clka_ck: dbg_clka_ck {
reg = <0x0414>;
};
stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck {
stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck@414 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
......@@ -601,7 +601,7 @@ stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck {
reg = <0x0414>;
};
trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck {
trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck@414 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
......@@ -609,7 +609,7 @@ trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck {
reg = <0x0414>;
};
stm_clk_div_ck: stm_clk_div_ck {
stm_clk_div_ck: stm_clk_div_ck@414 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&stm_pmd_clock_mux_ck>;
......@@ -619,7 +619,7 @@ stm_clk_div_ck: stm_clk_div_ck {
ti,index-power-of-two;
};
trace_clk_div_ck: trace_clk_div_ck {
trace_clk_div_ck: trace_clk_div_ck@414 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&trace_pmd_clk_mux_ck>;
......@@ -629,7 +629,7 @@ trace_clk_div_ck: trace_clk_div_ck {
ti,index-power-of-two;
};
clkout2_ck: clkout2_ck {
clkout2_ck: clkout2_ck@700 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkout2_div_ck>;
......
arch/arm/boot/dts/am33xx.dtsi
View file @ 1ea7c8b6
......@@ -688,7 +688,7 @@ ecap0: ecap@48300100 {
status = "disabled";
};
ehrpwm0: ehrpwm@48300200 {
ehrpwm0: pwm@48300200 {
compatible = "ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48300200 0x80>;
......@@ -718,7 +718,7 @@ ecap1: ecap@48302100 {
status = "disabled";
};
ehrpwm1: ehrpwm@48302200 {
ehrpwm1: pwm@48302200 {
compatible = "ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48302200 0x80>;
......@@ -748,7 +748,7 @@ ecap2: ecap@48304100 {
status = "disabled";
};
ehrpwm2: ehrpwm@48304200 {
ehrpwm2: pwm@48304200 {
compatible = "ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48304200 0x80>;
......@@ -868,6 +868,8 @@ gpmc: gpmc@50000000 {
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
......
arch/arm/boot/dts/am35xx-clocks.dtsi
View file @ 1ea7c8b6
......@@ -8,7 +8,7 @@
* published by the Free Software Foundation.
*/
&scm_clocks {
emac_ick: emac_ick {
emac_ick: emac_ick@32c {
#clock-cells = <0>;
compatible = "ti,am35xx-gate-clock";
clocks = <&ipss_ick>;
......@@ -16,7 +16,7 @@ emac_ick: emac_ick {
ti,bit-shift = <1>;
};
emac_fck: emac_fck {
emac_fck: emac_fck@32c {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&rmii_ck>;
......@@ -24,7 +24,7 @@ emac_fck: emac_fck {
ti,bit-shift = <9>;
};
vpfe_ick: vpfe_ick {
vpfe_ick: vpfe_ick@32c {
#clock-cells = <0>;
compatible = "ti,am35xx-gate-clock";
clocks = <&ipss_ick>;
......@@ -32,7 +32,7 @@ vpfe_ick: vpfe_ick {
ti,bit-shift = <2>;
};
vpfe_fck: vpfe_fck {
vpfe_fck: vpfe_fck@32c {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&pclk_ck>;
......@@ -40,7 +40,7 @@ vpfe_fck: vpfe_fck {
ti,bit-shift = <10>;
};
hsotgusb_ick_am35xx: hsotgusb_ick_am35xx {
hsotgusb_ick_am35xx: hsotgusb_ick_am35xx@32c {
#clock-cells = <0>;
compatible = "ti,am35xx-gate-clock";
clocks = <&ipss_ick>;
......@@ -48,7 +48,7 @@ hsotgusb_ick_am35xx: hsotgusb_ick_am35xx {
ti,bit-shift = <0>;
};
hsotgusb_fck_am35xx: hsotgusb_fck_am35xx {
hsotgusb_fck_am35xx: hsotgusb_fck_am35xx@32c {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_ck>;
......@@ -56,7 +56,7 @@ hsotgusb_fck_am35xx: hsotgusb_fck_am35xx {
ti,bit-shift = <8>;
};
hecc_ck: hecc_ck {
hecc_ck: hecc_ck@32c {
#clock-cells = <0>;
compatible = "ti,am35xx-gate-clock";
clocks = <&sys_ck>;
......@@ -65,7 +65,7 @@ hecc_ck: hecc_ck {
};
};
&cm_clocks {
ipss_ick: ipss_ick {
ipss_ick: ipss_ick@a10 {
#clock-cells = <0>;
compatible = "ti,am35xx-interface-clock";
clocks = <&core_l3_ick>;
......@@ -85,7 +85,7 @@ pclk_ck: pclk_ck {
clock-frequency = <27000000>;
};
uart4_ick_am35xx: uart4_ick_am35xx {
uart4_ick_am35xx: uart4_ick_am35xx@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -93,7 +93,7 @@ uart4_ick_am35xx: uart4_ick_am35xx {
ti,bit-shift = <23>;
};
uart4_fck_am35xx: uart4_fck_am35xx {
uart4_fck_am35xx: uart4_fck_am35xx@a00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_48m_fck>;
......
arch/arm/boot/dts/am4372.dtsi
View file @ 1ea7c8b6
......@@ -679,7 +679,7 @@ ecap0: ecap@48300100 {
status = "disabled";
};
ehrpwm0: ehrpwm@48300200 {
ehrpwm0: pwm@48300200 {
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48300200 0x80>;
......@@ -705,7 +705,7 @@ ecap1: ecap@48302100 {
status = "disabled";
};
ehrpwm1: ehrpwm@48302200 {
ehrpwm1: pwm@48302200 {
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48302200 0x80>;
......@@ -731,7 +731,7 @@ ecap2: ecap@48304100 {
status = "disabled";
};
ehrpwm2: ehrpwm@48304200 {
ehrpwm2: pwm@48304200 {
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48304200 0x80>;
......@@ -749,7 +749,7 @@ epwmss3: epwmss@48306000 {
ti,hwmods = "epwmss3";
status = "disabled";
ehrpwm3: ehrpwm@48306200 {
ehrpwm3: pwm@48306200 {
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48306200 0x80>;
......@@ -767,7 +767,7 @@ epwmss4: epwmss@48308000 {
ti,hwmods = "epwmss4";
status = "disabled";
ehrpwm4: ehrpwm@48308200 {
ehrpwm4: pwm@48308200 {
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48308200 0x80>;
......@@ -785,7 +785,7 @@ epwmss5: epwmss@4830a000 {
ti,hwmods = "epwmss5";
status = "disabled";
ehrpwm5: ehrpwm@4830a200 {
ehrpwm5: pwm@4830a200 {
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x4830a200 0x80>;
......@@ -896,6 +896,8 @@ gpmc: gpmc@50000000 {
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
......
arch/arm/boot/dts/am437x-gp-evm.dts
View file @ 1ea7c8b6
......@@ -119,7 +119,7 @@ clk_32k_rtc: clk_32k_rtc {
clock-frequency = <32768>;
};
sound0: sound@0 {
sound0: sound0 {
compatible = "simple-audio-card";
simple-audio-card,name = "AM437x-GP-EVM";
simple-audio-card,widgets =
......@@ -817,6 +817,7 @@ nand@0,0 {
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
ti,nand-ecc-opt = "bch16";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
......
arch/arm/boot/dts/am43x-epos-evm.dts
View file @ 1ea7c8b6
......@@ -107,7 +107,7 @@ backlight {
default-brightness-level = <8>;
};
sound0: sound@0 {
sound0: sound0 {
compatible = "simple-audio-card";
simple-audio-card,name = "AM43-EPOS-EVM";
simple-audio-card,widgets =
......@@ -568,6 +568,7 @@ nand@0,0 {
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
ti,nand-ecc-opt = "bch16";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
......
arch/arm/boot/dts/am43xx-clocks.dtsi
View file @ 1ea7c8b6
......@@ -8,7 +8,7 @@
* published by the Free Software Foundation.
*/
&scm_clocks {
sys_clkin_ck: sys_clkin_ck {
sys_clkin_ck: sys_clkin_ck@40 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
......@@ -16,7 +16,7 @@ sys_clkin_ck: sys_clkin_ck {
reg = <0x0040>;
};
crystal_freq_sel_ck: crystal_freq_sel_ck {
crystal_freq_sel_ck: crystal_freq_sel_ck@40 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
......@@ -104,7 +104,7 @@ aes0_fck: aes0_fck {
clock-div = <1>;
};
ehrpwm0_tbclk: ehrpwm0_tbclk {
ehrpwm0_tbclk: ehrpwm0_tbclk@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l4ls_gclk>;
......@@ -112,7 +112,7 @@ ehrpwm0_tbclk: ehrpwm0_tbclk {
reg = <0x0664>;
};
ehrpwm1_tbclk: ehrpwm1_tbclk {
ehrpwm1_tbclk: ehrpwm1_tbclk@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l4ls_gclk>;
......@@ -120,7 +120,7 @@ ehrpwm1_tbclk: ehrpwm1_tbclk {
reg = <0x0664>;
};
ehrpwm2_tbclk: ehrpwm2_tbclk {
ehrpwm2_tbclk: ehrpwm2_tbclk@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l4ls_gclk>;
......@@ -128,7 +128,7 @@ ehrpwm2_tbclk: ehrpwm2_tbclk {
reg = <0x0664>;
};
ehrpwm3_tbclk: ehrpwm3_tbclk {
ehrpwm3_tbclk: ehrpwm3_tbclk@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l4ls_gclk>;
......@@ -136,7 +136,7 @@ ehrpwm3_tbclk: ehrpwm3_tbclk {
reg = <0x0664>;
};
ehrpwm4_tbclk: ehrpwm4_tbclk {
ehrpwm4_tbclk: ehrpwm4_tbclk@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l4ls_gclk>;
......@@ -144,7 +144,7 @@ ehrpwm4_tbclk: ehrpwm4_tbclk {
reg = <0x0664>;
};
ehrpwm5_tbclk: ehrpwm5_tbclk {
ehrpwm5_tbclk: ehrpwm5_tbclk@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l4ls_gclk>;
......@@ -195,7 +195,7 @@ tclkin_ck: tclkin_ck {
clock-frequency = <26000000>;
};
dpll_core_ck: dpll_core_ck {
dpll_core_ck: dpll_core_ck@2d20 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-core-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
......@@ -208,7 +208,7 @@ dpll_core_x2_ck: dpll_core_x2_ck {
clocks = <&dpll_core_ck>;
};
dpll_core_m4_ck: dpll_core_m4_ck {
dpll_core_m4_ck: dpll_core_m4_ck@2d38 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
......@@ -219,7 +219,7 @@ dpll_core_m4_ck: dpll_core_m4_ck {
ti,invert-autoidle-bit;
};
dpll_core_m5_ck: dpll_core_m5_ck {
dpll_core_m5_ck: dpll_core_m5_ck@2d3c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
......@@ -230,7 +230,7 @@ dpll_core_m5_ck: dpll_core_m5_ck {
ti,invert-autoidle-bit;
};
dpll_core_m6_ck: dpll_core_m6_ck {
dpll_core_m6_ck: dpll_core_m6_ck@2d40 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
......@@ -241,14 +241,14 @@ dpll_core_m6_ck: dpll_core_m6_ck {
ti,invert-autoidle-bit;
};
dpll_mpu_ck: dpll_mpu_ck {
dpll_mpu_ck: dpll_mpu_ck@2d60 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2d60>, <0x2d64>, <0x2d6c>;
};
dpll_mpu_m2_ck: dpll_mpu_m2_ck {
dpll_mpu_m2_ck: dpll_mpu_m2_ck@2d70 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_mpu_ck>;
......@@ -267,14 +267,14 @@ mpu_periphclk: mpu_periphclk {
clock-div = <2>;
};
dpll_ddr_ck: dpll_ddr_ck {
dpll_ddr_ck: dpll_ddr_ck@2da0 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2da0>, <0x2da4>, <0x2dac>;
};
dpll_ddr_m2_ck: dpll_ddr_m2_ck {
dpll_ddr_m2_ck: dpll_ddr_m2_ck@2db0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_ddr_ck>;
......@@ -285,14 +285,14 @@ dpll_ddr_m2_ck: dpll_ddr_m2_ck {
ti,invert-autoidle-bit;
};
dpll_disp_ck: dpll_disp_ck {
dpll_disp_ck: dpll_disp_ck@2e20 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2e20>, <0x2e24>, <0x2e2c>;
};
dpll_disp_m2_ck: dpll_disp_m2_ck {
dpll_disp_m2_ck: dpll_disp_m2_ck@2e30 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_disp_ck>;
......@@ -304,14 +304,14 @@ dpll_disp_m2_ck: dpll_disp_m2_ck {
ti,set-rate-parent;
};
dpll_per_ck: dpll_per_ck {
dpll_per_ck: dpll_per_ck@2de0 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-j-type-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2de0>, <0x2de4>, <0x2dec>;
};
dpll_per_m2_ck: dpll_per_m2_ck {
dpll_per_m2_ck: dpll_per_m2_ck@2df0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_ck>;
......@@ -354,7 +354,7 @@ clkdiv32k_ck: clkdiv32k_ck {
clock-div = <732>;
};
clkdiv32k_ick: clkdiv32k_ick {
clkdiv32k_ick: clkdiv32k_ick@2a38 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ck>;
......@@ -370,7 +370,7 @@ sysclk_div: sysclk_div {
clock-div = <1>;
};
pruss_ocp_gclk: pruss_ocp_gclk {
pruss_ocp_gclk: pruss_ocp_gclk@4248 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
......@@ -383,56 +383,56 @@ clk_32k_tpm_ck: clk_32k_tpm_ck {
clock-frequency = <32768>;
};
timer1_fck: timer1_fck {
timer1_fck: timer1_fck@4200 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
reg = <0x4200>;
};
timer2_fck: timer2_fck {
timer2_fck: timer2_fck@4204 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
reg = <0x4204>;
};
timer3_fck: timer3_fck {
timer3_fck: timer3_fck@4208 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
reg = <0x4208>;
};
timer4_fck: timer4_fck {
timer4_fck: timer4_fck@420c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
reg = <0x420c>;
};
timer5_fck: timer5_fck {
timer5_fck: timer5_fck@4210 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
reg = <0x4210>;
};
timer6_fck: timer6_fck {
timer6_fck: timer6_fck@4214 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
reg = <0x4214>;
};
timer7_fck: timer7_fck {
timer7_fck: timer7_fck@4218 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
reg = <0x4218>;
};
wdt1_fck: wdt1_fck {
wdt1_fck: wdt1_fck@422c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
......@@ -487,14 +487,14 @@ cpsw_125mhz_gclk: cpsw_125mhz_gclk {
clock-div = <2>;
};
cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@4238 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
reg = <0x4238>;
};
dpll_clksel_mac_clk: dpll_clksel_mac_clk {
dpll_clksel_mac_clk: dpll_clksel_mac_clk@4234 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_m5_ck>;
......@@ -509,14 +509,14 @@ clk_32k_mosc_ck: clk_32k_mosc_ck {
clock-frequency = <32768>;
};
gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@4240 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
reg = <0x4240>;
};
gpio0_dbclk: gpio0_dbclk {
gpio0_dbclk: gpio0_dbclk@2b68 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&gpio0_dbclk_mux_ck>;
......@@ -524,7 +524,7 @@ gpio0_dbclk: gpio0_dbclk {
reg = <0x2b68>;
};
gpio1_dbclk: gpio1_dbclk {
gpio1_dbclk: gpio1_dbclk@8c78 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
......@@ -532,7 +532,7 @@ gpio1_dbclk: gpio1_dbclk {
reg = <0x8c78>;
};
gpio2_dbclk: gpio2_dbclk {
gpio2_dbclk: gpio2_dbclk@8c80 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
......@@ -540,7 +540,7 @@ gpio2_dbclk: gpio2_dbclk {
reg = <0x8c80>;
};
gpio3_dbclk: gpio3_dbclk {
gpio3_dbclk: gpio3_dbclk@8c88 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
......@@ -548,7 +548,7 @@ gpio3_dbclk: gpio3_dbclk {
reg = <0x8c88>;
};
gpio4_dbclk: gpio4_dbclk {
gpio4_dbclk: gpio4_dbclk@8c90 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
......@@ -556,7 +556,7 @@ gpio4_dbclk: gpio4_dbclk {
reg = <0x8c90>;
};
gpio5_dbclk: gpio5_dbclk {
gpio5_dbclk: gpio5_dbclk@8c98 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
......@@ -572,7 +572,7 @@ mmc_clk: mmc_clk {
clock-div = <2>;
};
gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@423c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
......@@ -580,7 +580,7 @@ gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
reg = <0x423c>;
};
gfx_fck_div_ck: gfx_fck_div_ck {
gfx_fck_div_ck: gfx_fck_div_ck@423c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&gfx_fclk_clksel_ck>;
......@@ -588,7 +588,7 @@ gfx_fck_div_ck: gfx_fck_div_ck {
ti,max-div = <2>;
};
disp_clk: disp_clk {
disp_clk: disp_clk@4244 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
......@@ -596,14 +596,14 @@ disp_clk: disp_clk {
ti,set-rate-parent;
};
dpll_extdev_ck: dpll_extdev_ck {
dpll_extdev_ck: dpll_extdev_ck@2e60 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x2e60>, <0x2e64>, <0x2e6c>;
};
dpll_extdev_m2_ck: dpll_extdev_m2_ck {
dpll_extdev_m2_ck: dpll_extdev_m2_ck@2e70 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_extdev_ck>;
......@@ -614,14 +614,14 @@ dpll_extdev_m2_ck: dpll_extdev_m2_ck {
ti,invert-autoidle-bit;
};
mux_synctimer32k_ck: mux_synctimer32k_ck {
mux_synctimer32k_ck: mux_synctimer32k_ck@4230 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
reg = <0x4230>;
};
synctimer_32kclk: synctimer_32kclk {
synctimer_32kclk: synctimer_32kclk@2a30 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&mux_synctimer32k_ck>;
......@@ -629,28 +629,28 @@ synctimer_32kclk: synctimer_32kclk {
reg = <0x2a30>;
};
timer8_fck: timer8_fck {
timer8_fck: timer8_fck@421c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
reg = <0x421c>;
};
timer9_fck: timer9_fck {
timer9_fck: timer9_fck@4220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
reg = <0x4220>;
};
timer10_fck: timer10_fck {
timer10_fck: timer10_fck@4224 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
reg = <0x4224>;
};
timer11_fck: timer11_fck {
timer11_fck: timer11_fck@4228 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
......@@ -679,7 +679,7 @@ dpll_ddr_x2_ck: dpll_ddr_x2_ck {
clocks = <&dpll_ddr_ck>;
};
dpll_ddr_m4_ck: dpll_ddr_m4_ck {
dpll_ddr_m4_ck: dpll_ddr_m4_ck@2db8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_ddr_x2_ck>;
......@@ -690,7 +690,7 @@ dpll_ddr_m4_ck: dpll_ddr_m4_ck {
ti,invert-autoidle-bit;
};
dpll_per_clkdcoldo: dpll_per_clkdcoldo {
dpll_per_clkdcoldo: dpll_per_clkdcoldo@2e14 {
#clock-cells = <0>;
compatible = "ti,fixed-factor-clock";
clocks = <&dpll_per_ck>;
......@@ -701,7 +701,7 @@ dpll_per_clkdcoldo: dpll_per_clkdcoldo {
ti,invert-autoidle-bit;
};
dll_aging_clk_div: dll_aging_clk_div {
dll_aging_clk_div: dll_aging_clk_div@4250 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin_ck>;
......@@ -733,14 +733,14 @@ vtp_clk_div: vtp_clk_div {
clock-div = <2>;
};
usbphy_32khz_clkmux: usbphy_32khz_clkmux {
usbphy_32khz_clkmux: usbphy_32khz_clkmux@4260 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
reg = <0x4260>;
};
usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k {
usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k@2a40 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&usbphy_32khz_clkmux>;
......@@ -748,7 +748,7 @@ usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k {
reg = <0x2a40>;
};
usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@2a48 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&usbphy_32khz_clkmux>;
......@@ -756,7 +756,7 @@ usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
reg = <0x2a48>;
};
usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m {
usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m@8a60 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_clkdcoldo>;
......@@ -764,11 +764,65 @@ usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m {
reg = <0x8a60>;
};
usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@8a68 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_clkdcoldo>;
ti,bit-shift = <8>;
reg = <0x8a68>;
};
clkout1_osc_div_ck: clkout1_osc_div_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin_ck>;
ti,bit-shift = <20>;
ti,max-div = <4>;
reg = <0x4100>;
};
clkout1_src2_mux_ck: clkout1_src2_mux_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
<&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
<&dpll_mpu_m2_ck>;
reg = <0x4100>;
};
clkout1_src2_pre_div_ck: clkout1_src2_pre_div_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&clkout1_src2_mux_ck>;
ti,bit-shift = <4>;
ti,max-div = <8>;
reg = <0x4100>;
};
clkout1_src2_post_div_ck: clkout1_src2_post_div_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&clkout1_src2_pre_div_ck>;
ti,bit-shift = <8>;
ti,max-div = <32>;
ti,index-power-of-two;
reg = <0x4100>;
};
clkout1_mux_ck: clkout1_mux_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>,
<&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>;
ti,bit-shift = <16>;
reg = <0x4100>;
};
clkout1_ck: clkout1_ck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkout1_mux_ck>;
ti,bit-shift = <23>;
reg = <0x4100>;
};
};
arch/arm/boot/dts/am572x-idk.dts 0 → 100644
View file @ 1ea7c8b6
/*
* Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "dra74x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "am57xx-idk-common.dtsi"
/ {
model = "TI AM5728 IDK";
compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74",
"ti,dra7";
memory {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
};
extcon_usb2: extcon_usb2 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
};
status-leds {
compatible = "gpio-leds";
cpu0-led {
label = "status0:red:cpu0";
gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "cpu0";
};
usr0-led {
label = "status0:green:usr";
gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
heartbeat-led {
label = "status0:blue:heartbeat";
gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "heartbeat";
};
cpu1-led {
label = "status1:red:cpu1";
gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "cpu1";
};
usr1-led {
label = "status1:green:usr";
gpios = <&gpio7 23 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
mmc0-led {
label = "status1:blue:mmc0";
gpios = <&gpio7 22 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "mmc0";
};
};
};
&omap_dwc3_2 {
extcon = <&extcon_usb2>;
};
&mmc1 {
status = "okay";
vmmc-supply = <&v3_3d>;
vmmc_aux-supply = <&ldo1_reg>;
bus-width = <4>;
cd-gpios = <&gpio6 27 0>; /* gpio 219 */
};
arch/arm/boot/dts/am57xx-beagle-x15.dts
View file @ 1ea7c8b6
......@@ -151,7 +151,7 @@ tpd12s015_out: endpoint {
};
};
sound0: sound@0 {
sound0: sound0 {
compatible = "simple-audio-card";
simple-audio-card,name = "BeagleBoard-X15";
simple-audio-card,widgets =
......@@ -173,8 +173,6 @@ simple-audio-card,cpu {
sound0_master: simple-audio-card,codec {
sound-dai = <&tlv320aic3104>;
assigned-clocks = <&clkoutmux2_clk_mux>;
assigned-clock-parents = <&sys_clk2_dclk_div>;
clocks = <&clkout2_clk>;
};
};
......@@ -584,6 +582,9 @@ tlv320aic3104: tlv320aic3104@18 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&clkout2_pins_default>;
pinctrl-1 = <&clkout2_pins_sleep>;
assigned-clocks = <&clkoutmux2_clk_mux>;
assigned-clock-parents = <&sys_clk2_dclk_div>;
status = "okay";
adc-settle-ms = <40>;
......@@ -812,6 +813,8 @@ &mcasp3 {
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1 2 0 0
>;
tx-num-evt = <32>;
rx-num-evt = <32>;
};
&mailbox5 {
......
arch/arm/boot/dts/am57xx-cl-som-am57x.dts
View file @ 1ea7c8b6
......@@ -51,7 +51,7 @@ ads7846reg: fixedregulator-ads7846-reg {
regulator-max-microvolt = <3300000>;
};
sound0: sound@0 {
sound0: sound0 {
compatible = "simple-audio-card";
simple-audio-card,name = "CL-SOM-AM57x-Sound-Card";
simple-audio-card,format = "i2s";
......
arch/arm/boot/dts/am57xx-idk-common.dtsi 0 → 100644
View file @ 1ea7c8b6
/*
* Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/ {
aliases {
rtc0 = &tps659038_rtc;
rtc1 = &rtc;
};
vmain: fixedregulator-vmain {
compatible = "regulator-fixed";
regulator-name = "VMAIN";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
v3_3d: fixedregulator-v3_3d {
compatible = "regulator-fixed";
regulator-name = "V3_3D";
vin-supply = <&smps9_reg>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
vtt_fixed: fixedregulator-vtt {
/* TPS51200 */
compatible = "regulator-fixed";
regulator-name = "vtt_fixed";
vin-supply = <&v3_3d>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
tps659038: tps659038@58 {
compatible = "ti,tps659038";
reg = <0x58>;
interrupts-extended = <&gpio6 16 IRQ_TYPE_LEVEL_HIGH
&dra7_pmx_core 0x418>;
#interrupt-cells = <2>;
interrupt-controller;
ti,system-power-controller;
tps659038_pmic {
compatible = "ti,tps659038-pmic";
regulators {
smps12_reg: smps12 {
/* VDD_MPU */
vin-supply = <&vmain>;
regulator-name = "smps12";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
smps3_reg: smps3 {
/* VDD_DDR EMIF1 EMIF2 */
vin-supply = <&vmain>;
regulator-name = "smps3";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
};
smps45_reg: smps45 {
/* VDD_DSPEVE on AM572 */
/* VDD_IVA + VDD_DSP on AM571 */
vin-supply = <&vmain>;
regulator-name = "smps45";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
smps6_reg: smps6 {
/* VDD_GPU */
vin-supply = <&vmain>;
regulator-name = "smps6";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
smps7_reg: smps7 {
/* VDD_CORE */
vin-supply = <&vmain>;
regulator-name = "smps7";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1150000>;
regulator-always-on;
regulator-boot-on;
};
smps8_reg: smps8 {
/* 5728 - VDD_IVAHD */
/* 5718 - N.C. test point */
vin-supply = <&vmain>;
regulator-name = "smps8";
};
smps9_reg: smps9 {
/* VDD_3_3D */
vin-supply = <&vmain>;
regulator-name = "smps9";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
ldo1_reg: ldo1 {
/* VDDSHV8 - VSDMMC */
/* NOTE: on rev 1.3a, data supply */
vin-supply = <&vmain>;
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: ldo2 {
/* VDDSH18V */
vin-supply = <&vmain>;
regulator-name = "ldo2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo3_reg: ldo3 {
/* R1.3a 572x V1_8PHY_LDO3: USB, SATA */
vin-supply = <&vmain>;
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo4_reg: ldo4 {
/* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/
vin-supply = <&vmain>;
regulator-name = "ldo4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
/* LDO5-8 unused */
ldo9_reg: ldo9 {
/* VDD_RTC */
vin-supply = <&vmain>;
regulator-name = "ldo9";
regulator-min-microvolt = <840000>;
regulator-max-microvolt = <1160000>;
regulator-always-on;
regulator-boot-on;
};
ldoln_reg: ldoln {
/* VDDA_1V8_PLL */
vin-supply = <&vmain>;
regulator-name = "ldoln";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldousb_reg: ldousb {
/* VDDA_3V_USB: VDDA_USBHS33 */
vin-supply = <&vmain>;
regulator-name = "ldousb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
ldortc_reg: ldortc {
/* VDDA_RTC */
vin-supply = <&vmain>;
regulator-name = "ldortc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
regen1: regen1 {
/* VDD_3V3_ON */
regulator-name = "regen1";
regulator-boot-on;
regulator-always-on;
};
regen2: regen2 {
/* Needed for PMIC internal resource */
regulator-name = "regen2";
regulator-boot-on;
regulator-always-on;
};
};
};
tps659038_rtc: tps659038_rtc {
compatible = "ti,palmas-rtc";
interrupt-parent = <&tps659038>;
interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
wakeup-source;
};
tps659038_pwr_button: tps659038_pwr_button {
compatible = "ti,palmas-pwrbutton";
interrupt-parent = <&tps659038>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
wakeup-source;
ti,palmas-long-press-seconds = <12>;
};
tps659038_gpio: tps659038_gpio {
compatible = "ti,palmas-gpio";
gpio-controller;
#gpio-cells = <2>;
};
};
};
&uart3 {
status = "okay";
interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH
&dra7_pmx_core 0x248>;
};
&rtc {
status = "okay";
ext-clk-src;
};
&mac {
status = "okay";
dual_emac;
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rgmii";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "rgmii";
dual_emac_res_vlan = <2>;
};
&usb2_phy1 {
phy-supply = <&ldousb_reg>;
};
&usb2_phy2 {
phy-supply = <&ldousb_reg>;
};
&usb1 {
dr_mode = "host";
};
&usb2 {
dr_mode = "otg";
};
&mmc2 {
status = "okay";
vmmc-supply = <&v3_3d>;
bus-width = <8>;
ti,non-removable;
max-frequency = <96000000>;
};
arch/arm/boot/dts/da850.dtsi
View file @ 1ea7c8b6
......@@ -261,13 +261,13 @@ mmc1: mmc@21b000 {
dma-names = "rx", "tx";
status = "disabled";
};
ehrpwm0: ehrpwm@300000 {
ehrpwm0: pwm@300000 {
compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x300000 0x2000>;
status = "disabled";
};
ehrpwm1: ehrpwm@302000 {
ehrpwm1: pwm@302000 {
compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x302000 0x2000>;
......
arch/arm/boot/dts/dm814x-clocks.dtsi
View file @ 1ea7c8b6
......@@ -5,7 +5,7 @@
*/
&pllss_clocks {
timer1_fck: timer1_fck {
timer1_fck: timer1_fck@2e0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
......@@ -14,7 +14,7 @@ timer1_fck: timer1_fck {
reg = <0x2e0>;
};
timer2_fck: timer2_fck {
timer2_fck: timer2_fck@2e0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
......@@ -23,7 +23,7 @@ timer2_fck: timer2_fck {
reg = <0x2e0>;
};
sysclk18_ck: sysclk18_ck {
sysclk18_ck: sysclk18_ck@2f0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&rtcosc_ck>, <&rtcdivider_ck>;
......@@ -33,7 +33,7 @@ sysclk18_ck: sysclk18_ck {
};
&scm_clocks {
devosc_ck: devosc_ck {
devosc_ck: devosc_ck@40 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&virt_20000000_ck>, <&virt_19200000_ck>;
......@@ -121,7 +121,7 @@ osc_src_ck: osc_src_ck {
clock-div = <1>;
};
mpu_clksrc_ck: mpu_clksrc_ck {
mpu_clksrc_ck: mpu_clksrc_ck@40 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&devosc_ck>, <&rtcdivider_ck>;
......
arch/arm/boot/dts/dm814x.dtsi
View file @ 1ea7c8b6
......@@ -568,6 +568,8 @@ gpmc: gpmc@50000000 {
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
};
};
};
......
arch/arm/boot/dts/dm816x-clocks.dtsi
View file @ 1ea7c8b6
......@@ -86,7 +86,7 @@ sys_clkin_ck: sys_clkin_ck {
/* 0x48180000 */
&prcm_clocks {
clkout_pre_ck: clkout_pre_ck {
clkout_pre_ck: clkout_pre_ck@100 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1
......@@ -94,7 +94,7 @@ clkout_pre_ck: clkout_pre_ck {
reg = <0x100>;
};
clkout_div_ck: clkout_div_ck {
clkout_div_ck: clkout_div_ck@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&clkout_pre_ck>;
......@@ -103,7 +103,7 @@ clkout_div_ck: clkout_div_ck {
reg = <0x100>;
};
clkout_ck: clkout_ck {
clkout_ck: clkout_ck@100 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkout_div_ck>;
......@@ -112,7 +112,7 @@ clkout_ck: clkout_ck {
};
/* CM_DPLL clocks p1795 */
sysclk1_ck: sysclk1_ck {
sysclk1_ck: sysclk1_ck@300 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&main_fapll 1>;
......@@ -120,7 +120,7 @@ sysclk1_ck: sysclk1_ck {
reg = <0x0300>;
};
sysclk2_ck: sysclk2_ck {
sysclk2_ck: sysclk2_ck@304 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&main_fapll 2>;
......@@ -128,7 +128,7 @@ sysclk2_ck: sysclk2_ck {
reg = <0x0304>;
};
sysclk3_ck: sysclk3_ck {
sysclk3_ck: sysclk3_ck@308 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&main_fapll 3>;
......@@ -136,7 +136,7 @@ sysclk3_ck: sysclk3_ck {
reg = <0x0308>;
};
sysclk4_ck: sysclk4_ck {
sysclk4_ck: sysclk4_ck@30c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&main_fapll 4>;
......@@ -144,7 +144,7 @@ sysclk4_ck: sysclk4_ck {
reg = <0x030c>;
};
sysclk5_ck: sysclk5_ck {
sysclk5_ck: sysclk5_ck@310 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sysclk4_ck>;
......@@ -152,7 +152,7 @@ sysclk5_ck: sysclk5_ck {
reg = <0x0310>;
};
sysclk6_ck: sysclk6_ck {
sysclk6_ck: sysclk6_ck@314 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&main_fapll 4>;
......@@ -160,7 +160,7 @@ sysclk6_ck: sysclk6_ck {
reg = <0x0314>;
};
sysclk10_ck: sysclk10_ck {
sysclk10_ck: sysclk10_ck@324 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&ddr_fapll 2>;
......@@ -168,7 +168,7 @@ sysclk10_ck: sysclk10_ck {
reg = <0x0324>;
};
sysclk24_ck: sysclk24_ck {
sysclk24_ck: sysclk24_ck@3b4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&main_fapll 5>;
......@@ -176,7 +176,7 @@ sysclk24_ck: sysclk24_ck {
reg = <0x03b4>;
};
mpu_ck: mpu_ck {
mpu_ck: mpu_ck@15dc {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sysclk2_ck>;
......@@ -184,7 +184,7 @@ mpu_ck: mpu_ck {
reg = <0x15dc>;
};
audio_pll_a_ck: audio_pll_a_ck {
audio_pll_a_ck: audio_pll_a_ck@35c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&audio_fapll 1>;
......@@ -192,56 +192,56 @@ audio_pll_a_ck: audio_pll_a_ck {
reg = <0x035c>;
};
sysclk18_ck: sysclk18_ck {
sysclk18_ck: sysclk18_ck@378 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_32k_ck>, <&audio_pll_a_ck>;
reg = <0x0378>;
};
timer1_fck: timer1_fck {
timer1_fck: timer1_fck@390 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
reg = <0x0390>;
};
timer2_fck: timer2_fck {
timer2_fck: timer2_fck@394 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
reg = <0x0394>;
};
timer3_fck: timer3_fck {
timer3_fck: timer3_fck@398 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
reg = <0x0398>;
};
timer4_fck: timer4_fck {
timer4_fck: timer4_fck@39c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
reg = <0x039c>;
};
timer5_fck: timer5_fck {
timer5_fck: timer5_fck@3a0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
reg = <0x03a0>;
};
timer6_fck: timer6_fck {
timer6_fck: timer6_fck@3a4 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
reg = <0x03a4>;
};
timer7_fck: timer7_fck {
timer7_fck: timer7_fck@3a8 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>;
......
arch/arm/boot/dts/dm816x.dtsi
View file @ 1ea7c8b6
......@@ -185,6 +185,8 @@ gpmc: gpmc@50000000 {
gpmc,num-waitpins = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
};
i2c1: i2c@48028000 {
......
arch/arm/boot/dts/dra7-evm.dts
View file @ 1ea7c8b6
......@@ -33,6 +33,7 @@ evm_3v3_sd: fixedregulator-sd {
evm_3v3_sw: fixedregulator-evm_3v3_sw {
compatible = "regulator-fixed";
regulator-name = "evm_3v3_sw";
vin-supply = <&sysen1>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
......@@ -64,10 +65,11 @@ vtt_fixed: fixedregulator-vtt {
regulator-always-on;
regulator-boot-on;
enable-active-high;
vin-supply = <&sysen2>;
gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
};
sound0: sound@0 {
sound0: sound0 {
compatible = "simple-audio-card";
simple-audio-card,name = "DRA7xx-EVM";
simple-audio-card,widgets =
......@@ -254,8 +256,9 @@ DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
nand_flash_x16: nand_flash_x16 {
/* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
* So NAND flash requires following switch settings:
* SW5.9 (GPMC_WPN) = LOW
* SW5.1 (NAND_BOOTn) = HIGH */
* SW5.1 (NAND_BOOTn) = ON (LOW)
* SW5.9 (GPMC_WPN) = OFF (HIGH)
*/
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
......@@ -523,6 +526,31 @@ ldousb_reg: ldousb {
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
/* REGEN1 is unused */
regen2: regen2 {
/* Needed for PMIC internal resources */
regulator-name = "regen2";
regulator-boot-on;
regulator-always-on;
};
/* REGEN3 is unused */
sysen1: sysen1 {
/* PMIC_REGEN_3V3 */
regulator-name = "sysen1";
regulator-boot-on;
regulator-always-on;
};
sysen2: sysen2 {
/* PMIC_REGEN_DDR */
regulator-name = "sysen2";
regulator-boot-on;
regulator-always-on;
};
};
};
};
......@@ -539,7 +567,7 @@ pcf_lcd: gpio@20 {
};
pcf_gpio_21: gpio@21 {
compatible = "ti,pcf8575";
compatible = "nxp,pcf8575";
reg = <0x21>;
lines-initial-states = <0x1408>;
gpio-controller;
......@@ -748,6 +776,7 @@ nand@0,0 {
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <16>;
......@@ -904,6 +933,8 @@ &mcasp3 {
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1 2 0 0
>;
tx-num-evt = <32>;
rx-num-evt = <32>;
};
&mailbox5 {
......
arch/arm/boot/dts/dra7.dtsi
View file @ 1ea7c8b6
......@@ -123,7 +123,7 @@ scm_conf: scm_conf@0 {
#size-cells = <1>;
ranges = <0 0x0 0x1400>;
pbias_regulator: pbias_regulator {
pbias_regulator: pbias_regulator@e00 {
compatible = "ti,pbias-dra7", "ti,pbias-omap";
reg = <0xe00 0x4>;
syscon = <&scm_conf>;
......@@ -161,6 +161,24 @@ scm_conf_pcie: scm_conf@1c24 {
compatible = "syscon";
reg = <0x1c24 0x0024>;
};
sdma_xbar: dma-router@b78 {
compatible = "ti,dra7-dma-crossbar";
reg = <0xb78 0xfc>;
#dma-cells = <1>;
dma-requests = <205>;
ti,dma-safe-map = <0>;
dma-masters = <&sdma>;
};
edma_xbar: dma-router@c78 {
compatible = "ti,dra7-dma-crossbar";
reg = <0xc78 0x7c>;
#dma-cells = <2>;
dma-requests = <204>;
ti,dma-safe-map = <0>;
dma-masters = <&edma>;
};
};
cm_core_aon: cm_core_aon@5000 {
......@@ -315,13 +333,43 @@ sdma: dma-controller@4a056000 {
dma-requests = <127>;
};
sdma_xbar: dma-router@4a002b78 {
compatible = "ti,dra7-dma-crossbar";
reg = <0x4a002b78 0xfc>;
#dma-cells = <1>;
dma-requests = <205>;
ti,dma-safe-map = <0>;
dma-masters = <&sdma>;
edma: edma@43300000 {
compatible = "ti,edma3-tpcc";
ti,hwmods = "tpcc";
reg = <0x43300000 0x100000>;
reg-names = "edma3_cc";
interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_ccint", "emda3_mperr",
"edma3_ccerrint";
dma-requests = <64>;
#dma-cells = <2>;
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
/*
* memcpy is disabled, can be enabled with:
* ti,edma-memcpy-channels = <20 21>;
* for example. Note that these channels need to be
* masked in the xbar as well.
*/
};
edma_tptc0: tptc@43400000 {
compatible = "ti,edma3-tptc";
ti,hwmods = "tptc0";
reg = <0x43400000 0x100000>;
interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_tcerrint";
};
edma_tptc1: tptc@43500000 {
compatible = "ti,edma3-tptc";
ti,hwmods = "tptc1";
reg = <0x43500000 0x100000>;
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_tcerrint";
};
gpio1: gpio@4ae10000 {
......@@ -773,12 +821,20 @@ timer11: timer@48088000 {
ti,hwmods = "timer11";
};
timer12: timer@4ae20000 {
compatible = "ti,omap5430-timer";
reg = <0x4ae20000 0x80>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer12";
ti,timer-alwon;
ti,timer-secure;
};
timer13: timer@48828000 {
compatible = "ti,omap5430-timer";
reg = <0x48828000 0x80>;
interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer13";
status = "disabled";
};
timer14: timer@4882a000 {
......@@ -786,7 +842,6 @@ timer14: timer@4882a000 {
reg = <0x4882a000 0x80>;
interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer14";
status = "disabled";
};
timer15: timer@4882c000 {
......@@ -794,7 +849,6 @@ timer15: timer@4882c000 {
reg = <0x4882c000 0x80>;
interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer15";
status = "disabled";
};
timer16: timer@4882e000 {
......@@ -802,7 +856,6 @@ timer16: timer@4882e000 {
reg = <0x4882e000 0x80>;
interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer16";
status = "disabled";
};
wdt2: wdt@4ae14000 {
......@@ -1404,6 +1457,8 @@ gpmc: gpmc@50000000 {
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
......@@ -1418,21 +1473,136 @@ atl: atl@4843c000 {
status = "disabled";
};
mcasp1: mcasp@48460000 {
compatible = "ti,dra7-mcasp-audio";
ti,hwmods = "mcasp1";
reg = <0x48460000 0x2000>,
<0x45800000 0x1000>;
reg-names = "mpu","dat";
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
dma-names = "tx", "rx";
clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>,
<&mcasp1_ahclkr_mux>;
clock-names = "fck", "ahclkx", "ahclkr";
status = "disabled";
};
mcasp2: mcasp@48464000 {
compatible = "ti,dra7-mcasp-audio";
ti,hwmods = "mcasp2";
reg = <0x48464000 0x2000>,
<0x45c00000 0x1000>;
reg-names = "mpu","dat";
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
dma-names = "tx", "rx";
clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>,
<&mcasp2_ahclkr_mux>;
clock-names = "fck", "ahclkx", "ahclkr";
status = "disabled";
};
mcasp3: mcasp@48468000 {
compatible = "ti,dra7-mcasp-audio";
ti,hwmods = "mcasp3";
reg = <0x48468000 0x2000>;
reg-names = "mpu";
reg = <0x48468000 0x2000>,
<0x46000000 0x1000>;
reg-names = "mpu","dat";
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
dmas = <&sdma_xbar 133>, <&sdma_xbar 132>;
dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
dma-names = "tx", "rx";
clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
mcasp4: mcasp@4846c000 {
compatible = "ti,dra7-mcasp-audio";
ti,hwmods = "mcasp4";
reg = <0x4846c000 0x2000>,
<0x48436000 0x1000>;
reg-names = "mpu","dat";
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
dma-names = "tx", "rx";
clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
mcasp5: mcasp@48470000 {
compatible = "ti,dra7-mcasp-audio";
ti,hwmods = "mcasp5";
reg = <0x48470000 0x2000>,
<0x4843a000 0x1000>;
reg-names = "mpu","dat";
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
dma-names = "tx", "rx";
clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
mcasp6: mcasp@48474000 {
compatible = "ti,dra7-mcasp-audio";
ti,hwmods = "mcasp6";
reg = <0x48474000 0x2000>,
<0x4844c000 0x1000>;
reg-names = "mpu","dat";
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
dma-names = "tx", "rx";
clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
mcasp7: mcasp@48478000 {
compatible = "ti,dra7-mcasp-audio";
ti,hwmods = "mcasp7";
reg = <0x48478000 0x2000>,
<0x48450000 0x1000>;
reg-names = "mpu","dat";
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
dma-names = "tx", "rx";
clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
mcasp8: mcasp@4847c000 {
compatible = "ti,dra7-mcasp-audio";
ti,hwmods = "mcasp8";
reg = <0x4847c000 0x2000>,
<0x48454000 0x1000>;
reg-names = "mpu","dat";
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
dma-names = "tx", "rx";
clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
crossbar_mpu: crossbar@4a002a48 {
compatible = "ti,irq-crossbar";
reg = <0x4a002a48 0x130>;
......
arch/arm/boot/dts/dra72-evm-common.dtsi 0 → 100644
View file @ 1ea7c8b6
/*
* Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "dra72x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clk/ti-dra7-atl.h>
/ {
compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
aliases {
display0 = &hdmi0;
};
evm_3v3: fixedregulator-evm_3v3 {
compatible = "regulator-fixed";
regulator-name = "evm_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
aic_dvdd: fixedregulator-aic_dvdd {
/* TPS77018DBVT */
compatible = "regulator-fixed";
regulator-name = "aic_dvdd";
vin-supply = <&evm_3v3>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
evm_3v3_sd: fixedregulator-sd {
compatible = "regulator-fixed";
regulator-name = "evm_3v3_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
};
extcon_usb1: extcon_usb1 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
};
extcon_usb2: extcon_usb2 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
};
hdmi0: connector {
compatible = "hdmi-connector";
label = "hdmi";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&tpd12s015_out>;
};
};
};
tpd12s015: encoder {
compatible = "ti,tpd12s015";
pinctrl-names = "default";
pinctrl-0 = <&tpd12s015_pins>;
gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
<&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
<&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tpd12s015_in: endpoint {
remote-endpoint = <&hdmi_out>;
};
};
port@1 {
reg = <1>;
tpd12s015_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
sound0: sound0 {
compatible = "simple-audio-card";
simple-audio-card,name = "DRA7xx-EVM";
simple-audio-card,widgets =
"Headphone", "Headphone Jack",
"Line", "Line Out",
"Microphone", "Mic Jack",
"Line", "Line In";
simple-audio-card,routing =
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT",
"Line Out", "LLOUT",
"Line Out", "RLOUT",
"MIC3L", "Mic Jack",
"MIC3R", "Mic Jack",
"Mic Jack", "Mic Bias",
"LINE1L", "Line In",
"LINE1R", "Line In";
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-master = <&sound0_master>;
simple-audio-card,frame-master = <&sound0_master>;
simple-audio-card,bitclock-inversion;
sound0_master: simple-audio-card,cpu {
sound-dai = <&mcasp3>;
system-clock-frequency = <5644800>;
};
simple-audio-card,codec {
sound-dai = <&tlv320aic3106>;
clocks = <&atl_clkin2_ck>;
};
};
};
&dra7_pmx_core {
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
>;
};
i2c5_pins: pinmux_i2c5_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
>;
};
i2c5_pins: pinmux_i2c5_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
>;
};
nand_default: nand_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */
>;
};
usb1_pins: pinmux_usb1_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
>;
};
usb2_pins: pinmux_usb2_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
>;
};
tps65917_pins_default: tps65917_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3824, PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
>;
};
mmc1_pins_default: mmc1_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc2_pins_default: mmc2_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
dcan1_pins_default: dcan1_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
>;
};
dcan1_pins_sleep: dcan1_pins_sleep {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
>;
};
qspi1_pins: pinmux_qspi1_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3474, PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
DRA7XX_CORE_IOPAD(0x3478, PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
DRA7XX_CORE_IOPAD(0x347c, PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
DRA7XX_CORE_IOPAD(0x3488, PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
DRA7XX_CORE_IOPAD(0x34b8, PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
>;
};
hdmi_pins: pinmux_hdmi_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
>;
};
tpd12s015_pins: pinmux_tpd12s015_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
>;
};
atl_pins: pinmux_atl_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */
DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */
>;
};
mcasp3_pins: pinmux_mcasp3_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */
>;
};
mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT_PULLDOWN | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE15)
>;
};
};
&i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
tps65917: tps65917@58 {
compatible = "ti,tps65917";
reg = <0x58>;
pinctrl-names = "default";
pinctrl-0 = <&tps65917_pins_default>;
interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
interrupt-controller;
#interrupt-cells = <2>;
ti,system-power-controller;
tps65917_pmic {
compatible = "ti,tps65917-pmic";
tps65917_regulators: regulators {
smps1_reg: smps1 {
/* VDD_MPU */
regulator-name = "smps1";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
smps2_reg: smps2 {
/* VDD_CORE */
regulator-name = "smps2";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1060000>;
regulator-boot-on;
regulator-always-on;
};
smps3_reg: smps3 {
/* VDD_GPU IVA DSPEVE */
regulator-name = "smps3";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-boot-on;
regulator-always-on;
};
smps4_reg: smps4 {
/* VDDS1V8 */
regulator-name = "smps4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
smps5_reg: smps5 {
/* VDD_DDR */
regulator-name = "smps5";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: ldo1 {
/* LDO1_OUT --> SDIO */
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-allow-bypass;
};
ldo3_reg: ldo3 {
/* VDDA_1V8_PHY */
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo5_reg: ldo5 {
/* VDDA_1V8_PLL */
regulator-name = "ldo5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo4_reg: ldo4 {
/* VDDA_3V_USB: VDDA_USBHS33 */
regulator-name = "ldo4";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
};
};
tps65917_power_button {
compatible = "ti,palmas-pwrbutton";
interrupt-parent = <&tps65917>;
interrupts = <1 IRQ_TYPE_NONE>;
wakeup-source;
ti,palmas-long-press-seconds = <6>;
};
};
pcf_gpio_21: gpio@21 {
compatible = "nxp,pcf8575";
reg = <0x21>;
lines-initial-states = <0x1408>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
tlv320aic3106: tlv320aic3106@19 {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic3106";
reg = <0x19>;
adc-settle-ms = <40>;
ai3x-micbias-vg = <1>; /* 2.0V */
status = "okay";
/* Regulators */
AVDD-supply = <&evm_3v3>;
IOVDD-supply = <&evm_3v3>;
DRVDD-supply = <&evm_3v3>;
DVDD-supply = <&aic_dvdd>;
};
};
&i2c5 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins>;
clock-frequency = <400000>;
pcf_hdmi: pcf8575@26 {
compatible = "nxp,pcf8575";
reg = <0x26>;
gpio-controller;
#gpio-cells = <2>;
/*
* initial state is used here to keep the mdio interface
* selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
* VIN2_S0 driven high otherwise Ethernet stops working
* VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
*/
lines-initial-states = <0x0f2b>;
p1 {
/* vin6_sel_s0: high: VIN6, low: audio */
gpio-hog;
gpios = <1 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "vin6_sel_s0";
};
};
};
&uart1 {
status = "okay";
interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<&dra7_pmx_core 0x3e0>;
};
&elm {
status = "okay";
};
&gpmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nand_default>;
ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
nand@0,0 {
/* To use NAND, DIP switch SW5 must be set like so:
* SW5.1 (NAND_SELn) = ON (LOW)
* SW5.9 (GPMC_WPN) = OFF (HIGH)
*/
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* device IO registers */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <16>;
gpmc,device-width = <2>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <80>;
gpmc,cs-wr-off-ns = <80>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <60>;
gpmc,adv-wr-off-ns = <60>;
gpmc,we-on-ns = <10>;
gpmc,we-off-ns = <50>;
gpmc,oe-on-ns = <4>;
gpmc,oe-off-ns = <40>;
gpmc,access-ns = <40>;
gpmc,wr-access-ns = <80>;
gpmc,rd-cycle-ns = <80>;
gpmc,wr-cycle-ns = <80>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
* which can be independently programmable. For
* NAND flash this is equal to size of erase-block */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x000020000>;
};
partition@1 {
label = "NAND.SPL.backup1";
reg = <0x00020000 0x00020000>;
};
partition@2 {
label = "NAND.SPL.backup2";
reg = <0x00040000 0x00020000>;
};
partition@3 {
label = "NAND.SPL.backup3";
reg = <0x00060000 0x00020000>;
};
partition@4 {
label = "NAND.u-boot-spl-os";
reg = <0x00080000 0x00040000>;
};
partition@5 {
label = "NAND.u-boot";
reg = <0x000c0000 0x00100000>;
};
partition@6 {
label = "NAND.u-boot-env";
reg = <0x001c0000 0x00020000>;
};
partition@7 {
label = "NAND.u-boot-env.backup1";
reg = <0x001e0000 0x00020000>;
};
partition@8 {
label = "NAND.kernel";
reg = <0x00200000 0x00800000>;
};
partition@9 {
label = "NAND.file-system";
reg = <0x00a00000 0x0f600000>;
};
};
};
&usb2_phy1 {
phy-supply = <&ldo4_reg>;
};
&usb2_phy2 {
phy-supply = <&ldo4_reg>;
};
&omap_dwc3_1 {
extcon = <&extcon_usb1>;
};
&omap_dwc3_2 {
extcon = <&extcon_usb2>;
};
&usb1 {
dr_mode = "peripheral";
pinctrl-names = "default";
pinctrl-0 = <&usb1_pins>;
};
&usb2 {
dr_mode = "host";
pinctrl-names = "default";
pinctrl-0 = <&usb2_pins>;
};
&mmc1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_default>;
vmmc-supply = <&evm_3v3_sd>;
vmmc_aux-supply = <&ldo1_reg>;
bus-width = <4>;
/*
* SDCD signal is not being used here - using the fact that GPIO mode
* is a viable alternative
*/
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
max-frequency = <192000000>;
};
&mmc2 {
/* SW5-3 in ON position */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins_default>;
vmmc-supply = <&evm_3v3>;
bus-width = <8>;
ti,non-removable;
max-frequency = <192000000>;
};
&dra7_pmx_core {
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 2 */
DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 2 */
DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15)
>;
};
};
&mac {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
};
&dcan1 {
status = "ok";
pinctrl-names = "default", "sleep", "active";
pinctrl-0 = <&dcan1_pins_sleep>;
pinctrl-1 = <&dcan1_pins_sleep>;
pinctrl-2 = <&dcan1_pins_default>;
};
&qspi {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&qspi1_pins>;
spi-max-frequency = <48000000>;
m25p80@0 {
compatible = "s25fl256s1";
spi-max-frequency = <48000000>;
reg = <0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-cpol;
spi-cpha;
#address-cells = <1>;
#size-cells = <1>;
/* MTD partition table.
* The ROM checks the first four physical blocks
* for a valid file to boot and the flash here is
* 64KiB block size.
*/
partition@0 {
label = "QSPI.SPL";
reg = <0x00000000 0x000010000>;
};
partition@1 {
label = "QSPI.SPL.backup1";
reg = <0x00010000 0x00010000>;
};
partition@2 {
label = "QSPI.SPL.backup2";
reg = <0x00020000 0x00010000>;
};
partition@3 {
label = "QSPI.SPL.backup3";
reg = <0x00030000 0x00010000>;
};
partition@4 {
label = "QSPI.u-boot";
reg = <0x00040000 0x00100000>;
};
partition@5 {
label = "QSPI.u-boot-spl-os";
reg = <0x00140000 0x00080000>;
};
partition@6 {
label = "QSPI.u-boot-env";
reg = <0x001c0000 0x00010000>;
};
partition@7 {
label = "QSPI.u-boot-env.backup1";
reg = <0x001d0000 0x0010000>;
};
partition@8 {
label = "QSPI.kernel";
reg = <0x001e0000 0x0800000>;
};
partition@9 {
label = "QSPI.file-system";
reg = <0x009e0000 0x01620000>;
};
};
};
&dss {
status = "ok";
vdda_video-supply = <&ldo5_reg>;
};
&hdmi {
status = "ok";
pinctrl-names = "default";
pinctrl-0 = <&hdmi_pins>;
port {
hdmi_out: endpoint {
remote-endpoint = <&tpd12s015_in>;
};
};
};
&atl {
pinctrl-names = "default";
pinctrl-0 = <&atl_pins>;
assigned-clocks = <&abe_dpll_sys_clk_mux>,
<&atl_gfclk_mux>,
<&dpll_abe_ck>,
<&dpll_abe_m2x2_ck>,
<&atl_clkin2_ck>;
assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
status = "okay";
atl2 {
bws = <DRA7_ATL_WS_MCASP2_FSX>;
aws = <DRA7_ATL_WS_MCASP3_FSX>;
};
};
&mcasp3 {
#sound-dai-cells = <0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mcasp3_pins>;
pinctrl-1 = <&mcasp3_sleep_pins>;
assigned-clocks = <&mcasp3_ahclkx_mux>;
assigned-clock-parents = <&atl_clkin2_ck>;
status = "okay";
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
/* 4 serializer */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1 2 0 0
>;
tx-num-evt = <32>;
rx-num-evt = <32>;
};
&mailbox5 {
status = "okay";
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
status = "okay";
};
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
status = "okay";
};
};
&mailbox6 {
status = "okay";
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
status = "okay";
};
};
arch/arm/boot/dts/dra72-evm-revc.dts 0 → 100644
View file @ 1ea7c8b6
/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "dra72-evm-common.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
/ {
model = "TI DRA722 Rev C EVM";
memory {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
};
};
&tps65917_regulators {
ldo2_reg: ldo2 {
/* LDO2_OUT --> VDDA_1V8_PHY2 */
regulator-name = "ldo2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
};
&hdmi {
vdda-supply = <&ldo2_reg>;
};
&pcf_gpio_21 {
interrupt-parent = <&gpio3>;
interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
};
&mac {
mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>,
<&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */
<&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */
dual_emac;
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <2>;
phy-mode = "rgmii-id";
dual_emac_res_vlan = <1>;
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <3>;
phy-mode = "rgmii-id";
dual_emac_res_vlan = <2>;
};
&davinci_mdio {
dp83867_0: ethernet-phy@2 {
reg = <2>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
};
dp83867_1: ethernet-phy@3 {
reg = <3>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
};
};
arch/arm/boot/dts/dra72-evm.dts
View file @ 1ea7c8b6
/*
* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "dra72x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clk/ti-dra7-atl.h>
#include "dra72-evm-common.dtsi"
/ {
model = "TI DRA722";
compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
memory {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */
};
};
aliases {
display0 = &hdmi0;
};
evm_3v3: fixedregulator-evm_3v3 {
compatible = "regulator-fixed";
regulator-name = "evm_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
aic_dvdd: fixedregulator-aic_dvdd {
/* TPS77018DBVT */
compatible = "regulator-fixed";
regulator-name = "aic_dvdd";
vin-supply = <&evm_3v3>;
&tps65917_regulators {
ldo2_reg: ldo2 {
/* LDO2_OUT --> TP1017 (UNUSED) */
regulator-name = "ldo2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
evm_3v3_sd: fixedregulator-sd {
compatible = "regulator-fixed";
regulator-name = "evm_3v3_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
};
extcon_usb1: extcon_usb1 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
};
extcon_usb2: extcon_usb2 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
};
hdmi0: connector {
compatible = "hdmi-connector";
label = "hdmi";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&tpd12s015_out>;
};
};
};
tpd12s015: encoder {
compatible = "ti,tpd12s015";
pinctrl-names = "default";
pinctrl-0 = <&tpd12s015_pins>;
gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
<&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
<&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tpd12s015_in: endpoint {
remote-endpoint = <&hdmi_out>;
};
};
port@1 {
reg = <1>;
tpd12s015_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
sound0: sound@0 {
compatible = "simple-audio-card";
simple-audio-card,name = "DRA7xx-EVM";
simple-audio-card,widgets =
"Headphone", "Headphone Jack",
"Line", "Line Out",
"Microphone", "Mic Jack",
"Line", "Line In";
simple-audio-card,routing =
"Headphone Jack", "HPLOUT",
"Headphone Jack", "HPROUT",
"Line Out", "LLOUT",
"Line Out", "RLOUT",
"MIC3L", "Mic Jack",
"MIC3R", "Mic Jack",
"Mic Jack", "Mic Bias",
"LINE1L", "Line In",
"LINE1R", "Line In";
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-master = <&sound0_master>;
simple-audio-card,frame-master = <&sound0_master>;
simple-audio-card,bitclock-inversion;
sound0_master: simple-audio-card,cpu {
sound-dai = <&mcasp3>;
system-clock-frequency = <5644800>;
};
simple-audio-card,codec {
sound-dai = <&tlv320aic3106>;
clocks = <&atl_clkin2_ck>;
};
};
};
&dra7_pmx_core {
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
>;
};
i2c5_pins: pinmux_i2c5_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
>;
};
i2c5_pins: pinmux_i2c5_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */
DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */
>;
};
nand_default: nand_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */
>;
};
usb1_pins: pinmux_usb1_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
>;
};
usb2_pins: pinmux_usb2_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
>;
};
tps65917_pins_default: tps65917_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3824, PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
>;
};
mmc1_pins_default: mmc1_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
>;
};
mmc2_pins_default: mmc2_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
>;
};
dcan1_pins_default: dcan1_pins_default {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
>;
};
dcan1_pins_sleep: dcan1_pins_sleep {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
>;
};
qspi1_pins: pinmux_qspi1_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3474, PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
DRA7XX_CORE_IOPAD(0x3478, PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
DRA7XX_CORE_IOPAD(0x347c, PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
DRA7XX_CORE_IOPAD(0x3488, PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
DRA7XX_CORE_IOPAD(0x34b8, PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
>;
};
hdmi_pins: pinmux_hdmi_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */
DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */
>;
};
tpd12s015_pins: pinmux_tpd12s015_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */
>;
};
atl_pins: pinmux_atl_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */
DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */
>;
};
mcasp3_pins: pinmux_mcasp3_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */
>;
};
mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT_PULLDOWN | MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE15)
>;
};
};
&i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
tps65917: tps65917@58 {
compatible = "ti,tps65917";
reg = <0x58>;
pinctrl-names = "default";
pinctrl-0 = <&tps65917_pins_default>;
interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
interrupt-controller;
#interrupt-cells = <2>;
ti,system-power-controller;
tps65917_pmic {
compatible = "ti,tps65917-pmic";
regulators {
smps1_reg: smps1 {
/* VDD_MPU */
regulator-name = "smps1";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
smps2_reg: smps2 {
/* VDD_CORE */
regulator-name = "smps2";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1060000>;
regulator-boot-on;
regulator-always-on;
};
smps3_reg: smps3 {
/* VDD_GPU IVA DSPEVE */
regulator-name = "smps3";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-boot-on;
regulator-always-on;
};
smps4_reg: smps4 {
/* VDDS1V8 */
regulator-name = "smps4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
smps5_reg: smps5 {
/* VDD_DDR */
regulator-name = "smps5";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: ldo1 {
/* LDO1_OUT --> SDIO */
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-allow-bypass;
};
ldo2_reg: ldo2 {
/* LDO2_OUT --> TP1017 (UNUSED) */
regulator-name = "ldo2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-allow-bypass;
};
ldo3_reg: ldo3 {
/* VDDA_1V8_PHY */
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo5_reg: ldo5 {
/* VDDA_1V8_PLL */
regulator-name = "ldo5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo4_reg: ldo4 {
/* VDDA_3V_USB: VDDA_USBHS33 */
regulator-name = "ldo4";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
};
};
tps65917_power_button {
compatible = "ti,palmas-pwrbutton";
interrupt-parent = <&tps65917>;
interrupts = <1 IRQ_TYPE_NONE>;
wakeup-source;
ti,palmas-long-press-seconds = <6>;
};
};
pcf_gpio_21: gpio@21 {
compatible = "ti,pcf8575";
reg = <0x21>;
lines-initial-states = <0x1408>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio6>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
};
tlv320aic3106: tlv320aic3106@19 {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic3106";
reg = <0x19>;
adc-settle-ms = <40>;
ai3x-micbias-vg = <1>; /* 2.0V */
status = "okay";
/* Regulators */
AVDD-supply = <&evm_3v3>;
IOVDD-supply = <&evm_3v3>;
DRVDD-supply = <&evm_3v3>;
DVDD-supply = <&aic_dvdd>;
regulator-allow-bypass;
};
};
&i2c5 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins>;
clock-frequency = <400000>;
pcf_hdmi: pcf8575@26 {
compatible = "nxp,pcf8575";
reg = <0x26>;
gpio-controller;
#gpio-cells = <2>;
/*
* initial state is used here to keep the mdio interface
* selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
* VIN2_S0 driven high otherwise Ethernet stops working
* VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
*/
lines-initial-states = <0x0f2b>;
p1 {
/* vin6_sel_s0: high: VIN6, low: audio */
gpio-hog;
gpios = <1 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "vin6_sel_s0";
};
};
};
&uart1 {
status = "okay";
interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<&dra7_pmx_core 0x3e0>;
};
&elm {
status = "okay";
};
&gpmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nand_default>;
ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
nand@0,0 {
/* To use NAND, DIP switch SW5 must be set like so:
* SW5.1 (NAND_SELn) = ON (LOW)
* SW5.9 (GPMC_WPN) = OFF (HIGH)
*/
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* device IO registers */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <16>;
gpmc,device-width = <2>;
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <80>;
gpmc,cs-wr-off-ns = <80>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <60>;
gpmc,adv-wr-off-ns = <60>;
gpmc,we-on-ns = <10>;
gpmc,we-off-ns = <50>;
gpmc,oe-on-ns = <4>;
gpmc,oe-off-ns = <40>;
gpmc,access-ns = <40>;
gpmc,wr-access-ns = <80>;
gpmc,rd-cycle-ns = <80>;
gpmc,wr-cycle-ns = <80>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
* which can be independently programmable. For
* NAND flash this is equal to size of erase-block */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x000020000>;
};
partition@1 {
label = "NAND.SPL.backup1";
reg = <0x00020000 0x00020000>;
};
partition@2 {
label = "NAND.SPL.backup2";
reg = <0x00040000 0x00020000>;
};
partition@3 {
label = "NAND.SPL.backup3";
reg = <0x00060000 0x00020000>;
};
partition@4 {
label = "NAND.u-boot-spl-os";
reg = <0x00080000 0x00040000>;
};
partition@5 {
label = "NAND.u-boot";
reg = <0x000c0000 0x00100000>;
};
partition@6 {
label = "NAND.u-boot-env";
reg = <0x001c0000 0x00020000>;
};
partition@7 {
label = "NAND.u-boot-env.backup1";
reg = <0x001e0000 0x00020000>;
};
partition@8 {
label = "NAND.kernel";
reg = <0x00200000 0x00800000>;
};
partition@9 {
label = "NAND.file-system";
reg = <0x00a00000 0x0f600000>;
};
};
};
&usb2_phy1 {
phy-supply = <&ldo4_reg>;
};
&usb2_phy2 {
phy-supply = <&ldo4_reg>;
};
&omap_dwc3_1 {
extcon = <&extcon_usb1>;
};
&omap_dwc3_2 {
extcon = <&extcon_usb2>;
};
&usb1 {
dr_mode = "peripheral";
pinctrl-names = "default";
pinctrl-0 = <&usb1_pins>;
};
&usb2 {
dr_mode = "host";
pinctrl-names = "default";
pinctrl-0 = <&usb2_pins>;
};
&mmc1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_default>;
vmmc-supply = <&evm_3v3_sd>;
vmmc_aux-supply = <&ldo1_reg>;
bus-width = <4>;
/*
* SDCD signal is not being used here - using the fact that GPIO mode
* is a viable alternative
*/
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
max-frequency = <192000000>;
};
&mmc2 {
/* SW5-3 in ON position */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins_default>;
vmmc-supply = <&evm_3v3>;
bus-width = <8>;
ti,non-removable;
max-frequency = <192000000>;
&hdmi {
vdda-supply = <&ldo3_reg>;
};
&dra7_pmx_core {
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 2 */
DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 2 */
DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15)
DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15)
>;
};
&pcf_gpio_21 {
interrupt-parent = <&gpio6>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
};
&mac {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
slaves = <1>;
mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>;
};
......@@ -697,158 +43,3 @@ &cpsw_emac0 {
phy_id = <&davinci_mdio>, <3>;
phy-mode = "rgmii";
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
};
&dcan1 {
status = "ok";
pinctrl-names = "default", "sleep", "active";
pinctrl-0 = <&dcan1_pins_sleep>;
pinctrl-1 = <&dcan1_pins_sleep>;
pinctrl-2 = <&dcan1_pins_default>;
};
&qspi {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&qspi1_pins>;
spi-max-frequency = <48000000>;
m25p80@0 {
compatible = "s25fl256s1";
spi-max-frequency = <48000000>;
reg = <0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-cpol;
spi-cpha;
#address-cells = <1>;
#size-cells = <1>;
/* MTD partition table.
* The ROM checks the first four physical blocks
* for a valid file to boot and the flash here is
* 64KiB block size.
*/
partition@0 {
label = "QSPI.SPL";
reg = <0x00000000 0x000010000>;
};
partition@1 {
label = "QSPI.SPL.backup1";
reg = <0x00010000 0x00010000>;
};
partition@2 {
label = "QSPI.SPL.backup2";
reg = <0x00020000 0x00010000>;
};
partition@3 {
label = "QSPI.SPL.backup3";
reg = <0x00030000 0x00010000>;
};
partition@4 {
label = "QSPI.u-boot";
reg = <0x00040000 0x00100000>;
};
partition@5 {
label = "QSPI.u-boot-spl-os";
reg = <0x00140000 0x00080000>;
};
partition@6 {
label = "QSPI.u-boot-env";
reg = <0x001c0000 0x00010000>;
};
partition@7 {
label = "QSPI.u-boot-env.backup1";
reg = <0x001d0000 0x0010000>;
};
partition@8 {
label = "QSPI.kernel";
reg = <0x001e0000 0x0800000>;
};
partition@9 {
label = "QSPI.file-system";
reg = <0x009e0000 0x01620000>;
};
};
};
&dss {
status = "ok";
vdda_video-supply = <&ldo5_reg>;
};
&hdmi {
status = "ok";
vdda-supply = <&ldo3_reg>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_pins>;
port {
hdmi_out: endpoint {
remote-endpoint = <&tpd12s015_in>;
};
};
};
&atl {
pinctrl-names = "default";
pinctrl-0 = <&atl_pins>;
assigned-clocks = <&abe_dpll_sys_clk_mux>,
<&atl_gfclk_mux>,
<&dpll_abe_ck>,
<&dpll_abe_m2x2_ck>,
<&atl_clkin2_ck>;
assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
status = "okay";
atl2 {
bws = <DRA7_ATL_WS_MCASP2_FSX>;
aws = <DRA7_ATL_WS_MCASP3_FSX>;
};
};
&mcasp3 {
#sound-dai-cells = <0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&mcasp3_pins>;
pinctrl-1 = <&mcasp3_sleep_pins>;
assigned-clocks = <&mcasp3_ahclkx_mux>;
assigned-clock-parents = <&atl_clkin2_ck>;
status = "okay";
op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
/* 4 serializer */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1 2 0 0
>;
};
&mailbox5 {
status = "okay";
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
status = "okay";
};
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
status = "okay";
};
};
&mailbox6 {
status = "okay";
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
status = "okay";
};
};
arch/arm/boot/dts/dra7xx-clocks.dtsi
View file @ 1ea7c8b6
......@@ -188,7 +188,7 @@ video2_m2_clkin_ck: video2_m2_clkin_ck {
clock-frequency = <0>;
};
dpll_abe_ck: dpll_abe_ck {
dpll_abe_ck: dpll_abe_ck@1e0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-m4xen-clock";
clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
......@@ -201,7 +201,7 @@ dpll_abe_x2_ck: dpll_abe_x2_ck {
clocks = <&dpll_abe_ck>;
};
dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_x2_ck>;
......@@ -212,7 +212,7 @@ dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
ti,invert-autoidle-bit;
};
abe_clk: abe_clk {
abe_clk: abe_clk@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2x2_ck>;
......@@ -221,7 +221,7 @@ abe_clk: abe_clk {
ti,index-power-of-two;
};
dpll_abe_m2_ck: dpll_abe_m2_ck {
dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_ck>;
......@@ -232,7 +232,7 @@ dpll_abe_m2_ck: dpll_abe_m2_ck {
ti,invert-autoidle-bit;
};
dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_x2_ck>;
......@@ -243,7 +243,7 @@ dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
ti,invert-autoidle-bit;
};
dpll_core_byp_mux: dpll_core_byp_mux {
dpll_core_byp_mux: dpll_core_byp_mux@12c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
......@@ -251,7 +251,7 @@ dpll_core_byp_mux: dpll_core_byp_mux {
reg = <0x012c>;
};
dpll_core_ck: dpll_core_ck {
dpll_core_ck: dpll_core_ck@120 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-core-clock";
clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
......@@ -264,7 +264,7 @@ dpll_core_x2_ck: dpll_core_x2_ck {
clocks = <&dpll_core_ck>;
};
dpll_core_h12x2_ck: dpll_core_h12x2_ck {
dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
......@@ -283,14 +283,14 @@ mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
clock-div = <1>;
};
dpll_mpu_ck: dpll_mpu_ck {
dpll_mpu_ck: dpll_mpu_ck@160 {
#clock-cells = <0>;
compatible = "ti,omap5-mpu-dpll-clock";
clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
};
dpll_mpu_m2_ck: dpll_mpu_m2_ck {
dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_mpu_ck>;
......@@ -317,7 +317,7 @@ dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
clock-div = <1>;
};
dpll_dsp_byp_mux: dpll_dsp_byp_mux {
dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
......@@ -325,14 +325,14 @@ dpll_dsp_byp_mux: dpll_dsp_byp_mux {
reg = <0x0240>;
};
dpll_dsp_ck: dpll_dsp_ck {
dpll_dsp_ck: dpll_dsp_ck@234 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
};
dpll_dsp_m2_ck: dpll_dsp_m2_ck {
dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_dsp_ck>;
......@@ -351,7 +351,7 @@ iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
clock-div = <1>;
};
dpll_iva_byp_mux: dpll_iva_byp_mux {
dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
......@@ -359,14 +359,14 @@ dpll_iva_byp_mux: dpll_iva_byp_mux {
reg = <0x01ac>;
};
dpll_iva_ck: dpll_iva_ck {
dpll_iva_ck: dpll_iva_ck@1a0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
};
dpll_iva_m2_ck: dpll_iva_m2_ck {
dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_iva_ck>;
......@@ -385,7 +385,7 @@ iva_dclk: iva_dclk {
clock-div = <1>;
};
dpll_gpu_byp_mux: dpll_gpu_byp_mux {
dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
......@@ -393,14 +393,14 @@ dpll_gpu_byp_mux: dpll_gpu_byp_mux {
reg = <0x02e4>;
};
dpll_gpu_ck: dpll_gpu_ck {
dpll_gpu_ck: dpll_gpu_ck@2d8 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
};
dpll_gpu_m2_ck: dpll_gpu_m2_ck {
dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gpu_ck>;
......@@ -411,7 +411,7 @@ dpll_gpu_m2_ck: dpll_gpu_m2_ck {
ti,invert-autoidle-bit;
};
dpll_core_m2_ck: dpll_core_m2_ck {
dpll_core_m2_ck: dpll_core_m2_ck@130 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_ck>;
......@@ -430,7 +430,7 @@ core_dpll_out_dclk_div: core_dpll_out_dclk_div {
clock-div = <1>;
};
dpll_ddr_byp_mux: dpll_ddr_byp_mux {
dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
......@@ -438,14 +438,14 @@ dpll_ddr_byp_mux: dpll_ddr_byp_mux {
reg = <0x021c>;
};
dpll_ddr_ck: dpll_ddr_ck {
dpll_ddr_ck: dpll_ddr_ck@210 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
};
dpll_ddr_m2_ck: dpll_ddr_m2_ck {
dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_ddr_ck>;
......@@ -456,7 +456,7 @@ dpll_ddr_m2_ck: dpll_ddr_m2_ck {
ti,invert-autoidle-bit;
};
dpll_gmac_byp_mux: dpll_gmac_byp_mux {
dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
......@@ -464,14 +464,14 @@ dpll_gmac_byp_mux: dpll_gmac_byp_mux {
reg = <0x02b4>;
};
dpll_gmac_ck: dpll_gmac_ck {
dpll_gmac_ck: dpll_gmac_ck@2a8 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
};
dpll_gmac_m2_ck: dpll_gmac_m2_ck {
dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_ck>;
......@@ -530,7 +530,7 @@ eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
clock-div = <1>;
};
dpll_eve_byp_mux: dpll_eve_byp_mux {
dpll_eve_byp_mux: dpll_eve_byp_mux@290 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
......@@ -538,14 +538,14 @@ dpll_eve_byp_mux: dpll_eve_byp_mux {
reg = <0x0290>;
};
dpll_eve_ck: dpll_eve_ck {
dpll_eve_ck: dpll_eve_ck@284 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
};
dpll_eve_m2_ck: dpll_eve_m2_ck {
dpll_eve_m2_ck: dpll_eve_m2_ck@294 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_eve_ck>;
......@@ -564,7 +564,7 @@ eve_dclk_div: eve_dclk_div {
clock-div = <1>;
};
dpll_core_h13x2_ck: dpll_core_h13x2_ck {
dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
......@@ -575,7 +575,7 @@ dpll_core_h13x2_ck: dpll_core_h13x2_ck {
ti,invert-autoidle-bit;
};
dpll_core_h14x2_ck: dpll_core_h14x2_ck {
dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
......@@ -586,7 +586,7 @@ dpll_core_h14x2_ck: dpll_core_h14x2_ck {
ti,invert-autoidle-bit;
};
dpll_core_h22x2_ck: dpll_core_h22x2_ck {
dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
......@@ -597,7 +597,7 @@ dpll_core_h22x2_ck: dpll_core_h22x2_ck {
ti,invert-autoidle-bit;
};
dpll_core_h23x2_ck: dpll_core_h23x2_ck {
dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
......@@ -608,7 +608,7 @@ dpll_core_h23x2_ck: dpll_core_h23x2_ck {
ti,invert-autoidle-bit;
};
dpll_core_h24x2_ck: dpll_core_h24x2_ck {
dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
......@@ -625,7 +625,7 @@ dpll_ddr_x2_ck: dpll_ddr_x2_ck {
clocks = <&dpll_ddr_ck>;
};
dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck {
dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_ddr_x2_ck>;
......@@ -642,7 +642,7 @@ dpll_dsp_x2_ck: dpll_dsp_x2_ck {
clocks = <&dpll_dsp_ck>;
};
dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck {
dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_dsp_x2_ck>;
......@@ -659,7 +659,7 @@ dpll_gmac_x2_ck: dpll_gmac_x2_ck {
clocks = <&dpll_gmac_ck>;
};
dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck {
dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_x2_ck>;
......@@ -670,7 +670,7 @@ dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck {
ti,invert-autoidle-bit;
};
dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck {
dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_x2_ck>;
......@@ -681,7 +681,7 @@ dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck {
ti,invert-autoidle-bit;
};
dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck {
dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_x2_ck>;
......@@ -692,7 +692,7 @@ dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck {
ti,invert-autoidle-bit;
};
dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck {
dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_x2_ck>;
......@@ -727,7 +727,7 @@ hdmi_div_clk: hdmi_div_clk {
clock-div = <1>;
};
l3_iclk_div: l3_iclk_div {
l3_iclk_div: l3_iclk_div@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
ti,max-div = <2>;
......@@ -777,7 +777,7 @@ video2_div_clk: video2_div_clk {
clock-div = <1>;
};
ipu1_gfclk_mux: ipu1_gfclk_mux {
ipu1_gfclk_mux: ipu1_gfclk_mux@520 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
......@@ -785,7 +785,7 @@ ipu1_gfclk_mux: ipu1_gfclk_mux {
reg = <0x0520>;
};
mcasp1_ahclkr_mux: mcasp1_ahclkr_mux {
mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
......@@ -793,7 +793,7 @@ mcasp1_ahclkr_mux: mcasp1_ahclkr_mux {
reg = <0x0550>;
};
mcasp1_ahclkx_mux: mcasp1_ahclkx_mux {
mcasp1_ahclkx_mux: mcasp1_ahclkx_mux@550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
......@@ -801,7 +801,7 @@ mcasp1_ahclkx_mux: mcasp1_ahclkx_mux {
reg = <0x0550>;
};
mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux {
mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux@550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
......@@ -809,7 +809,7 @@ mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux {
reg = <0x0550>;
};
timer5_gfclk_mux: timer5_gfclk_mux {
timer5_gfclk_mux: timer5_gfclk_mux@558 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
......@@ -817,7 +817,7 @@ timer5_gfclk_mux: timer5_gfclk_mux {
reg = <0x0558>;
};
timer6_gfclk_mux: timer6_gfclk_mux {
timer6_gfclk_mux: timer6_gfclk_mux@560 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
......@@ -825,7 +825,7 @@ timer6_gfclk_mux: timer6_gfclk_mux {
reg = <0x0560>;
};
timer7_gfclk_mux: timer7_gfclk_mux {
timer7_gfclk_mux: timer7_gfclk_mux@568 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
......@@ -833,7 +833,7 @@ timer7_gfclk_mux: timer7_gfclk_mux {
reg = <0x0568>;
};
timer8_gfclk_mux: timer8_gfclk_mux {
timer8_gfclk_mux: timer8_gfclk_mux@570 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
......@@ -841,7 +841,7 @@ timer8_gfclk_mux: timer8_gfclk_mux {
reg = <0x0570>;
};
uart6_gfclk_mux: uart6_gfclk_mux {
uart6_gfclk_mux: uart6_gfclk_mux@580 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
......@@ -856,7 +856,7 @@ dummy_ck: dummy_ck {
};
};
&prm_clocks {
sys_clkin1: sys_clkin1 {
sys_clkin1: sys_clkin1@110 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
......@@ -864,28 +864,28 @@ sys_clkin1: sys_clkin1 {
ti,index-starts-at-one;
};
abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux {
abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x0118>;
};
abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
reg = <0x0114>;
};
abe_dpll_clk_mux: abe_dpll_clk_mux {
abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
reg = <0x010c>;
};
abe_24m_fclk: abe_24m_fclk {
abe_24m_fclk: abe_24m_fclk@11c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2x2_ck>;
......@@ -893,7 +893,7 @@ abe_24m_fclk: abe_24m_fclk {
ti,dividers = <8>, <16>;
};
aess_fclk: aess_fclk {
aess_fclk: aess_fclk@178 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&abe_clk>;
......@@ -901,7 +901,7 @@ aess_fclk: aess_fclk {
ti,max-div = <2>;
};
abe_giclk_div: abe_giclk_div {
abe_giclk_div: abe_giclk_div@174 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&aess_fclk>;
......@@ -909,7 +909,7 @@ abe_giclk_div: abe_giclk_div {
ti,max-div = <2>;
};
abe_lp_clk_div: abe_lp_clk_div {
abe_lp_clk_div: abe_lp_clk_div@1d8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2x2_ck>;
......@@ -917,7 +917,7 @@ abe_lp_clk_div: abe_lp_clk_div {
ti,dividers = <16>, <32>;
};
abe_sys_clk_div: abe_sys_clk_div {
abe_sys_clk_div: abe_sys_clk_div@120 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin1>;
......@@ -925,14 +925,14 @@ abe_sys_clk_div: abe_sys_clk_div {
ti,max-div = <2>;
};
adc_gfclk_mux: adc_gfclk_mux {
adc_gfclk_mux: adc_gfclk_mux@1dc {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
reg = <0x01dc>;
};
sys_clk1_dclk_div: sys_clk1_dclk_div {
sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin1>;
......@@ -941,7 +941,7 @@ sys_clk1_dclk_div: sys_clk1_dclk_div {
ti,index-power-of-two;
};
sys_clk2_dclk_div: sys_clk2_dclk_div {
sys_clk2_dclk_div: sys_clk2_dclk_div@1cc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin2>;
......@@ -950,7 +950,7 @@ sys_clk2_dclk_div: sys_clk2_dclk_div {
ti,index-power-of-two;
};
per_abe_x1_dclk_div: per_abe_x1_dclk_div {
per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2_ck>;
......@@ -959,7 +959,7 @@ per_abe_x1_dclk_div: per_abe_x1_dclk_div {
ti,index-power-of-two;
};
dsp_gclk_div: dsp_gclk_div {
dsp_gclk_div: dsp_gclk_div@18c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_dsp_m2_ck>;
......@@ -968,7 +968,7 @@ dsp_gclk_div: dsp_gclk_div {
ti,index-power-of-two;
};
gpu_dclk: gpu_dclk {
gpu_dclk: gpu_dclk@1a0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gpu_m2_ck>;
......@@ -977,7 +977,7 @@ gpu_dclk: gpu_dclk {
ti,index-power-of-two;
};
emif_phy_dclk_div: emif_phy_dclk_div {
emif_phy_dclk_div: emif_phy_dclk_div@190 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_ddr_m2_ck>;
......@@ -986,7 +986,7 @@ emif_phy_dclk_div: emif_phy_dclk_div {
ti,index-power-of-two;
};
gmac_250m_dclk_div: gmac_250m_dclk_div {
gmac_250m_dclk_div: gmac_250m_dclk_div@19c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_m2_ck>;
......@@ -995,7 +995,7 @@ gmac_250m_dclk_div: gmac_250m_dclk_div {
ti,index-power-of-two;
};
l3init_480m_dclk_div: l3init_480m_dclk_div {
l3init_480m_dclk_div: l3init_480m_dclk_div@1ac {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_usb_m2_ck>;
......@@ -1004,7 +1004,7 @@ l3init_480m_dclk_div: l3init_480m_dclk_div {
ti,index-power-of-two;
};
usb_otg_dclk_div: usb_otg_dclk_div {
usb_otg_dclk_div: usb_otg_dclk_div@184 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&usb_otg_clkin_ck>;
......@@ -1013,7 +1013,7 @@ usb_otg_dclk_div: usb_otg_dclk_div {
ti,index-power-of-two;
};
sata_dclk_div: sata_dclk_div {
sata_dclk_div: sata_dclk_div@1c0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin1>;
......@@ -1022,7 +1022,7 @@ sata_dclk_div: sata_dclk_div {
ti,index-power-of-two;
};
pcie2_dclk_div: pcie2_dclk_div {
pcie2_dclk_div: pcie2_dclk_div@1b8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_pcie_ref_m2_ck>;
......@@ -1031,7 +1031,7 @@ pcie2_dclk_div: pcie2_dclk_div {
ti,index-power-of-two;
};
pcie_dclk_div: pcie_dclk_div {
pcie_dclk_div: pcie_dclk_div@1b4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&apll_pcie_m2_ck>;
......@@ -1040,7 +1040,7 @@ pcie_dclk_div: pcie_dclk_div {
ti,index-power-of-two;
};
emu_dclk_div: emu_dclk_div {
emu_dclk_div: emu_dclk_div@194 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin1>;
......@@ -1049,7 +1049,7 @@ emu_dclk_div: emu_dclk_div {
ti,index-power-of-two;
};
secure_32k_dclk_div: secure_32k_dclk_div {
secure_32k_dclk_div: secure_32k_dclk_div@1c4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&secure_32k_clk_src_ck>;
......@@ -1058,21 +1058,21 @@ secure_32k_dclk_div: secure_32k_dclk_div {
ti,index-power-of-two;
};
clkoutmux0_clk_mux: clkoutmux0_clk_mux {
clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
reg = <0x0158>;
};
clkoutmux1_clk_mux: clkoutmux1_clk_mux {
clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
reg = <0x015c>;
};
clkoutmux2_clk_mux: clkoutmux2_clk_mux {
clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
......@@ -1087,21 +1087,21 @@ custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
clock-div = <2>;
};
eve_clk: eve_clk {
eve_clk: eve_clk@180 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
reg = <0x0180>;
};
hdmi_dpll_clk_mux: hdmi_dpll_clk_mux {
hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x0164>;
};
mlb_clk: mlb_clk {
mlb_clk: mlb_clk@134 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mlb_clkin_ck>;
......@@ -1110,7 +1110,7 @@ mlb_clk: mlb_clk {
ti,index-power-of-two;
};
mlbp_clk: mlbp_clk {
mlbp_clk: mlbp_clk@130 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mlbp_clkin_ck>;
......@@ -1119,7 +1119,7 @@ mlbp_clk: mlbp_clk {
ti,index-power-of-two;
};
per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div {
per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2_ck>;
......@@ -1128,7 +1128,7 @@ per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div {
ti,index-power-of-two;
};
timer_sys_clk_div: timer_sys_clk_div {
timer_sys_clk_div: timer_sys_clk_div@144 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin1>;
......@@ -1136,28 +1136,28 @@ timer_sys_clk_div: timer_sys_clk_div {
ti,max-div = <2>;
};
video1_dpll_clk_mux: video1_dpll_clk_mux {
video1_dpll_clk_mux: video1_dpll_clk_mux@168 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x0168>;
};
video2_dpll_clk_mux: video2_dpll_clk_mux {
video2_dpll_clk_mux: video2_dpll_clk_mux@16c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
reg = <0x016c>;
};
wkupaon_iclk_mux: wkupaon_iclk_mux {
wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
reg = <0x0108>;
};
gpio1_dbclk: gpio1_dbclk {
gpio1_dbclk: gpio1_dbclk@1838 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -1165,7 +1165,7 @@ gpio1_dbclk: gpio1_dbclk {
reg = <0x1838>;
};
dcan1_sys_clk_mux: dcan1_sys_clk_mux {
dcan1_sys_clk_mux: dcan1_sys_clk_mux@1888 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&sys_clkin2>;
......@@ -1173,7 +1173,7 @@ dcan1_sys_clk_mux: dcan1_sys_clk_mux {
reg = <0x1888>;
};
timer1_gfclk_mux: timer1_gfclk_mux {
timer1_gfclk_mux: timer1_gfclk_mux@1840 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
......@@ -1181,7 +1181,7 @@ timer1_gfclk_mux: timer1_gfclk_mux {
reg = <0x1840>;
};
uart10_gfclk_mux: uart10_gfclk_mux {
uart10_gfclk_mux: uart10_gfclk_mux@1880 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
......@@ -1190,14 +1190,14 @@ uart10_gfclk_mux: uart10_gfclk_mux {
};
};
&cm_core_clocks {
dpll_pcie_ref_ck: dpll_pcie_ref_ck {
dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&sys_clkin1>;
reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
};
dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck {
dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_pcie_ref_ck>;
......@@ -1216,7 +1216,7 @@ apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
ti,bit-shift = <7>;
};
apll_pcie_ck: apll_pcie_ck {
apll_pcie_ck: apll_pcie_ck@21c {
#clock-cells = <0>;
compatible = "ti,dra7-apll-clock";
clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
......@@ -1305,7 +1305,7 @@ apll_pcie_m2_ck: apll_pcie_m2_ck {
clock-div = <1>;
};
dpll_per_byp_mux: dpll_per_byp_mux {
dpll_per_byp_mux: dpll_per_byp_mux@14c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
......@@ -1313,14 +1313,14 @@ dpll_per_byp_mux: dpll_per_byp_mux {
reg = <0x014c>;
};
dpll_per_ck: dpll_per_ck {
dpll_per_ck: dpll_per_ck@140 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
};
dpll_per_m2_ck: dpll_per_m2_ck {
dpll_per_m2_ck: dpll_per_m2_ck@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_ck>;
......@@ -1339,7 +1339,7 @@ func_96m_aon_dclk_div: func_96m_aon_dclk_div {
clock-div = <1>;
};
dpll_usb_byp_mux: dpll_usb_byp_mux {
dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
......@@ -1347,14 +1347,14 @@ dpll_usb_byp_mux: dpll_usb_byp_mux {
reg = <0x018c>;
};
dpll_usb_ck: dpll_usb_ck {
dpll_usb_ck: dpll_usb_ck@180 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-j-type-clock";
clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
};
dpll_usb_m2_ck: dpll_usb_m2_ck {
dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_usb_ck>;
......@@ -1365,7 +1365,7 @@ dpll_usb_m2_ck: dpll_usb_m2_ck {
ti,invert-autoidle-bit;
};
dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck {
dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_pcie_ref_ck>;
......@@ -1382,7 +1382,7 @@ dpll_per_x2_ck: dpll_per_x2_ck {
clocks = <&dpll_per_ck>;
};
dpll_per_h11x2_ck: dpll_per_h11x2_ck {
dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
......@@ -1393,7 +1393,7 @@ dpll_per_h11x2_ck: dpll_per_h11x2_ck {
ti,invert-autoidle-bit;
};
dpll_per_h12x2_ck: dpll_per_h12x2_ck {
dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
......@@ -1404,7 +1404,7 @@ dpll_per_h12x2_ck: dpll_per_h12x2_ck {
ti,invert-autoidle-bit;
};
dpll_per_h13x2_ck: dpll_per_h13x2_ck {
dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
......@@ -1415,7 +1415,7 @@ dpll_per_h13x2_ck: dpll_per_h13x2_ck {
ti,invert-autoidle-bit;
};
dpll_per_h14x2_ck: dpll_per_h14x2_ck {
dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
......@@ -1426,7 +1426,7 @@ dpll_per_h14x2_ck: dpll_per_h14x2_ck {
ti,invert-autoidle-bit;
};
dpll_per_m2x2_ck: dpll_per_m2x2_ck {
dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
......@@ -1485,7 +1485,7 @@ func_96m_fclk: func_96m_fclk {
clock-div = <2>;
};
l3init_60m_fclk: l3init_60m_fclk {
l3init_60m_fclk: l3init_60m_fclk@104 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_usb_m2_ck>;
......@@ -1493,7 +1493,7 @@ l3init_60m_fclk: l3init_60m_fclk {
ti,dividers = <1>, <8>;
};
clkout2_clk: clkout2_clk {
clkout2_clk: clkout2_clk@6b0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkoutmux2_clk_mux>;
......@@ -1501,7 +1501,7 @@ clkout2_clk: clkout2_clk {
reg = <0x06b0>;
};
l3init_960m_gfclk: l3init_960m_gfclk {
l3init_960m_gfclk: l3init_960m_gfclk@6c0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_usb_clkdcoldo>;
......@@ -1509,7 +1509,7 @@ l3init_960m_gfclk: l3init_960m_gfclk {
reg = <0x06c0>;
};
dss_32khz_clk: dss_32khz_clk {
dss_32khz_clk: dss_32khz_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -1517,7 +1517,7 @@ dss_32khz_clk: dss_32khz_clk {
reg = <0x1120>;
};
dss_48mhz_clk: dss_48mhz_clk {
dss_48mhz_clk: dss_48mhz_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&func_48m_fclk>;
......@@ -1525,7 +1525,7 @@ dss_48mhz_clk: dss_48mhz_clk {
reg = <0x1120>;
};
dss_dss_clk: dss_dss_clk {
dss_dss_clk: dss_dss_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_h12x2_ck>;
......@@ -1534,7 +1534,7 @@ dss_dss_clk: dss_dss_clk {
ti,set-rate-parent;
};
dss_hdmi_clk: dss_hdmi_clk {
dss_hdmi_clk: dss_hdmi_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&hdmi_dpll_clk_mux>;
......@@ -1542,7 +1542,7 @@ dss_hdmi_clk: dss_hdmi_clk {
reg = <0x1120>;
};
dss_video1_clk: dss_video1_clk {
dss_video1_clk: dss_video1_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&video1_dpll_clk_mux>;
......@@ -1550,7 +1550,7 @@ dss_video1_clk: dss_video1_clk {
reg = <0x1120>;
};
dss_video2_clk: dss_video2_clk {
dss_video2_clk: dss_video2_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&video2_dpll_clk_mux>;
......@@ -1558,7 +1558,7 @@ dss_video2_clk: dss_video2_clk {
reg = <0x1120>;
};
gpio2_dbclk: gpio2_dbclk {
gpio2_dbclk: gpio2_dbclk@1760 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -1566,7 +1566,7 @@ gpio2_dbclk: gpio2_dbclk {
reg = <0x1760>;
};
gpio3_dbclk: gpio3_dbclk {
gpio3_dbclk: gpio3_dbclk@1768 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -1574,7 +1574,7 @@ gpio3_dbclk: gpio3_dbclk {
reg = <0x1768>;
};
gpio4_dbclk: gpio4_dbclk {
gpio4_dbclk: gpio4_dbclk@1770 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -1582,7 +1582,7 @@ gpio4_dbclk: gpio4_dbclk {
reg = <0x1770>;
};
gpio5_dbclk: gpio5_dbclk {
gpio5_dbclk: gpio5_dbclk@1778 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -1590,7 +1590,7 @@ gpio5_dbclk: gpio5_dbclk {
reg = <0x1778>;
};
gpio6_dbclk: gpio6_dbclk {
gpio6_dbclk: gpio6_dbclk@1780 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -1598,7 +1598,7 @@ gpio6_dbclk: gpio6_dbclk {
reg = <0x1780>;
};
gpio7_dbclk: gpio7_dbclk {
gpio7_dbclk: gpio7_dbclk@1810 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -1606,7 +1606,7 @@ gpio7_dbclk: gpio7_dbclk {
reg = <0x1810>;
};
gpio8_dbclk: gpio8_dbclk {
gpio8_dbclk: gpio8_dbclk@1818 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -1614,7 +1614,7 @@ gpio8_dbclk: gpio8_dbclk {
reg = <0x1818>;
};
mmc1_clk32k: mmc1_clk32k {
mmc1_clk32k: mmc1_clk32k@1328 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -1622,7 +1622,7 @@ mmc1_clk32k: mmc1_clk32k {
reg = <0x1328>;
};
mmc2_clk32k: mmc2_clk32k {
mmc2_clk32k: mmc2_clk32k@1330 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -1630,7 +1630,7 @@ mmc2_clk32k: mmc2_clk32k {
reg = <0x1330>;
};
mmc3_clk32k: mmc3_clk32k {
mmc3_clk32k: mmc3_clk32k@1820 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -1638,7 +1638,7 @@ mmc3_clk32k: mmc3_clk32k {
reg = <0x1820>;
};
mmc4_clk32k: mmc4_clk32k {
mmc4_clk32k: mmc4_clk32k@1828 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -1646,7 +1646,7 @@ mmc4_clk32k: mmc4_clk32k {
reg = <0x1828>;
};
sata_ref_clk: sata_ref_clk {
sata_ref_clk: sata_ref_clk@1388 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_clkin1>;
......@@ -1654,7 +1654,7 @@ sata_ref_clk: sata_ref_clk {
reg = <0x1388>;
};
usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@13f0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3init_960m_gfclk>;
......@@ -1662,7 +1662,7 @@ usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
reg = <0x13f0>;
};
usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m@1340 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3init_960m_gfclk>;
......@@ -1670,7 +1670,7 @@ usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
reg = <0x1340>;
};
usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -1678,7 +1678,7 @@ usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
reg = <0x0640>;
};
usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k {
usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -1686,7 +1686,7 @@ usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k {
reg = <0x0688>;
};
usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k {
usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -1694,7 +1694,7 @@ usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k {
reg = <0x0698>;
};
atl_dpll_clk_mux: atl_dpll_clk_mux {
atl_dpll_clk_mux: atl_dpll_clk_mux@c00 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
......@@ -1702,7 +1702,7 @@ atl_dpll_clk_mux: atl_dpll_clk_mux {
reg = <0x0c00>;
};
atl_gfclk_mux: atl_gfclk_mux {
atl_gfclk_mux: atl_gfclk_mux@c00 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
......@@ -1710,7 +1710,7 @@ atl_gfclk_mux: atl_gfclk_mux {
reg = <0x0c00>;
};
gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div@13d0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_gmac_m2_ck>;
......@@ -1719,7 +1719,7 @@ gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
ti,dividers = <2>;
};
gmac_rft_clk_mux: gmac_rft_clk_mux {
gmac_rft_clk_mux: gmac_rft_clk_mux@13d0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
......@@ -1727,7 +1727,7 @@ gmac_rft_clk_mux: gmac_rft_clk_mux {
reg = <0x13d0>;
};
gpu_core_gclk_mux: gpu_core_gclk_mux {
gpu_core_gclk_mux: gpu_core_gclk_mux@1220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
......@@ -1735,7 +1735,7 @@ gpu_core_gclk_mux: gpu_core_gclk_mux {
reg = <0x1220>;
};
gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
......@@ -1743,7 +1743,7 @@ gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
reg = <0x1220>;
};
l3instr_ts_gclk_div: l3instr_ts_gclk_div {
l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&wkupaon_iclk_mux>;
......@@ -1752,7 +1752,7 @@ l3instr_ts_gclk_div: l3instr_ts_gclk_div {
ti,dividers = <8>, <16>, <32>;
};
mcasp2_ahclkr_mux: mcasp2_ahclkr_mux {
mcasp2_ahclkr_mux: mcasp2_ahclkr_mux@1860 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
......@@ -1760,7 +1760,7 @@ mcasp2_ahclkr_mux: mcasp2_ahclkr_mux {
reg = <0x1860>;
};
mcasp2_ahclkx_mux: mcasp2_ahclkx_mux {
mcasp2_ahclkx_mux: mcasp2_ahclkx_mux@1860 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
......@@ -1768,7 +1768,7 @@ mcasp2_ahclkx_mux: mcasp2_ahclkx_mux {
reg = <0x1860>;
};
mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux {
mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux@1860 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
......@@ -1776,7 +1776,7 @@ mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux {
reg = <0x1860>;
};
mcasp3_ahclkx_mux: mcasp3_ahclkx_mux {
mcasp3_ahclkx_mux: mcasp3_ahclkx_mux@1868 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
......@@ -1784,7 +1784,7 @@ mcasp3_ahclkx_mux: mcasp3_ahclkx_mux {
reg = <0x1868>;
};
mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux {
mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux@1868 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
......@@ -1792,7 +1792,7 @@ mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux {
reg = <0x1868>;
};
mcasp4_ahclkx_mux: mcasp4_ahclkx_mux {
mcasp4_ahclkx_mux: mcasp4_ahclkx_mux@1898 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
......@@ -1800,7 +1800,7 @@ mcasp4_ahclkx_mux: mcasp4_ahclkx_mux {
reg = <0x1898>;
};
mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux {
mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux@1898 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
......@@ -1808,7 +1808,7 @@ mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux {
reg = <0x1898>;
};
mcasp5_ahclkx_mux: mcasp5_ahclkx_mux {
mcasp5_ahclkx_mux: mcasp5_ahclkx_mux@1878 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
......@@ -1816,7 +1816,7 @@ mcasp5_ahclkx_mux: mcasp5_ahclkx_mux {
reg = <0x1878>;
};
mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux {
mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux@1878 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
......@@ -1824,7 +1824,7 @@ mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux {
reg = <0x1878>;
};
mcasp6_ahclkx_mux: mcasp6_ahclkx_mux {
mcasp6_ahclkx_mux: mcasp6_ahclkx_mux@1904 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
......@@ -1832,7 +1832,7 @@ mcasp6_ahclkx_mux: mcasp6_ahclkx_mux {
reg = <0x1904>;
};
mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux {
mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux@1904 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
......@@ -1840,7 +1840,7 @@ mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux {
reg = <0x1904>;
};
mcasp7_ahclkx_mux: mcasp7_ahclkx_mux {
mcasp7_ahclkx_mux: mcasp7_ahclkx_mux@1908 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
......@@ -1848,7 +1848,7 @@ mcasp7_ahclkx_mux: mcasp7_ahclkx_mux {
reg = <0x1908>;
};
mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux {
mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux@1908 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
......@@ -1856,7 +1856,7 @@ mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux {
reg = <0x1908>;
};
mcasp8_ahclk_mux: mcasp8_ahclk_mux {
mcasp8_ahclkx_mux: mcasp8_ahclkx_mux@1890 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
......@@ -1864,7 +1864,7 @@ mcasp8_ahclk_mux: mcasp8_ahclk_mux {
reg = <0x1890>;
};
mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux {
mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux@1890 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
......@@ -1872,7 +1872,7 @@ mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux {
reg = <0x1890>;
};
mmc1_fclk_mux: mmc1_fclk_mux {
mmc1_fclk_mux: mmc1_fclk_mux@1328 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
......@@ -1880,7 +1880,7 @@ mmc1_fclk_mux: mmc1_fclk_mux {
reg = <0x1328>;
};
mmc1_fclk_div: mmc1_fclk_div {
mmc1_fclk_div: mmc1_fclk_div@1328 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc1_fclk_mux>;
......@@ -1890,7 +1890,7 @@ mmc1_fclk_div: mmc1_fclk_div {
ti,index-power-of-two;
};
mmc2_fclk_mux: mmc2_fclk_mux {
mmc2_fclk_mux: mmc2_fclk_mux@1330 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
......@@ -1898,7 +1898,7 @@ mmc2_fclk_mux: mmc2_fclk_mux {
reg = <0x1330>;
};
mmc2_fclk_div: mmc2_fclk_div {
mmc2_fclk_div: mmc2_fclk_div@1330 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc2_fclk_mux>;
......@@ -1908,7 +1908,7 @@ mmc2_fclk_div: mmc2_fclk_div {
ti,index-power-of-two;
};
mmc3_gfclk_mux: mmc3_gfclk_mux {
mmc3_gfclk_mux: mmc3_gfclk_mux@1820 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
......@@ -1916,7 +1916,7 @@ mmc3_gfclk_mux: mmc3_gfclk_mux {
reg = <0x1820>;
};
mmc3_gfclk_div: mmc3_gfclk_div {
mmc3_gfclk_div: mmc3_gfclk_div@1820 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc3_gfclk_mux>;
......@@ -1926,7 +1926,7 @@ mmc3_gfclk_div: mmc3_gfclk_div {
ti,index-power-of-two;
};
mmc4_gfclk_mux: mmc4_gfclk_mux {
mmc4_gfclk_mux: mmc4_gfclk_mux@1828 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
......@@ -1934,7 +1934,7 @@ mmc4_gfclk_mux: mmc4_gfclk_mux {
reg = <0x1828>;
};
mmc4_gfclk_div: mmc4_gfclk_div {
mmc4_gfclk_div: mmc4_gfclk_div@1828 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc4_gfclk_mux>;
......@@ -1944,7 +1944,7 @@ mmc4_gfclk_div: mmc4_gfclk_div {
ti,index-power-of-two;
};
qspi_gfclk_mux: qspi_gfclk_mux {
qspi_gfclk_mux: qspi_gfclk_mux@1838 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
......@@ -1952,7 +1952,7 @@ qspi_gfclk_mux: qspi_gfclk_mux {
reg = <0x1838>;
};
qspi_gfclk_div: qspi_gfclk_div {
qspi_gfclk_div: qspi_gfclk_div@1838 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&qspi_gfclk_mux>;
......@@ -1962,7 +1962,7 @@ qspi_gfclk_div: qspi_gfclk_div {
ti,index-power-of-two;
};
timer10_gfclk_mux: timer10_gfclk_mux {
timer10_gfclk_mux: timer10_gfclk_mux@1728 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
......@@ -1970,7 +1970,7 @@ timer10_gfclk_mux: timer10_gfclk_mux {
reg = <0x1728>;
};
timer11_gfclk_mux: timer11_gfclk_mux {
timer11_gfclk_mux: timer11_gfclk_mux@1730 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
......@@ -1978,7 +1978,7 @@ timer11_gfclk_mux: timer11_gfclk_mux {
reg = <0x1730>;
};
timer13_gfclk_mux: timer13_gfclk_mux {
timer13_gfclk_mux: timer13_gfclk_mux@17c8 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
......@@ -1986,7 +1986,7 @@ timer13_gfclk_mux: timer13_gfclk_mux {
reg = <0x17c8>;
};
timer14_gfclk_mux: timer14_gfclk_mux {
timer14_gfclk_mux: timer14_gfclk_mux@17d0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
......@@ -1994,7 +1994,7 @@ timer14_gfclk_mux: timer14_gfclk_mux {
reg = <0x17d0>;
};
timer15_gfclk_mux: timer15_gfclk_mux {
timer15_gfclk_mux: timer15_gfclk_mux@17d8 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
......@@ -2002,7 +2002,7 @@ timer15_gfclk_mux: timer15_gfclk_mux {
reg = <0x17d8>;
};
timer16_gfclk_mux: timer16_gfclk_mux {
timer16_gfclk_mux: timer16_gfclk_mux@1830 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
......@@ -2010,7 +2010,7 @@ timer16_gfclk_mux: timer16_gfclk_mux {
reg = <0x1830>;
};
timer2_gfclk_mux: timer2_gfclk_mux {
timer2_gfclk_mux: timer2_gfclk_mux@1738 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
......@@ -2018,7 +2018,7 @@ timer2_gfclk_mux: timer2_gfclk_mux {
reg = <0x1738>;
};
timer3_gfclk_mux: timer3_gfclk_mux {
timer3_gfclk_mux: timer3_gfclk_mux@1740 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
......@@ -2026,7 +2026,7 @@ timer3_gfclk_mux: timer3_gfclk_mux {
reg = <0x1740>;
};
timer4_gfclk_mux: timer4_gfclk_mux {
timer4_gfclk_mux: timer4_gfclk_mux@1748 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
......@@ -2034,7 +2034,7 @@ timer4_gfclk_mux: timer4_gfclk_mux {
reg = <0x1748>;
};
timer9_gfclk_mux: timer9_gfclk_mux {
timer9_gfclk_mux: timer9_gfclk_mux@1750 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
......@@ -2042,7 +2042,7 @@ timer9_gfclk_mux: timer9_gfclk_mux {
reg = <0x1750>;
};
uart1_gfclk_mux: uart1_gfclk_mux {
uart1_gfclk_mux: uart1_gfclk_mux@1840 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
......@@ -2050,7 +2050,7 @@ uart1_gfclk_mux: uart1_gfclk_mux {
reg = <0x1840>;
};
uart2_gfclk_mux: uart2_gfclk_mux {
uart2_gfclk_mux: uart2_gfclk_mux@1848 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
......@@ -2058,7 +2058,7 @@ uart2_gfclk_mux: uart2_gfclk_mux {
reg = <0x1848>;
};
uart3_gfclk_mux: uart3_gfclk_mux {
uart3_gfclk_mux: uart3_gfclk_mux@1850 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
......@@ -2066,7 +2066,7 @@ uart3_gfclk_mux: uart3_gfclk_mux {
reg = <0x1850>;
};
uart4_gfclk_mux: uart4_gfclk_mux {
uart4_gfclk_mux: uart4_gfclk_mux@1858 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
......@@ -2074,7 +2074,7 @@ uart4_gfclk_mux: uart4_gfclk_mux {
reg = <0x1858>;
};
uart5_gfclk_mux: uart5_gfclk_mux {
uart5_gfclk_mux: uart5_gfclk_mux@1870 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
......@@ -2082,7 +2082,7 @@ uart5_gfclk_mux: uart5_gfclk_mux {
reg = <0x1870>;
};
uart7_gfclk_mux: uart7_gfclk_mux {
uart7_gfclk_mux: uart7_gfclk_mux@18d0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
......@@ -2090,7 +2090,7 @@ uart7_gfclk_mux: uart7_gfclk_mux {
reg = <0x18d0>;
};
uart8_gfclk_mux: uart8_gfclk_mux {
uart8_gfclk_mux: uart8_gfclk_mux@18e0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
......@@ -2098,7 +2098,7 @@ uart8_gfclk_mux: uart8_gfclk_mux {
reg = <0x18e0>;
};
uart9_gfclk_mux: uart9_gfclk_mux {
uart9_gfclk_mux: uart9_gfclk_mux@18e8 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
......@@ -2106,7 +2106,7 @@ uart9_gfclk_mux: uart9_gfclk_mux {
reg = <0x18e8>;
};
vip1_gclk_mux: vip1_gclk_mux {
vip1_gclk_mux: vip1_gclk_mux@1020 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
......@@ -2114,7 +2114,7 @@ vip1_gclk_mux: vip1_gclk_mux {
reg = <0x1020>;
};
vip2_gclk_mux: vip2_gclk_mux {
vip2_gclk_mux: vip2_gclk_mux@1028 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
......@@ -2122,7 +2122,7 @@ vip2_gclk_mux: vip2_gclk_mux {
reg = <0x1028>;
};
vip3_gclk_mux: vip3_gclk_mux {
vip3_gclk_mux: vip3_gclk_mux@1030 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
......@@ -2139,7 +2139,7 @@ coreaon_clkdm: coreaon_clkdm {
};
&scm_conf_clocks {
dss_deshdcp_clk: dss_deshdcp_clk {
dss_deshdcp_clk: dss_deshdcp_clk@558 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3_iclk_div>;
......@@ -2147,7 +2147,7 @@ dss_deshdcp_clk: dss_deshdcp_clk {
reg = <0x558>;
};
ehrpwm0_tbclk: ehrpwm0_tbclk {
ehrpwm0_tbclk: ehrpwm0_tbclk@558 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l4_root_clk_div>;
......@@ -2155,7 +2155,7 @@ ehrpwm0_tbclk: ehrpwm0_tbclk {
reg = <0x0558>;
};
ehrpwm1_tbclk: ehrpwm1_tbclk {
ehrpwm1_tbclk: ehrpwm1_tbclk@558 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l4_root_clk_div>;
......@@ -2163,7 +2163,7 @@ ehrpwm1_tbclk: ehrpwm1_tbclk {
reg = <0x0558>;
};
ehrpwm2_tbclk: ehrpwm2_tbclk {
ehrpwm2_tbclk: ehrpwm2_tbclk@558 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l4_root_clk_div>;
......
arch/arm/boot/dts/omap2420-clocks.dtsi
View file @ 1ea7c8b6
......@@ -9,7 +9,7 @@
*/
&prcm_clocks {
sys_clkout2_src_gate: sys_clkout2_src_gate {
sys_clkout2_src_gate: sys_clkout2_src_gate@70 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clocks = <&core_ck>;
......@@ -17,7 +17,7 @@ sys_clkout2_src_gate: sys_clkout2_src_gate {
reg = <0x0070>;
};
sys_clkout2_src_mux: sys_clkout2_src_mux {
sys_clkout2_src_mux: sys_clkout2_src_mux@70 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
......@@ -31,7 +31,7 @@ sys_clkout2_src: sys_clkout2_src {
clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>;
};
sys_clkout2: sys_clkout2 {
sys_clkout2: sys_clkout2@70 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkout2_src>;
......@@ -41,7 +41,7 @@ sys_clkout2: sys_clkout2 {
ti,index-power-of-two;
};
dsp_gate_ick: dsp_gate_ick {
dsp_gate_ick: dsp_gate_ick@810 {
#clock-cells = <0>;
compatible = "ti,composite-interface-clock";
clocks = <&dsp_fck>;
......@@ -49,7 +49,7 @@ dsp_gate_ick: dsp_gate_ick {
reg = <0x0810>;
};
dsp_div_ick: dsp_div_ick {
dsp_div_ick: dsp_div_ick@840 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&dsp_fck>;
......@@ -65,7 +65,7 @@ dsp_ick: dsp_ick {
clocks = <&dsp_gate_ick>, <&dsp_div_ick>;
};
iva1_gate_ifck: iva1_gate_ifck {
iva1_gate_ifck: iva1_gate_ifck@800 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&core_ck>;
......@@ -73,7 +73,7 @@ iva1_gate_ifck: iva1_gate_ifck {
reg = <0x0800>;
};
iva1_div_ifck: iva1_div_ifck {
iva1_div_ifck: iva1_div_ifck@840 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&core_ck>;
......@@ -96,7 +96,7 @@ iva1_ifck_div: iva1_ifck_div {
clock-div = <2>;
};
iva1_mpu_int_ifck: iva1_mpu_int_ifck {
iva1_mpu_int_ifck: iva1_mpu_int_ifck@800 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&iva1_ifck_div>;
......@@ -104,7 +104,7 @@ iva1_mpu_int_ifck: iva1_mpu_int_ifck {
reg = <0x0800>;
};
wdt3_ick: wdt3_ick {
wdt3_ick: wdt3_ick@210 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -112,7 +112,7 @@ wdt3_ick: wdt3_ick {
reg = <0x0210>;
};
wdt3_fck: wdt3_fck {
wdt3_fck: wdt3_fck@200 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_32k_ck>;
......@@ -120,7 +120,7 @@ wdt3_fck: wdt3_fck {
reg = <0x0200>;
};
mmc_ick: mmc_ick {
mmc_ick: mmc_ick@210 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -128,7 +128,7 @@ mmc_ick: mmc_ick {
reg = <0x0210>;
};
mmc_fck: mmc_fck {
mmc_fck: mmc_fck@200 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_96m_ck>;
......@@ -136,7 +136,7 @@ mmc_fck: mmc_fck {
reg = <0x0200>;
};
eac_ick: eac_ick {
eac_ick: eac_ick@210 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -144,7 +144,7 @@ eac_ick: eac_ick {
reg = <0x0210>;
};
eac_fck: eac_fck {
eac_fck: eac_fck@200 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_96m_ck>;
......@@ -152,7 +152,7 @@ eac_fck: eac_fck {
reg = <0x0200>;
};
i2c1_fck: i2c1_fck {
i2c1_fck: i2c1_fck@200 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_12m_ck>;
......@@ -160,7 +160,7 @@ i2c1_fck: i2c1_fck {
reg = <0x0200>;
};
i2c2_fck: i2c2_fck {
i2c2_fck: i2c2_fck@200 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_12m_ck>;
......@@ -168,7 +168,7 @@ i2c2_fck: i2c2_fck {
reg = <0x0200>;
};
vlynq_ick: vlynq_ick {
vlynq_ick: vlynq_ick@210 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l3_ck>;
......@@ -176,7 +176,7 @@ vlynq_ick: vlynq_ick {
reg = <0x0210>;
};
vlynq_gate_fck: vlynq_gate_fck {
vlynq_gate_fck: vlynq_gate_fck@200 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&core_ck>;
......@@ -192,7 +192,7 @@ core_d18_ck: core_d18_ck {
clock-div = <18>;
};
vlynq_mux_fck: vlynq_mux_fck {
vlynq_mux_fck: vlynq_mux_fck@240 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_96m_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&dummy_ck>, <&core_d6_ck>, <&dummy_ck>, <&core_d8_ck>, <&core_d9_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d12_ck>, <&dummy_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d16_ck>, <&dummy_ck>, <&core_d18_ck>;
......
arch/arm/boot/dts/omap2420-n8x0-common.dtsi
View file @ 1ea7c8b6
......@@ -7,7 +7,7 @@ memory {
};
ocp {
i2c@0 {
i2c0 {
compatible = "i2c-cbus-gpio";
gpios = <&gpio3 2 GPIO_ACTIVE_HIGH /* gpio66 clk */
&gpio3 1 GPIO_ACTIVE_HIGH /* gpio65 dat */
......
arch/arm/boot/dts/omap2420.dtsi
View file @ 1ea7c8b6
......@@ -130,6 +130,10 @@ gpmc: gpmc@6800a000 {
gpmc,num-cs = <8>;
gpmc,num-waitpins = <4>;
ti,hwmods = "gpmc";
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
};
mcbsp1: mcbsp@48074000 {
......
arch/arm/boot/dts/omap2430-clocks.dtsi
View file @ 1ea7c8b6
......@@ -9,7 +9,7 @@
*/
&scm_clocks {
mcbsp3_mux_fck: mcbsp3_mux_fck {
mcbsp3_mux_fck: mcbsp3_mux_fck@78 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_96m_ck>, <&mcbsp_clks>;
......@@ -22,7 +22,7 @@ mcbsp3_fck: mcbsp3_fck {
clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
};
mcbsp4_mux_fck: mcbsp4_mux_fck {
mcbsp4_mux_fck: mcbsp4_mux_fck@78 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_96m_ck>, <&mcbsp_clks>;
......@@ -36,7 +36,7 @@ mcbsp4_fck: mcbsp4_fck {
clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
};
mcbsp5_mux_fck: mcbsp5_mux_fck {
mcbsp5_mux_fck: mcbsp5_mux_fck@78 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_96m_ck>, <&mcbsp_clks>;
......@@ -52,7 +52,7 @@ mcbsp5_fck: mcbsp5_fck {
};
&prcm_clocks {
iva2_1_gate_ick: iva2_1_gate_ick {
iva2_1_gate_ick: iva2_1_gate_ick@800 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&dsp_fck>;
......@@ -60,7 +60,7 @@ iva2_1_gate_ick: iva2_1_gate_ick {
reg = <0x0800>;
};
iva2_1_div_ick: iva2_1_div_ick {
iva2_1_div_ick: iva2_1_div_ick@840 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&dsp_fck>;
......@@ -76,7 +76,7 @@ iva2_1_ick: iva2_1_ick {
clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>;
};
mdm_gate_ick: mdm_gate_ick {
mdm_gate_ick: mdm_gate_ick@c10 {
#clock-cells = <0>;
compatible = "ti,composite-interface-clock";
clocks = <&core_ck>;
......@@ -84,7 +84,7 @@ mdm_gate_ick: mdm_gate_ick {
reg = <0x0c10>;
};
mdm_div_ick: mdm_div_ick {
mdm_div_ick: mdm_div_ick@c40 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&core_ck>;
......@@ -98,7 +98,7 @@ mdm_ick: mdm_ick {
clocks = <&mdm_gate_ick>, <&mdm_div_ick>;
};
mdm_osc_ck: mdm_osc_ck {
mdm_osc_ck: mdm_osc_ck@c00 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&osc_ck>;
......@@ -106,7 +106,7 @@ mdm_osc_ck: mdm_osc_ck {
reg = <0x0c00>;
};
mcbsp3_ick: mcbsp3_ick {
mcbsp3_ick: mcbsp3_ick@214 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -114,7 +114,7 @@ mcbsp3_ick: mcbsp3_ick {
reg = <0x0214>;
};
mcbsp3_gate_fck: mcbsp3_gate_fck {
mcbsp3_gate_fck: mcbsp3_gate_fck@204 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&mcbsp_clks>;
......@@ -122,7 +122,7 @@ mcbsp3_gate_fck: mcbsp3_gate_fck {
reg = <0x0204>;
};
mcbsp4_ick: mcbsp4_ick {
mcbsp4_ick: mcbsp4_ick@214 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -130,7 +130,7 @@ mcbsp4_ick: mcbsp4_ick {
reg = <0x0214>;
};
mcbsp4_gate_fck: mcbsp4_gate_fck {
mcbsp4_gate_fck: mcbsp4_gate_fck@204 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&mcbsp_clks>;
......@@ -138,7 +138,7 @@ mcbsp4_gate_fck: mcbsp4_gate_fck {
reg = <0x0204>;
};
mcbsp5_ick: mcbsp5_ick {
mcbsp5_ick: mcbsp5_ick@214 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -146,7 +146,7 @@ mcbsp5_ick: mcbsp5_ick {
reg = <0x0214>;
};
mcbsp5_gate_fck: mcbsp5_gate_fck {
mcbsp5_gate_fck: mcbsp5_gate_fck@204 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&mcbsp_clks>;
......@@ -154,7 +154,7 @@ mcbsp5_gate_fck: mcbsp5_gate_fck {
reg = <0x0204>;
};
mcspi3_ick: mcspi3_ick {
mcspi3_ick: mcspi3_ick@214 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -162,7 +162,7 @@ mcspi3_ick: mcspi3_ick {
reg = <0x0214>;
};
mcspi3_fck: mcspi3_fck {
mcspi3_fck: mcspi3_fck@204 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_48m_ck>;
......@@ -170,7 +170,7 @@ mcspi3_fck: mcspi3_fck {
reg = <0x0204>;
};
icr_ick: icr_ick {
icr_ick: icr_ick@410 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&sys_ck>;
......@@ -178,7 +178,7 @@ icr_ick: icr_ick {
reg = <0x0410>;
};
i2chs1_fck: i2chs1_fck {
i2chs1_fck: i2chs1_fck@204 {
#clock-cells = <0>;
compatible = "ti,omap2430-interface-clock";
clocks = <&func_96m_ck>;
......@@ -186,7 +186,7 @@ i2chs1_fck: i2chs1_fck {
reg = <0x0204>;
};
i2chs2_fck: i2chs2_fck {
i2chs2_fck: i2chs2_fck@204 {
#clock-cells = <0>;
compatible = "ti,omap2430-interface-clock";
clocks = <&func_96m_ck>;
......@@ -194,7 +194,7 @@ i2chs2_fck: i2chs2_fck {
reg = <0x0204>;
};
usbhs_ick: usbhs_ick {
usbhs_ick: usbhs_ick@214 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l3_ck>;
......@@ -202,7 +202,7 @@ usbhs_ick: usbhs_ick {
reg = <0x0214>;
};
mmchs1_ick: mmchs1_ick {
mmchs1_ick: mmchs1_ick@214 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -210,7 +210,7 @@ mmchs1_ick: mmchs1_ick {
reg = <0x0214>;
};
mmchs1_fck: mmchs1_fck {
mmchs1_fck: mmchs1_fck@204 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_96m_ck>;
......@@ -218,7 +218,7 @@ mmchs1_fck: mmchs1_fck {
reg = <0x0204>;
};
mmchs2_ick: mmchs2_ick {
mmchs2_ick: mmchs2_ick@214 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -226,7 +226,7 @@ mmchs2_ick: mmchs2_ick {
reg = <0x0214>;
};
mmchs2_fck: mmchs2_fck {
mmchs2_fck: mmchs2_fck@204 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_96m_ck>;
......@@ -234,7 +234,7 @@ mmchs2_fck: mmchs2_fck {
reg = <0x0204>;
};
gpio5_ick: gpio5_ick {
gpio5_ick: gpio5_ick@214 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -242,7 +242,7 @@ gpio5_ick: gpio5_ick {
reg = <0x0214>;
};
gpio5_fck: gpio5_fck {
gpio5_fck: gpio5_fck@204 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_32k_ck>;
......@@ -250,7 +250,7 @@ gpio5_fck: gpio5_fck {
reg = <0x0204>;
};
mdm_intc_ick: mdm_intc_ick {
mdm_intc_ick: mdm_intc_ick@214 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -258,7 +258,7 @@ mdm_intc_ick: mdm_intc_ick {
reg = <0x0214>;
};
mmchsdb1_fck: mmchsdb1_fck {
mmchsdb1_fck: mmchsdb1_fck@204 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_32k_ck>;
......@@ -266,7 +266,7 @@ mmchsdb1_fck: mmchsdb1_fck {
reg = <0x0204>;
};
mmchsdb2_fck: mmchsdb2_fck {
mmchsdb2_fck: mmchsdb2_fck@204 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_32k_ck>;
......
arch/arm/boot/dts/omap2430.dtsi
View file @ 1ea7c8b6
......@@ -63,7 +63,7 @@ scm_clocks: clocks {
#size-cells = <0>;
};
pbias_regulator: pbias_regulator {
pbias_regulator: pbias_regulator@230 {
compatible = "ti,pbias-omap2", "ti,pbias-omap";
reg = <0x230 0x4>;
syscon = <&scm_conf>;
......@@ -154,6 +154,10 @@ gpmc: gpmc@6e000000 {
gpmc,num-cs = <8>;
gpmc,num-waitpins = <4>;
ti,hwmods = "gpmc";
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
};
mcbsp1: mcbsp@48074000 {
......
arch/arm/boot/dts/omap24xx-clocks.dtsi
View file @ 1ea7c8b6
......@@ -8,7 +8,7 @@
* published by the Free Software Foundation.
*/
&scm_clocks {
mcbsp1_mux_fck: mcbsp1_mux_fck {
mcbsp1_mux_fck: mcbsp1_mux_fck@4 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_96m_ck>, <&mcbsp_clks>;
......@@ -22,7 +22,7 @@ mcbsp1_fck: mcbsp1_fck {
clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
};
mcbsp2_mux_fck: mcbsp2_mux_fck {
mcbsp2_mux_fck: mcbsp2_mux_fck@4 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_96m_ck>, <&mcbsp_clks>;
......@@ -74,7 +74,7 @@ virt_26m_ck: virt_26m_ck {
clock-frequency = <26000000>;
};
aplls_clkin_ck: aplls_clkin_ck {
aplls_clkin_ck: aplls_clkin_ck@540 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&virt_19200000_ck>, <&virt_26m_ck>, <&virt_13m_ck>, <&virt_12m_ck>;
......@@ -90,7 +90,7 @@ aplls_clkin_x2_ck: aplls_clkin_x2_ck {
clock-div = <1>;
};
osc_ck: osc_ck {
osc_ck: osc_ck@60 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&aplls_clkin_ck>, <&aplls_clkin_x2_ck>;
......@@ -99,7 +99,7 @@ osc_ck: osc_ck {
ti,index-starts-at-one;
};
sys_ck: sys_ck {
sys_ck: sys_ck@60 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&osc_ck>;
......@@ -121,14 +121,14 @@ mcbsp_clks: mcbsp_clks {
clock-frequency = <0x0>;
};
dpll_ck: dpll_ck {
dpll_ck: dpll_ck@500 {
#clock-cells = <0>;
compatible = "ti,omap2-dpll-core-clock";
clocks = <&sys_ck>, <&sys_ck>;
reg = <0x0500>, <0x0540>;
};
apll96_ck: apll96_ck {
apll96_ck: apll96_ck@500 {
#clock-cells = <0>;
compatible = "ti,omap2-apll-clock";
clocks = <&sys_ck>;
......@@ -138,7 +138,7 @@ apll96_ck: apll96_ck {
reg = <0x0500>, <0x0530>, <0x0520>;
};
apll54_ck: apll54_ck {
apll54_ck: apll54_ck@500 {
#clock-cells = <0>;
compatible = "ti,omap2-apll-clock";
clocks = <&sys_ck>;
......@@ -148,7 +148,7 @@ apll54_ck: apll54_ck {
reg = <0x0500>, <0x0530>, <0x0520>;
};
func_54m_ck: func_54m_ck {
func_54m_ck: func_54m_ck@540 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&apll54_ck>, <&alt_ck>;
......@@ -176,7 +176,7 @@ apll96_d2_ck: apll96_d2_ck {
clock-div = <2>;
};
func_48m_ck: func_48m_ck {
func_48m_ck: func_48m_ck@540 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&apll96_d2_ck>, <&alt_ck>;
......@@ -192,7 +192,7 @@ func_12m_ck: func_12m_ck {
clock-div = <4>;
};
sys_clkout_src_gate: sys_clkout_src_gate {
sys_clkout_src_gate: sys_clkout_src_gate@70 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clocks = <&core_ck>;
......@@ -200,7 +200,7 @@ sys_clkout_src_gate: sys_clkout_src_gate {
reg = <0x0070>;
};
sys_clkout_src_mux: sys_clkout_src_mux {
sys_clkout_src_mux: sys_clkout_src_mux@70 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
......@@ -213,7 +213,7 @@ sys_clkout_src: sys_clkout_src {
clocks = <&sys_clkout_src_gate>, <&sys_clkout_src_mux>;
};
sys_clkout: sys_clkout {
sys_clkout: sys_clkout@70 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkout_src>;
......@@ -223,7 +223,7 @@ sys_clkout: sys_clkout {
ti,index-power-of-two;
};
emul_ck: emul_ck {
emul_ck: emul_ck@78 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&func_54m_ck>;
......@@ -231,7 +231,7 @@ emul_ck: emul_ck {
reg = <0x0078>;
};
mpu_ck: mpu_ck {
mpu_ck: mpu_ck@140 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&core_ck>;
......@@ -240,7 +240,7 @@ mpu_ck: mpu_ck {
ti,index-starts-at-one;
};
dsp_gate_fck: dsp_gate_fck {
dsp_gate_fck: dsp_gate_fck@800 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&core_ck>;
......@@ -248,7 +248,7 @@ dsp_gate_fck: dsp_gate_fck {
reg = <0x0800>;
};
dsp_div_fck: dsp_div_fck {
dsp_div_fck: dsp_div_fck@840 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&core_ck>;
......@@ -261,7 +261,7 @@ dsp_fck: dsp_fck {
clocks = <&dsp_gate_fck>, <&dsp_div_fck>;
};
core_l3_ck: core_l3_ck {
core_l3_ck: core_l3_ck@240 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&core_ck>;
......@@ -270,7 +270,7 @@ core_l3_ck: core_l3_ck {
ti,index-starts-at-one;
};
gfx_3d_gate_fck: gfx_3d_gate_fck {
gfx_3d_gate_fck: gfx_3d_gate_fck@300 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&core_l3_ck>;
......@@ -278,7 +278,7 @@ gfx_3d_gate_fck: gfx_3d_gate_fck {
reg = <0x0300>;
};
gfx_3d_div_fck: gfx_3d_div_fck {
gfx_3d_div_fck: gfx_3d_div_fck@340 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&core_l3_ck>;
......@@ -293,7 +293,7 @@ gfx_3d_fck: gfx_3d_fck {
clocks = <&gfx_3d_gate_fck>, <&gfx_3d_div_fck>;
};
gfx_2d_gate_fck: gfx_2d_gate_fck {
gfx_2d_gate_fck: gfx_2d_gate_fck@300 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&core_l3_ck>;
......@@ -301,7 +301,7 @@ gfx_2d_gate_fck: gfx_2d_gate_fck {
reg = <0x0300>;
};
gfx_2d_div_fck: gfx_2d_div_fck {
gfx_2d_div_fck: gfx_2d_div_fck@340 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&core_l3_ck>;
......@@ -316,7 +316,7 @@ gfx_2d_fck: gfx_2d_fck {
clocks = <&gfx_2d_gate_fck>, <&gfx_2d_div_fck>;
};
gfx_ick: gfx_ick {
gfx_ick: gfx_ick@310 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_l3_ck>;
......@@ -324,7 +324,7 @@ gfx_ick: gfx_ick {
reg = <0x0310>;
};
l4_ck: l4_ck {
l4_ck: l4_ck@240 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&core_l3_ck>;
......@@ -334,7 +334,7 @@ l4_ck: l4_ck {
ti,index-starts-at-one;
};
dss_ick: dss_ick {
dss_ick: dss_ick@210 {
#clock-cells = <0>;
compatible = "ti,omap3-no-wait-interface-clock";
clocks = <&l4_ck>;
......@@ -342,7 +342,7 @@ dss_ick: dss_ick {
reg = <0x0210>;
};
dss1_gate_fck: dss1_gate_fck {
dss1_gate_fck: dss1_gate_fck@200 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clocks = <&core_ck>;
......@@ -428,7 +428,7 @@ core_d16_ck: core_d16_ck {
clock-div = <16>;
};
dss1_mux_fck: dss1_mux_fck {
dss1_mux_fck: dss1_mux_fck@240 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&sys_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&core_d5_ck>, <&core_d6_ck>, <&core_d8_ck>, <&core_d9_ck>, <&core_d12_ck>, <&core_d16_ck>;
......@@ -442,7 +442,7 @@ dss1_fck: dss1_fck {
clocks = <&dss1_gate_fck>, <&dss1_mux_fck>;
};
dss2_gate_fck: dss2_gate_fck {
dss2_gate_fck: dss2_gate_fck@200 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clocks = <&func_48m_ck>;
......@@ -450,7 +450,7 @@ dss2_gate_fck: dss2_gate_fck {
reg = <0x0200>;
};
dss2_mux_fck: dss2_mux_fck {
dss2_mux_fck: dss2_mux_fck@240 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&sys_ck>, <&func_48m_ck>;
......@@ -464,7 +464,7 @@ dss2_fck: dss2_fck {
clocks = <&dss2_gate_fck>, <&dss2_mux_fck>;
};
dss_54m_fck: dss_54m_fck {
dss_54m_fck: dss_54m_fck@200 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_54m_ck>;
......@@ -472,7 +472,7 @@ dss_54m_fck: dss_54m_fck {
reg = <0x0200>;
};
ssi_ssr_sst_gate_fck: ssi_ssr_sst_gate_fck {
ssi_ssr_sst_gate_fck: ssi_ssr_sst_gate_fck@204 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&core_ck>;
......@@ -480,7 +480,7 @@ ssi_ssr_sst_gate_fck: ssi_ssr_sst_gate_fck {
reg = <0x0204>;
};
ssi_ssr_sst_div_fck: ssi_ssr_sst_div_fck {
ssi_ssr_sst_div_fck: ssi_ssr_sst_div_fck@240 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&core_ck>;
......@@ -494,7 +494,7 @@ ssi_ssr_sst_fck: ssi_ssr_sst_fck {
clocks = <&ssi_ssr_sst_gate_fck>, <&ssi_ssr_sst_div_fck>;
};
usb_l4_gate_ick: usb_l4_gate_ick {
usb_l4_gate_ick: usb_l4_gate_ick@214 {
#clock-cells = <0>;
compatible = "ti,composite-interface-clock";
clocks = <&core_l3_ck>;
......@@ -502,7 +502,7 @@ usb_l4_gate_ick: usb_l4_gate_ick {
reg = <0x0214>;
};
usb_l4_div_ick: usb_l4_div_ick {
usb_l4_div_ick: usb_l4_div_ick@240 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&core_l3_ck>;
......@@ -517,7 +517,7 @@ usb_l4_ick: usb_l4_ick {
clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
};
ssi_l4_ick: ssi_l4_ick {
ssi_l4_ick: ssi_l4_ick@214 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -525,7 +525,7 @@ ssi_l4_ick: ssi_l4_ick {
reg = <0x0214>;
};
gpt1_ick: gpt1_ick {
gpt1_ick: gpt1_ick@410 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&sys_ck>;
......@@ -533,7 +533,7 @@ gpt1_ick: gpt1_ick {
reg = <0x0410>;
};
gpt1_gate_fck: gpt1_gate_fck {
gpt1_gate_fck: gpt1_gate_fck@400 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&func_32k_ck>;
......@@ -541,7 +541,7 @@ gpt1_gate_fck: gpt1_gate_fck {
reg = <0x0400>;
};
gpt1_mux_fck: gpt1_mux_fck {
gpt1_mux_fck: gpt1_mux_fck@440 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
......@@ -554,7 +554,7 @@ gpt1_fck: gpt1_fck {
clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
};
gpt2_ick: gpt2_ick {
gpt2_ick: gpt2_ick@210 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -562,7 +562,7 @@ gpt2_ick: gpt2_ick {
reg = <0x0210>;
};
gpt2_gate_fck: gpt2_gate_fck {
gpt2_gate_fck: gpt2_gate_fck@200 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&func_32k_ck>;
......@@ -570,7 +570,7 @@ gpt2_gate_fck: gpt2_gate_fck {
reg = <0x0200>;
};
gpt2_mux_fck: gpt2_mux_fck {
gpt2_mux_fck: gpt2_mux_fck@244 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
......@@ -584,7 +584,7 @@ gpt2_fck: gpt2_fck {
clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
};
gpt3_ick: gpt3_ick {
gpt3_ick: gpt3_ick@210 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -592,7 +592,7 @@ gpt3_ick: gpt3_ick {
reg = <0x0210>;
};
gpt3_gate_fck: gpt3_gate_fck {
gpt3_gate_fck: gpt3_gate_fck@200 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&func_32k_ck>;
......@@ -600,7 +600,7 @@ gpt3_gate_fck: gpt3_gate_fck {
reg = <0x0200>;
};
gpt3_mux_fck: gpt3_mux_fck {
gpt3_mux_fck: gpt3_mux_fck@244 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
......@@ -614,7 +614,7 @@ gpt3_fck: gpt3_fck {
clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
};
gpt4_ick: gpt4_ick {
gpt4_ick: gpt4_ick@210 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -622,7 +622,7 @@ gpt4_ick: gpt4_ick {
reg = <0x0210>;
};
gpt4_gate_fck: gpt4_gate_fck {
gpt4_gate_fck: gpt4_gate_fck@200 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&func_32k_ck>;
......@@ -630,7 +630,7 @@ gpt4_gate_fck: gpt4_gate_fck {
reg = <0x0200>;
};
gpt4_mux_fck: gpt4_mux_fck {
gpt4_mux_fck: gpt4_mux_fck@244 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
......@@ -644,7 +644,7 @@ gpt4_fck: gpt4_fck {
clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
};
gpt5_ick: gpt5_ick {
gpt5_ick: gpt5_ick@210 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -652,7 +652,7 @@ gpt5_ick: gpt5_ick {
reg = <0x0210>;
};
gpt5_gate_fck: gpt5_gate_fck {
gpt5_gate_fck: gpt5_gate_fck@200 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&func_32k_ck>;
......@@ -660,7 +660,7 @@ gpt5_gate_fck: gpt5_gate_fck {
reg = <0x0200>;
};
gpt5_mux_fck: gpt5_mux_fck {
gpt5_mux_fck: gpt5_mux_fck@244 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
......@@ -674,7 +674,7 @@ gpt5_fck: gpt5_fck {
clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
};
gpt6_ick: gpt6_ick {
gpt6_ick: gpt6_ick@210 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -682,7 +682,7 @@ gpt6_ick: gpt6_ick {
reg = <0x0210>;
};
gpt6_gate_fck: gpt6_gate_fck {
gpt6_gate_fck: gpt6_gate_fck@200 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&func_32k_ck>;
......@@ -690,7 +690,7 @@ gpt6_gate_fck: gpt6_gate_fck {
reg = <0x0200>;
};
gpt6_mux_fck: gpt6_mux_fck {
gpt6_mux_fck: gpt6_mux_fck@244 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
......@@ -704,7 +704,7 @@ gpt6_fck: gpt6_fck {
clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
};
gpt7_ick: gpt7_ick {
gpt7_ick: gpt7_ick@210 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -712,7 +712,7 @@ gpt7_ick: gpt7_ick {
reg = <0x0210>;
};
gpt7_gate_fck: gpt7_gate_fck {
gpt7_gate_fck: gpt7_gate_fck@200 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&func_32k_ck>;
......@@ -720,7 +720,7 @@ gpt7_gate_fck: gpt7_gate_fck {
reg = <0x0200>;
};
gpt7_mux_fck: gpt7_mux_fck {
gpt7_mux_fck: gpt7_mux_fck@244 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
......@@ -734,7 +734,7 @@ gpt7_fck: gpt7_fck {
clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
};
gpt8_ick: gpt8_ick {
gpt8_ick: gpt8_ick@210 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -742,7 +742,7 @@ gpt8_ick: gpt8_ick {
reg = <0x0210>;
};
gpt8_gate_fck: gpt8_gate_fck {
gpt8_gate_fck: gpt8_gate_fck@200 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&func_32k_ck>;
......@@ -750,7 +750,7 @@ gpt8_gate_fck: gpt8_gate_fck {
reg = <0x0200>;
};
gpt8_mux_fck: gpt8_mux_fck {
gpt8_mux_fck: gpt8_mux_fck@244 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
......@@ -764,7 +764,7 @@ gpt8_fck: gpt8_fck {
clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
};
gpt9_ick: gpt9_ick {
gpt9_ick: gpt9_ick@210 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -772,7 +772,7 @@ gpt9_ick: gpt9_ick {
reg = <0x0210>;
};
gpt9_gate_fck: gpt9_gate_fck {
gpt9_gate_fck: gpt9_gate_fck@200 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&func_32k_ck>;
......@@ -780,7 +780,7 @@ gpt9_gate_fck: gpt9_gate_fck {
reg = <0x0200>;
};
gpt9_mux_fck: gpt9_mux_fck {
gpt9_mux_fck: gpt9_mux_fck@244 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
......@@ -794,7 +794,7 @@ gpt9_fck: gpt9_fck {
clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>;
};
gpt10_ick: gpt10_ick {
gpt10_ick: gpt10_ick@210 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -802,7 +802,7 @@ gpt10_ick: gpt10_ick {
reg = <0x0210>;
};
gpt10_gate_fck: gpt10_gate_fck {
gpt10_gate_fck: gpt10_gate_fck@200 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&func_32k_ck>;
......@@ -810,7 +810,7 @@ gpt10_gate_fck: gpt10_gate_fck {
reg = <0x0200>;
};
gpt10_mux_fck: gpt10_mux_fck {
gpt10_mux_fck: gpt10_mux_fck@244 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
......@@ -824,7 +824,7 @@ gpt10_fck: gpt10_fck {
clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
};
gpt11_ick: gpt11_ick {
gpt11_ick: gpt11_ick@210 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -832,7 +832,7 @@ gpt11_ick: gpt11_ick {
reg = <0x0210>;
};
gpt11_gate_fck: gpt11_gate_fck {
gpt11_gate_fck: gpt11_gate_fck@200 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&func_32k_ck>;
......@@ -840,7 +840,7 @@ gpt11_gate_fck: gpt11_gate_fck {
reg = <0x0200>;
};
gpt11_mux_fck: gpt11_mux_fck {
gpt11_mux_fck: gpt11_mux_fck@244 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
......@@ -854,7 +854,7 @@ gpt11_fck: gpt11_fck {
clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>;
};
gpt12_ick: gpt12_ick {
gpt12_ick: gpt12_ick@210 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -862,7 +862,7 @@ gpt12_ick: gpt12_ick {
reg = <0x0210>;
};
gpt12_gate_fck: gpt12_gate_fck {
gpt12_gate_fck: gpt12_gate_fck@200 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&func_32k_ck>;
......@@ -870,7 +870,7 @@ gpt12_gate_fck: gpt12_gate_fck {
reg = <0x0200>;
};
gpt12_mux_fck: gpt12_mux_fck {
gpt12_mux_fck: gpt12_mux_fck@244 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
......@@ -884,7 +884,7 @@ gpt12_fck: gpt12_fck {
clocks = <&gpt12_gate_fck>, <&gpt12_mux_fck>;
};
mcbsp1_ick: mcbsp1_ick {
mcbsp1_ick: mcbsp1_ick@210 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -892,7 +892,7 @@ mcbsp1_ick: mcbsp1_ick {
reg = <0x0210>;
};
mcbsp1_gate_fck: mcbsp1_gate_fck {
mcbsp1_gate_fck: mcbsp1_gate_fck@200 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&mcbsp_clks>;
......@@ -900,7 +900,7 @@ mcbsp1_gate_fck: mcbsp1_gate_fck {
reg = <0x0200>;
};
mcbsp2_ick: mcbsp2_ick {
mcbsp2_ick: mcbsp2_ick@210 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -908,7 +908,7 @@ mcbsp2_ick: mcbsp2_ick {
reg = <0x0210>;
};
mcbsp2_gate_fck: mcbsp2_gate_fck {
mcbsp2_gate_fck: mcbsp2_gate_fck@200 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&mcbsp_clks>;
......@@ -916,7 +916,7 @@ mcbsp2_gate_fck: mcbsp2_gate_fck {
reg = <0x0200>;
};
mcspi1_ick: mcspi1_ick {
mcspi1_ick: mcspi1_ick@210 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -924,7 +924,7 @@ mcspi1_ick: mcspi1_ick {
reg = <0x0210>;
};
mcspi1_fck: mcspi1_fck {
mcspi1_fck: mcspi1_fck@200 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_48m_ck>;
......@@ -932,7 +932,7 @@ mcspi1_fck: mcspi1_fck {
reg = <0x0200>;
};
mcspi2_ick: mcspi2_ick {
mcspi2_ick: mcspi2_ick@210 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -940,7 +940,7 @@ mcspi2_ick: mcspi2_ick {
reg = <0x0210>;
};
mcspi2_fck: mcspi2_fck {
mcspi2_fck: mcspi2_fck@200 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_48m_ck>;
......@@ -948,7 +948,7 @@ mcspi2_fck: mcspi2_fck {
reg = <0x0200>;
};
uart1_ick: uart1_ick {
uart1_ick: uart1_ick@210 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -956,7 +956,7 @@ uart1_ick: uart1_ick {
reg = <0x0210>;
};
uart1_fck: uart1_fck {
uart1_fck: uart1_fck@200 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_48m_ck>;
......@@ -964,7 +964,7 @@ uart1_fck: uart1_fck {
reg = <0x0200>;
};
uart2_ick: uart2_ick {
uart2_ick: uart2_ick@210 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -972,7 +972,7 @@ uart2_ick: uart2_ick {
reg = <0x0210>;
};
uart2_fck: uart2_fck {
uart2_fck: uart2_fck@200 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_48m_ck>;
......@@ -980,7 +980,7 @@ uart2_fck: uart2_fck {
reg = <0x0200>;
};
uart3_ick: uart3_ick {
uart3_ick: uart3_ick@214 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -988,7 +988,7 @@ uart3_ick: uart3_ick {
reg = <0x0214>;
};
uart3_fck: uart3_fck {
uart3_fck: uart3_fck@204 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_48m_ck>;
......@@ -996,7 +996,7 @@ uart3_fck: uart3_fck {
reg = <0x0204>;
};
gpios_ick: gpios_ick {
gpios_ick: gpios_ick@410 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&sys_ck>;
......@@ -1004,7 +1004,7 @@ gpios_ick: gpios_ick {
reg = <0x0410>;
};
gpios_fck: gpios_fck {
gpios_fck: gpios_fck@400 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_32k_ck>;
......@@ -1012,7 +1012,7 @@ gpios_fck: gpios_fck {
reg = <0x0400>;
};
mpu_wdt_ick: mpu_wdt_ick {
mpu_wdt_ick: mpu_wdt_ick@410 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&sys_ck>;
......@@ -1020,7 +1020,7 @@ mpu_wdt_ick: mpu_wdt_ick {
reg = <0x0410>;
};
mpu_wdt_fck: mpu_wdt_fck {
mpu_wdt_fck: mpu_wdt_fck@400 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_32k_ck>;
......@@ -1028,7 +1028,7 @@ mpu_wdt_fck: mpu_wdt_fck {
reg = <0x0400>;
};
sync_32k_ick: sync_32k_ick {
sync_32k_ick: sync_32k_ick@410 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&sys_ck>;
......@@ -1036,7 +1036,7 @@ sync_32k_ick: sync_32k_ick {
reg = <0x0410>;
};
wdt1_ick: wdt1_ick {
wdt1_ick: wdt1_ick@410 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&sys_ck>;
......@@ -1044,7 +1044,7 @@ wdt1_ick: wdt1_ick {
reg = <0x0410>;
};
omapctrl_ick: omapctrl_ick {
omapctrl_ick: omapctrl_ick@410 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&sys_ck>;
......@@ -1052,7 +1052,7 @@ omapctrl_ick: omapctrl_ick {
reg = <0x0410>;
};
cam_fck: cam_fck {
cam_fck: cam_fck@200 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&func_96m_ck>;
......@@ -1060,7 +1060,7 @@ cam_fck: cam_fck {
reg = <0x0200>;
};
cam_ick: cam_ick {
cam_ick: cam_ick@210 {
#clock-cells = <0>;
compatible = "ti,omap3-no-wait-interface-clock";
clocks = <&l4_ck>;
......@@ -1068,7 +1068,7 @@ cam_ick: cam_ick {
reg = <0x0210>;
};
mailboxes_ick: mailboxes_ick {
mailboxes_ick: mailboxes_ick@210 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -1076,7 +1076,7 @@ mailboxes_ick: mailboxes_ick {
reg = <0x0210>;
};
wdt4_ick: wdt4_ick {
wdt4_ick: wdt4_ick@210 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -1084,7 +1084,7 @@ wdt4_ick: wdt4_ick {
reg = <0x0210>;
};
wdt4_fck: wdt4_fck {
wdt4_fck: wdt4_fck@200 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_32k_ck>;
......@@ -1092,7 +1092,7 @@ wdt4_fck: wdt4_fck {
reg = <0x0200>;
};
mspro_ick: mspro_ick {
mspro_ick: mspro_ick@210 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -1100,7 +1100,7 @@ mspro_ick: mspro_ick {
reg = <0x0210>;
};
mspro_fck: mspro_fck {
mspro_fck: mspro_fck@200 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_96m_ck>;
......@@ -1108,7 +1108,7 @@ mspro_fck: mspro_fck {
reg = <0x0200>;
};
fac_ick: fac_ick {
fac_ick: fac_ick@210 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -1116,7 +1116,7 @@ fac_ick: fac_ick {
reg = <0x0210>;
};
fac_fck: fac_fck {
fac_fck: fac_fck@200 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_12m_ck>;
......@@ -1124,7 +1124,7 @@ fac_fck: fac_fck {
reg = <0x0200>;
};
hdq_ick: hdq_ick {
hdq_ick: hdq_ick@210 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -1132,7 +1132,7 @@ hdq_ick: hdq_ick {
reg = <0x0210>;
};
hdq_fck: hdq_fck {
hdq_fck: hdq_fck@200 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_12m_ck>;
......@@ -1140,7 +1140,7 @@ hdq_fck: hdq_fck {
reg = <0x0200>;
};
i2c1_ick: i2c1_ick {
i2c1_ick: i2c1_ick@210 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -1148,7 +1148,7 @@ i2c1_ick: i2c1_ick {
reg = <0x0210>;
};
i2c2_ick: i2c2_ick {
i2c2_ick: i2c2_ick@210 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -1156,7 +1156,7 @@ i2c2_ick: i2c2_ick {
reg = <0x0210>;
};
gpmc_fck: gpmc_fck {
gpmc_fck: gpmc_fck@238 {
#clock-cells = <0>;
compatible = "ti,fixed-factor-clock";
clocks = <&core_l3_ck>;
......@@ -1174,7 +1174,7 @@ sdma_fck: sdma_fck {
clock-div = <1>;
};
sdma_ick: sdma_ick {
sdma_ick: sdma_ick@238 {
#clock-cells = <0>;
compatible = "ti,fixed-factor-clock";
clocks = <&core_l3_ck>;
......@@ -1184,7 +1184,7 @@ sdma_ick: sdma_ick {
ti,clock-mult = <1>;
};
sdrc_ick: sdrc_ick {
sdrc_ick: sdrc_ick@238 {
#clock-cells = <0>;
compatible = "ti,fixed-factor-clock";
clocks = <&core_l3_ck>;
......@@ -1194,7 +1194,7 @@ sdrc_ick: sdrc_ick {
ti,clock-mult = <1>;
};
des_ick: des_ick {
des_ick: des_ick@21c {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -1202,7 +1202,7 @@ des_ick: des_ick {
reg = <0x021c>;
};
sha_ick: sha_ick {
sha_ick: sha_ick@21c {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -1210,7 +1210,7 @@ sha_ick: sha_ick {
reg = <0x021c>;
};
rng_ick: rng_ick {
rng_ick: rng_ick@21c {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -1218,7 +1218,7 @@ rng_ick: rng_ick {
reg = <0x021c>;
};
aes_ick: aes_ick {
aes_ick: aes_ick@21c {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -1226,7 +1226,7 @@ aes_ick: aes_ick {
reg = <0x021c>;
};
pka_ick: pka_ick {
pka_ick: pka_ick@21c {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l4_ck>;
......@@ -1234,7 +1234,7 @@ pka_ick: pka_ick {
reg = <0x021c>;
};
usb_fck: usb_fck {
usb_fck: usb_fck@204 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&func_48m_ck>;
......
arch/arm/boot/dts/omap3-beagle.dts
View file @ 1ea7c8b6
......@@ -390,6 +390,7 @@ nand@0,0 {
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
ti,nand-ecc-opt = "ham1";
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
nand-bus-width = <16>;
#address-cells = <1>;
#size-cells = <1>;
......
arch/arm/boot/dts/omap3-n9.dts
View file @ 1ea7c8b6
......@@ -57,3 +57,17 @@ csi2a_ep: endpoint {
&modem {
compatible = "nokia,n9-modem";
};
&lis302 {
st,axis-x = <1>; /* LIS3_DEV_X */
st,axis-y = <(-2)>; /* LIS3_INV_DEV_Y */
st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */
st,min-limit-x = <(-46)>;
st,min-limit-y = <3>;
st,min-limit-z = <3>;
st,max-limit-x = <(-3)>;
st,max-limit-y = <46>;
st,max-limit-z = <46>;
};
arch/arm/boot/dts/omap3-n950-n9.dtsi
View file @ 1ea7c8b6
......@@ -14,6 +14,13 @@ / {
cpus {
cpu@0 {
cpu0-supply = <&vcc>;
operating-points = <
/* kHz uV */
300000 1012500
600000 1200000
800000 1325000
1000000 1375000
>;
};
};
......@@ -39,9 +46,34 @@ vwlan_fixed: fixedregulator@2 {
enable-active-high;
regulator-boot-off;
};
leds {
compatible = "gpio-leds";
heartbeat {
label = "debug::sleep";
gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; /* gpio92 */
linux,default-trigger = "default-on";
pinctrl-names = "default";
pinctrl-0 = <&debug_leds>;
};
};
};
&omap3_pmx_core {
accelerator_pins: pinmux_accelerator_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT | MUX_MODE4) /* mcspi2_somi.gpio_180 -> LIS302 INT1 */
OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT | MUX_MODE4) /* mcspi2_cs0.gpio_181 -> LIS302 INT2 */
>;
};
debug_leds: pinmux_debug_led_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE4) /* dss_data22.gpio_92 */
>;
};
mmc2_pins: pinmux_mmc2_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */
......@@ -129,6 +161,30 @@ &twl_gpio {
ti,pulldowns = <0x008106>; /* BIT(1) | BIT(2) | BIT(8) | BIT(15) */
};
&vdac {
regulator-name = "vdac";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
&vpll1 {
regulator-name = "vpll1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
&vpll2 {
regulator-name = "vpll2";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
&vaux1 {
regulator-name = "vaux1";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
/* CSI-2 receiver */
&vaux2 {
regulator-name = "vaux2";
......@@ -143,12 +199,107 @@ &vaux3 {
regulator-max-microvolt = <2800000>;
};
&vaux4 {
regulator-name = "vaux4";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
&vmmc1 {
regulator-name = "vmmc1";
regulator-min-microvolt = <1850000>;
regulator-max-microvolt = <3150000>;
};
&vmmc2 {
regulator-name = "vmmc2";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
};
&vintana1 {
regulator-name = "vintana1";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
};
&vintana2 {
regulator-name = "vintana2";
regulator-min-microvolt = <2750000>;
regulator-max-microvolt = <2750000>;
};
&vintdig {
regulator-name = "vintdig";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
};
&vsim {
regulator-name = "vsim";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
&vio {
regulator-name = "vio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
&i2c2 {
clock-frequency = <400000>;
};
&i2c3 {
clock-frequency = <400000>;
lis302: lis302@1d {
compatible = "st,lis3lv02d";
reg = <0x1d>;
Vdd-supply = <&vaux1>;
Vdd_IO-supply = <&vio>;
pinctrl-names = "default";
pinctrl-0 = <&accelerator_pins>;
interrupts-extended = <&gpio6 20 IRQ_TYPE_EDGE_FALLING>, <&gpio6 21 IRQ_TYPE_EDGE_FALLING>; /* 180, 181 */
/* click flags */
st,click-single-x;
st,click-single-y;
st,click-single-z;
/* Limits are 0.5g * value */
st,click-threshold-x = <8>;
st,click-threshold-y = <8>;
st,click-threshold-z = <10>;
/* Click must be longer than time limit */
st,click-time-limit = <9>;
/* Kind of debounce filter */
st,click-latency = <50>;
st,wakeup-x-hi;
st,wakeup-y-hi;
st,wakeup-threshold = <(800/18)>; /* millig-value / 18 to get HW values */
st,wakeup2-z-hi;
st,wakeup2-threshold = <(1000/18)>; /* millig-value / 18 to get HW values */
st,highpass-cutoff-hz = <2>;
/* Interrupt line 1 for thresholds */
st,irq1-ff-wu-1;
st,irq1-ff-wu-2;
/* Interrupt line 2 for click detection */
st,irq2-click;
st,wu-duration-1 = <8>;
st,wu-duration-2 = <8>;
};
};
&mmc1 {
......
arch/arm/boot/dts/omap3-n950.dts
View file @ 1ea7c8b6
......@@ -11,10 +11,33 @@
/dts-v1/;
#include "omap3-n950-n9.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Nokia N950";
compatible = "nokia,omap3-n950", "ti,omap36xx", "ti,omap3";
keys {
compatible = "gpio-keys";
keypad_slide {
label = "Keypad Slide";
gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; /* 109 */
linux,input-type = <EV_SW>;
linux,code = <SW_KEYPAD_SLIDE>;
wakeup-source;
pinctrl-names = "default";
pinctrl-0 = <&keypad_slide_pins>;
};
};
};
&omap3_pmx_core {
keypad_slide_pins: pinmux_debug_led_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4) /* cam_d10.gpio_109 */
>;
};
};
&omap3_pmx_core {
......@@ -86,3 +109,79 @@ wlcore: wlcore@0 {
&modem {
compatible = "nokia,n950-modem";
};
&twl {
twl_audio: audio {
compatible = "ti,twl4030-audio";
ti,enable-vibra = <1>;
};
};
&twl_keypad {
linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_BACKSLASH)
MATRIX_KEY(0x01, 0x00, KEY_LEFTSHIFT)
MATRIX_KEY(0x02, 0x00, KEY_COMPOSE)
MATRIX_KEY(0x03, 0x00, KEY_LEFTMETA)
MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL)
MATRIX_KEY(0x05, 0x00, KEY_BACKSPACE)
MATRIX_KEY(0x06, 0x00, KEY_VOLUMEDOWN)
MATRIX_KEY(0x07, 0x00, KEY_VOLUMEUP)
MATRIX_KEY(0x03, 0x01, KEY_Z)
MATRIX_KEY(0x04, 0x01, KEY_A)
MATRIX_KEY(0x05, 0x01, KEY_Q)
MATRIX_KEY(0x06, 0x01, KEY_W)
MATRIX_KEY(0x07, 0x01, KEY_E)
MATRIX_KEY(0x03, 0x02, KEY_X)
MATRIX_KEY(0x04, 0x02, KEY_S)
MATRIX_KEY(0x05, 0x02, KEY_D)
MATRIX_KEY(0x06, 0x02, KEY_C)
MATRIX_KEY(0x07, 0x02, KEY_V)
MATRIX_KEY(0x03, 0x03, KEY_O)
MATRIX_KEY(0x04, 0x03, KEY_I)
MATRIX_KEY(0x05, 0x03, KEY_U)
MATRIX_KEY(0x06, 0x03, KEY_L)
MATRIX_KEY(0x07, 0x03, KEY_APOSTROPHE)
MATRIX_KEY(0x03, 0x04, KEY_Y)
MATRIX_KEY(0x04, 0x04, KEY_K)
MATRIX_KEY(0x05, 0x04, KEY_J)
MATRIX_KEY(0x06, 0x04, KEY_H)
MATRIX_KEY(0x07, 0x04, KEY_G)
MATRIX_KEY(0x03, 0x05, KEY_B)
MATRIX_KEY(0x04, 0x05, KEY_COMMA)
MATRIX_KEY(0x05, 0x05, KEY_M)
MATRIX_KEY(0x06, 0x05, KEY_N)
MATRIX_KEY(0x07, 0x05, KEY_DOT)
MATRIX_KEY(0x00, 0x06, KEY_SPACE)
MATRIX_KEY(0x03, 0x06, KEY_T)
MATRIX_KEY(0x04, 0x06, KEY_UP)
MATRIX_KEY(0x05, 0x06, KEY_LEFT)
MATRIX_KEY(0x06, 0x06, KEY_RIGHT)
MATRIX_KEY(0x07, 0x06, KEY_DOWN)
MATRIX_KEY(0x03, 0x07, KEY_P)
MATRIX_KEY(0x04, 0x07, KEY_ENTER)
MATRIX_KEY(0x05, 0x07, KEY_SLASH)
MATRIX_KEY(0x06, 0x07, KEY_F)
MATRIX_KEY(0x07, 0x07, KEY_R)
>;
};
&lis302 {
st,axis-x = <(-2)>; /* LIS3_INV_DEV_Y */
st,axis-y = <(-1)>; /* LIS3_INV_DEV_X */
st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */
st,min-limit-x = <(-32)>;
st,min-limit-y = <3>;
st,min-limit-z = <3>;
st,max-limit-x = <(-3)>;
st,max-limit-y = <32>;
st,max-limit-z = <32>;
};
arch/arm/boot/dts/omap3.dtsi
View file @ 1ea7c8b6
......@@ -43,7 +43,7 @@ cpu@0 {
};
};
pmu {
pmu@54000000 {
compatible = "arm,cortex-a8-pmu";
reg = <0x54000000 0x800000>;
interrupts = <3>;
......@@ -119,7 +119,7 @@ scm_conf: scm_conf@270 {
#size-cells = <1>;
ranges = <0 0x270 0x330>;
pbias_regulator: pbias_regulator {
pbias_regulator: pbias_regulator@2b0 {
compatible = "ti,pbias-omap3", "ti,pbias-omap";
reg = <0x2b0 0x4>;
syscon = <&scm_conf>;
......@@ -725,6 +725,8 @@ gpmc: gpmc@6e000000 {
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
};
usb_otg_hs: usb_otg_hs@480ab000 {
......
arch/arm/boot/dts/omap3430es1-clocks.dtsi
View file @ 1ea7c8b6
......@@ -8,7 +8,7 @@
* published by the Free Software Foundation.
*/
&cm_clocks {
gfx_l3_ck: gfx_l3_ck {
gfx_l3_ck: gfx_l3_ck@b10 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&l3_ick>;
......@@ -16,7 +16,7 @@ gfx_l3_ck: gfx_l3_ck {
ti,bit-shift = <0>;
};
gfx_l3_fck: gfx_l3_fck {
gfx_l3_fck: gfx_l3_fck@b40 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&l3_ick>;
......@@ -33,7 +33,7 @@ gfx_l3_ick: gfx_l3_ick {
clock-div = <1>;
};
gfx_cg1_ck: gfx_cg1_ck {
gfx_cg1_ck: gfx_cg1_ck@b00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&gfx_l3_fck>;
......@@ -41,7 +41,7 @@ gfx_cg1_ck: gfx_cg1_ck {
ti,bit-shift = <1>;
};
gfx_cg2_ck: gfx_cg2_ck {
gfx_cg2_ck: gfx_cg2_ck@b00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&gfx_l3_fck>;
......@@ -49,7 +49,7 @@ gfx_cg2_ck: gfx_cg2_ck {
ti,bit-shift = <2>;
};
d2d_26m_fck: d2d_26m_fck {
d2d_26m_fck: d2d_26m_fck@a00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&sys_ck>;
......@@ -57,7 +57,7 @@ d2d_26m_fck: d2d_26m_fck {
ti,bit-shift = <3>;
};
fshostusb_fck: fshostusb_fck {
fshostusb_fck: fshostusb_fck@a00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_48m_fck>;
......@@ -65,7 +65,7 @@ fshostusb_fck: fshostusb_fck {
ti,bit-shift = <5>;
};
ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1 {
ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1@a00 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clocks = <&corex2_fck>;
......@@ -73,7 +73,7 @@ ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1 {
reg = <0x0a00>;
};
ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1 {
ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1@a40 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&corex2_fck>;
......@@ -96,7 +96,7 @@ ssi_sst_fck: ssi_sst_fck_3430es1 {
clock-div = <2>;
};
hsotgusb_ick_3430es1: hsotgusb_ick_3430es1 {
hsotgusb_ick_3430es1: hsotgusb_ick_3430es1@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-no-wait-interface-clock";
clocks = <&core_l3_ick>;
......@@ -104,7 +104,7 @@ hsotgusb_ick_3430es1: hsotgusb_ick_3430es1 {
ti,bit-shift = <4>;
};
fac_ick: fac_ick {
fac_ick: fac_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -120,7 +120,7 @@ ssi_l4_ick: ssi_l4_ick {
clock-div = <1>;
};
ssi_ick: ssi_ick_3430es1 {
ssi_ick: ssi_ick_3430es1@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-no-wait-interface-clock";
clocks = <&ssi_l4_ick>;
......@@ -128,7 +128,7 @@ ssi_ick: ssi_ick_3430es1 {
ti,bit-shift = <0>;
};
usb_l4_gate_ick: usb_l4_gate_ick {
usb_l4_gate_ick: usb_l4_gate_ick@a10 {
#clock-cells = <0>;
compatible = "ti,composite-interface-clock";
clocks = <&l4_ick>;
......@@ -136,7 +136,7 @@ usb_l4_gate_ick: usb_l4_gate_ick {
reg = <0x0a10>;
};
usb_l4_div_ick: usb_l4_div_ick {
usb_l4_div_ick: usb_l4_div_ick@a40 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&l4_ick>;
......@@ -152,7 +152,7 @@ usb_l4_ick: usb_l4_ick {
clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
};
dss1_alwon_fck: dss1_alwon_fck_3430es1 {
dss1_alwon_fck: dss1_alwon_fck_3430es1@e00 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll4_m4x2_ck>;
......@@ -161,7 +161,7 @@ dss1_alwon_fck: dss1_alwon_fck_3430es1 {
ti,set-rate-parent;
};
dss_ick: dss_ick_3430es1 {
dss_ick: dss_ick_3430es1@e10 {
#clock-cells = <0>;
compatible = "ti,omap3-no-wait-interface-clock";
clocks = <&l4_ick>;
......
arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
View file @ 1ea7c8b6
......@@ -16,7 +16,7 @@ security_l4_ick2: security_l4_ick2 {
clock-div = <1>;
};
aes1_ick: aes1_ick {
aes1_ick: aes1_ick@a14 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&security_l4_ick2>;
......@@ -24,7 +24,7 @@ aes1_ick: aes1_ick {
reg = <0x0a14>;
};
rng_ick: rng_ick {
rng_ick: rng_ick@a14 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&security_l4_ick2>;
......@@ -32,7 +32,7 @@ rng_ick: rng_ick {
ti,bit-shift = <2>;
};
sha11_ick: sha11_ick {
sha11_ick: sha11_ick@a14 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&security_l4_ick2>;
......@@ -40,7 +40,7 @@ sha11_ick: sha11_ick {
ti,bit-shift = <1>;
};
des1_ick: des1_ick {
des1_ick: des1_ick@a14 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&security_l4_ick2>;
......@@ -48,7 +48,7 @@ des1_ick: des1_ick {
ti,bit-shift = <0>;
};
cam_mclk: cam_mclk {
cam_mclk: cam_mclk@f00 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll4_m5x2_ck>;
......@@ -57,7 +57,7 @@ cam_mclk: cam_mclk {
ti,set-rate-parent;
};
cam_ick: cam_ick {
cam_ick: cam_ick@f10 {
#clock-cells = <0>;
compatible = "ti,omap3-no-wait-interface-clock";
clocks = <&l4_ick>;
......@@ -65,7 +65,7 @@ cam_ick: cam_ick {
ti,bit-shift = <0>;
};
csi2_96m_fck: csi2_96m_fck {
csi2_96m_fck: csi2_96m_fck@f00 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&core_96m_fck>;
......@@ -81,7 +81,7 @@ security_l3_ick: security_l3_ick {
clock-div = <1>;
};
pka_ick: pka_ick {
pka_ick: pka_ick@a14 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&security_l3_ick>;
......@@ -89,7 +89,7 @@ pka_ick: pka_ick {
ti,bit-shift = <4>;
};
icr_ick: icr_ick {
icr_ick: icr_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -97,7 +97,7 @@ icr_ick: icr_ick {
ti,bit-shift = <29>;
};
des2_ick: des2_ick {
des2_ick: des2_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -105,7 +105,7 @@ des2_ick: des2_ick {
ti,bit-shift = <26>;
};
mspro_ick: mspro_ick {
mspro_ick: mspro_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -113,7 +113,7 @@ mspro_ick: mspro_ick {
ti,bit-shift = <23>;
};
mailboxes_ick: mailboxes_ick {
mailboxes_ick: mailboxes_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -129,7 +129,7 @@ ssi_l4_ick: ssi_l4_ick {
clock-div = <1>;
};
sr1_fck: sr1_fck {
sr1_fck: sr1_fck@c00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&sys_ck>;
......@@ -137,7 +137,7 @@ sr1_fck: sr1_fck {
ti,bit-shift = <6>;
};
sr2_fck: sr2_fck {
sr2_fck: sr2_fck@c00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&sys_ck>;
......@@ -153,7 +153,7 @@ sr_l4_ick: sr_l4_ick {
clock-div = <1>;
};
dpll2_fck: dpll2_fck {
dpll2_fck: dpll2_fck@40 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&core_ck>;
......@@ -163,7 +163,7 @@ dpll2_fck: dpll2_fck {
ti,index-starts-at-one;
};
dpll2_ck: dpll2_ck {
dpll2_ck: dpll2_ck@4 {
#clock-cells = <0>;
compatible = "ti,omap3-dpll-clock";
clocks = <&sys_ck>, <&dpll2_fck>;
......@@ -173,7 +173,7 @@ dpll2_ck: dpll2_ck {
ti,low-power-bypass;
};
dpll2_m2_ck: dpll2_m2_ck {
dpll2_m2_ck: dpll2_m2_ck@44 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll2_ck>;
......@@ -182,7 +182,7 @@ dpll2_m2_ck: dpll2_m2_ck {
ti,index-starts-at-one;
};
iva2_ck: iva2_ck {
iva2_ck: iva2_ck@0 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&dpll2_m2_ck>;
......@@ -190,7 +190,7 @@ iva2_ck: iva2_ck {
ti,bit-shift = <0>;
};
modem_fck: modem_fck {
modem_fck: modem_fck@a00 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&sys_ck>;
......@@ -198,7 +198,7 @@ modem_fck: modem_fck {
ti,bit-shift = <31>;
};
sad2d_ick: sad2d_ick {
sad2d_ick: sad2d_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l3_ick>;
......@@ -206,7 +206,7 @@ sad2d_ick: sad2d_ick {
ti,bit-shift = <3>;
};
mad2d_ick: mad2d_ick {
mad2d_ick: mad2d_ick@a18 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&l3_ick>;
......@@ -214,7 +214,7 @@ mad2d_ick: mad2d_ick {
ti,bit-shift = <3>;
};
mspro_fck: mspro_fck {
mspro_fck: mspro_fck@a00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_96m_fck>;
......
arch/arm/boot/dts/omap34xx.dtsi
View file @ 1ea7c8b6
......@@ -55,7 +55,7 @@ ports {
};
};
bandgap {
bandgap@48002524 {
reg = <0x48002524 0x4>;
compatible = "ti,omap34xx-bandgap";
#thermal-sensor-cells = <0>;
......
arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
View file @ 1ea7c8b6
......@@ -25,7 +25,7 @@ corex2_d5_fck: corex2_d5_fck {
};
};
&cm_clocks {
dpll5_ck: dpll5_ck {
dpll5_ck: dpll5_ck@d04 {
#clock-cells = <0>;
compatible = "ti,omap3-dpll-clock";
clocks = <&sys_ck>, <&sys_ck>;
......@@ -34,7 +34,7 @@ dpll5_ck: dpll5_ck {
ti,lock;
};
dpll5_m2_ck: dpll5_m2_ck {
dpll5_m2_ck: dpll5_m2_ck@d50 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll5_ck>;
......@@ -43,7 +43,7 @@ dpll5_m2_ck: dpll5_m2_ck {
ti,index-starts-at-one;
};
sgx_gate_fck: sgx_gate_fck {
sgx_gate_fck: sgx_gate_fck@b00 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&core_ck>;
......@@ -91,7 +91,7 @@ core_d2_ck: core_d2_ck {
clock-div = <2>;
};
sgx_mux_fck: sgx_mux_fck {
sgx_mux_fck: sgx_mux_fck@b40 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
......@@ -104,7 +104,7 @@ sgx_fck: sgx_fck {
clocks = <&sgx_gate_fck>, <&sgx_mux_fck>;
};
sgx_ick: sgx_ick {
sgx_ick: sgx_ick@b10 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&l3_ick>;
......@@ -112,7 +112,7 @@ sgx_ick: sgx_ick {
ti,bit-shift = <0>;
};
cpefuse_fck: cpefuse_fck {
cpefuse_fck: cpefuse_fck@a08 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_ck>;
......@@ -120,7 +120,7 @@ cpefuse_fck: cpefuse_fck {
ti,bit-shift = <0>;
};
ts_fck: ts_fck {
ts_fck: ts_fck@a08 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&omap_32k_fck>;
......@@ -128,7 +128,7 @@ ts_fck: ts_fck {
ti,bit-shift = <1>;
};
usbtll_fck: usbtll_fck {
usbtll_fck: usbtll_fck@a08 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&dpll5_m2_ck>;
......@@ -136,7 +136,7 @@ usbtll_fck: usbtll_fck {
ti,bit-shift = <2>;
};
usbtll_ick: usbtll_ick {
usbtll_ick: usbtll_ick@a18 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -144,7 +144,7 @@ usbtll_ick: usbtll_ick {
ti,bit-shift = <2>;
};
mmchs3_ick: mmchs3_ick {
mmchs3_ick: mmchs3_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -152,7 +152,7 @@ mmchs3_ick: mmchs3_ick {
ti,bit-shift = <30>;
};
mmchs3_fck: mmchs3_fck {
mmchs3_fck: mmchs3_fck@a00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_96m_fck>;
......@@ -160,7 +160,7 @@ mmchs3_fck: mmchs3_fck {
ti,bit-shift = <30>;
};
dss1_alwon_fck: dss1_alwon_fck_3430es2 {
dss1_alwon_fck: dss1_alwon_fck_3430es2@e00 {
#clock-cells = <0>;
compatible = "ti,dss-gate-clock";
clocks = <&dpll4_m4x2_ck>;
......@@ -169,7 +169,7 @@ dss1_alwon_fck: dss1_alwon_fck_3430es2 {
ti,set-rate-parent;
};
dss_ick: dss_ick_3430es2 {
dss_ick: dss_ick_3430es2@e10 {
#clock-cells = <0>;
compatible = "ti,omap3-dss-interface-clock";
clocks = <&l4_ick>;
......@@ -177,7 +177,7 @@ dss_ick: dss_ick_3430es2 {
ti,bit-shift = <0>;
};
usbhost_120m_fck: usbhost_120m_fck {
usbhost_120m_fck: usbhost_120m_fck@1400 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll5_m2_ck>;
......@@ -185,7 +185,7 @@ usbhost_120m_fck: usbhost_120m_fck {
ti,bit-shift = <1>;
};
usbhost_48m_fck: usbhost_48m_fck {
usbhost_48m_fck: usbhost_48m_fck@1400 {
#clock-cells = <0>;
compatible = "ti,dss-gate-clock";
clocks = <&omap_48m_fck>;
......@@ -193,7 +193,7 @@ usbhost_48m_fck: usbhost_48m_fck {
ti,bit-shift = <0>;
};
usbhost_ick: usbhost_ick {
usbhost_ick: usbhost_ick@1410 {
#clock-cells = <0>;
compatible = "ti,omap3-dss-interface-clock";
clocks = <&l4_ick>;
......
arch/arm/boot/dts/omap36xx-clocks.dtsi
View file @ 1ea7c8b6
......@@ -8,14 +8,14 @@
* published by the Free Software Foundation.
*/
&cm_clocks {
dpll4_ck: dpll4_ck {
dpll4_ck: dpll4_ck@d00 {
#clock-cells = <0>;
compatible = "ti,omap3-dpll-per-j-type-clock";
clocks = <&sys_ck>, <&sys_ck>;
reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
};
dpll4_m5x2_ck: dpll4_m5x2_ck {
dpll4_m5x2_ck: dpll4_m5x2_ck@d00 {
#clock-cells = <0>;
compatible = "ti,hsdiv-gate-clock";
clocks = <&dpll4_m5x2_mul_ck>;
......@@ -25,7 +25,7 @@ dpll4_m5x2_ck: dpll4_m5x2_ck {
ti,set-bit-to-disable;
};
dpll4_m2x2_ck: dpll4_m2x2_ck {
dpll4_m2x2_ck: dpll4_m2x2_ck@d00 {
#clock-cells = <0>;
compatible = "ti,hsdiv-gate-clock";
clocks = <&dpll4_m2x2_mul_ck>;
......@@ -34,7 +34,7 @@ dpll4_m2x2_ck: dpll4_m2x2_ck {
ti,set-bit-to-disable;
};
dpll3_m3x2_ck: dpll3_m3x2_ck {
dpll3_m3x2_ck: dpll3_m3x2_ck@d00 {
#clock-cells = <0>;
compatible = "ti,hsdiv-gate-clock";
clocks = <&dpll3_m3x2_mul_ck>;
......@@ -43,7 +43,7 @@ dpll3_m3x2_ck: dpll3_m3x2_ck {
ti,set-bit-to-disable;
};
dpll4_m3x2_ck: dpll4_m3x2_ck {
dpll4_m3x2_ck: dpll4_m3x2_ck@d00 {
#clock-cells = <0>;
compatible = "ti,hsdiv-gate-clock";
clocks = <&dpll4_m3x2_mul_ck>;
......@@ -52,7 +52,7 @@ dpll4_m3x2_ck: dpll4_m3x2_ck {
ti,set-bit-to-disable;
};
dpll4_m6x2_ck: dpll4_m6x2_ck {
dpll4_m6x2_ck: dpll4_m6x2_ck@d00 {
#clock-cells = <0>;
compatible = "ti,hsdiv-gate-clock";
clocks = <&dpll4_m6x2_mul_ck>;
......@@ -61,7 +61,7 @@ dpll4_m6x2_ck: dpll4_m6x2_ck {
ti,set-bit-to-disable;
};
uart4_fck: uart4_fck {
uart4_fck: uart4_fck@1000 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&per_48m_fck>;
......
arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
View file @ 1ea7c8b6
......@@ -8,7 +8,7 @@
* published by the Free Software Foundation.
*/
&cm_clocks {
ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2 {
ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2@a00 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clocks = <&corex2_fck>;
......@@ -16,7 +16,7 @@ ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2 {
reg = <0x0a00>;
};
ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 {
ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@a40 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&corex2_fck>;
......@@ -39,7 +39,7 @@ ssi_sst_fck: ssi_sst_fck_3430es2 {
clock-div = <2>;
};
hsotgusb_ick_3430es2: hsotgusb_ick_3430es2 {
hsotgusb_ick_3430es2: hsotgusb_ick_3430es2@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-hsotgusb-interface-clock";
clocks = <&core_l3_ick>;
......@@ -55,7 +55,7 @@ ssi_l4_ick: ssi_l4_ick {
clock-div = <1>;
};
ssi_ick: ssi_ick_3430es2 {
ssi_ick: ssi_ick_3430es2@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-ssi-interface-clock";
clocks = <&ssi_l4_ick>;
......@@ -63,7 +63,7 @@ ssi_ick: ssi_ick_3430es2 {
ti,bit-shift = <0>;
};
usim_gate_fck: usim_gate_fck {
usim_gate_fck: usim_gate_fck@c00 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&omap_96m_fck>;
......@@ -143,7 +143,7 @@ dpll5_m2_d20_ck: dpll5_m2_d20_ck {
clock-div = <20>;
};
usim_mux_fck: usim_mux_fck {
usim_mux_fck: usim_mux_fck@c40 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
......@@ -158,7 +158,7 @@ usim_fck: usim_fck {
clocks = <&usim_gate_fck>, <&usim_mux_fck>;
};
usim_ick: usim_ick {
usim_ick: usim_ick@c10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&wkup_l4_ick>;
......
arch/arm/boot/dts/omap36xx.dtsi
View file @ 1ea7c8b6
......@@ -87,7 +87,7 @@ ports {
};
};
bandgap {
bandgap@48002524 {
reg = <0x48002524 0x4>;
compatible = "ti,omap36xx-bandgap";
#thermal-sensor-cells = <0>;
......
arch/arm/boot/dts/omap3xxx-clocks.dtsi
View file @ 1ea7c8b6
......@@ -14,14 +14,14 @@ virt_16_8m_ck: virt_16_8m_ck {
clock-frequency = <16800000>;
};
osc_sys_ck: osc_sys_ck {
osc_sys_ck: osc_sys_ck@d40 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>;
reg = <0x0d40>;
};
sys_ck: sys_ck {
sys_ck: sys_ck@1270 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&osc_sys_ck>;
......@@ -31,7 +31,7 @@ sys_ck: sys_ck {
ti,index-starts-at-one;
};
sys_clkout1: sys_clkout1 {
sys_clkout1: sys_clkout1@d70 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&osc_sys_ck>;
......@@ -81,7 +81,7 @@ wkup_l4_ick: wkup_l4_ick {
};
&scm_clocks {
mcbsp5_mux_fck: mcbsp5_mux_fck {
mcbsp5_mux_fck: mcbsp5_mux_fck@68 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&core_96m_fck>, <&mcbsp_clks>;
......@@ -95,7 +95,7 @@ mcbsp5_fck: mcbsp5_fck {
clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
};
mcbsp1_mux_fck: mcbsp1_mux_fck {
mcbsp1_mux_fck: mcbsp1_mux_fck@4 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&core_96m_fck>, <&mcbsp_clks>;
......@@ -109,7 +109,7 @@ mcbsp1_fck: mcbsp1_fck {
clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
};
mcbsp2_mux_fck: mcbsp2_mux_fck {
mcbsp2_mux_fck: mcbsp2_mux_fck@4 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&per_96m_fck>, <&mcbsp_clks>;
......@@ -123,7 +123,7 @@ mcbsp2_fck: mcbsp2_fck {
clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
};
mcbsp3_mux_fck: mcbsp3_mux_fck {
mcbsp3_mux_fck: mcbsp3_mux_fck@68 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&per_96m_fck>, <&mcbsp_clks>;
......@@ -136,7 +136,7 @@ mcbsp3_fck: mcbsp3_fck {
clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
};
mcbsp4_mux_fck: mcbsp4_mux_fck {
mcbsp4_mux_fck: mcbsp4_mux_fck@68 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&per_96m_fck>, <&mcbsp_clks>;
......@@ -193,14 +193,14 @@ virt_38_4m_ck: virt_38_4m_ck {
clock-frequency = <38400000>;
};
dpll4_ck: dpll4_ck {
dpll4_ck: dpll4_ck@d00 {
#clock-cells = <0>;
compatible = "ti,omap3-dpll-per-clock";
clocks = <&sys_ck>, <&sys_ck>;
reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
};
dpll4_m2_ck: dpll4_m2_ck {
dpll4_m2_ck: dpll4_m2_ck@d48 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll4_ck>;
......@@ -217,7 +217,7 @@ dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck {
clock-div = <1>;
};
dpll4_m2x2_ck: dpll4_m2x2_ck {
dpll4_m2x2_ck: dpll4_m2x2_ck@d00 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll4_m2x2_mul_ck>;
......@@ -234,14 +234,14 @@ omap_96m_alwon_fck: omap_96m_alwon_fck {
clock-div = <1>;
};
dpll3_ck: dpll3_ck {
dpll3_ck: dpll3_ck@d00 {
#clock-cells = <0>;
compatible = "ti,omap3-dpll-core-clock";
clocks = <&sys_ck>, <&sys_ck>;
reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>;
};
dpll3_m3_ck: dpll3_m3_ck {
dpll3_m3_ck: dpll3_m3_ck@1140 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll3_ck>;
......@@ -259,7 +259,7 @@ dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck {
clock-div = <1>;
};
dpll3_m3x2_ck: dpll3_m3x2_ck {
dpll3_m3x2_ck: dpll3_m3x2_ck@d00 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll3_m3x2_mul_ck>;
......@@ -288,7 +288,7 @@ mcbsp_clks: mcbsp_clks {
clock-frequency = <0x0>;
};
dpll3_m2_ck: dpll3_m2_ck {
dpll3_m2_ck: dpll3_m2_ck@d40 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll3_ck>;
......@@ -306,7 +306,7 @@ core_ck: core_ck {
clock-div = <1>;
};
dpll1_fck: dpll1_fck {
dpll1_fck: dpll1_fck@940 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&core_ck>;
......@@ -316,7 +316,7 @@ dpll1_fck: dpll1_fck {
ti,index-starts-at-one;
};
dpll1_ck: dpll1_ck {
dpll1_ck: dpll1_ck@904 {
#clock-cells = <0>;
compatible = "ti,omap3-dpll-clock";
clocks = <&sys_ck>, <&dpll1_fck>;
......@@ -331,7 +331,7 @@ dpll1_x2_ck: dpll1_x2_ck {
clock-div = <1>;
};
dpll1_x2m2_ck: dpll1_x2m2_ck {
dpll1_x2m2_ck: dpll1_x2m2_ck@944 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll1_x2_ck>;
......@@ -348,7 +348,7 @@ cm_96m_fck: cm_96m_fck {
clock-div = <1>;
};
omap_96m_fck: omap_96m_fck {
omap_96m_fck: omap_96m_fck@d40 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&cm_96m_fck>, <&sys_ck>;
......@@ -356,7 +356,7 @@ omap_96m_fck: omap_96m_fck {
reg = <0x0d40>;
};
dpll4_m3_ck: dpll4_m3_ck {
dpll4_m3_ck: dpll4_m3_ck@e40 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll4_ck>;
......@@ -374,7 +374,7 @@ dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck {
clock-div = <1>;
};
dpll4_m3x2_ck: dpll4_m3x2_ck {
dpll4_m3x2_ck: dpll4_m3x2_ck@d00 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll4_m3x2_mul_ck>;
......@@ -383,7 +383,7 @@ dpll4_m3x2_ck: dpll4_m3x2_ck {
ti,set-bit-to-disable;
};
omap_54m_fck: omap_54m_fck {
omap_54m_fck: omap_54m_fck@d40 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
......@@ -399,7 +399,7 @@ cm_96m_d2_fck: cm_96m_d2_fck {
clock-div = <2>;
};
omap_48m_fck: omap_48m_fck {
omap_48m_fck: omap_48m_fck@d40 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
......@@ -415,7 +415,7 @@ omap_12m_fck: omap_12m_fck {
clock-div = <4>;
};
dpll4_m4_ck: dpll4_m4_ck {
dpll4_m4_ck: dpll4_m4_ck@e40 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll4_ck>;
......@@ -433,7 +433,7 @@ dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
ti,set-rate-parent;
};
dpll4_m4x2_ck: dpll4_m4x2_ck {
dpll4_m4x2_ck: dpll4_m4x2_ck@d00 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll4_m4x2_mul_ck>;
......@@ -443,7 +443,7 @@ dpll4_m4x2_ck: dpll4_m4x2_ck {
ti,set-rate-parent;
};
dpll4_m5_ck: dpll4_m5_ck {
dpll4_m5_ck: dpll4_m5_ck@f40 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll4_ck>;
......@@ -461,7 +461,7 @@ dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck {
ti,set-rate-parent;
};
dpll4_m5x2_ck: dpll4_m5x2_ck {
dpll4_m5x2_ck: dpll4_m5x2_ck@d00 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll4_m5x2_mul_ck>;
......@@ -471,7 +471,7 @@ dpll4_m5x2_ck: dpll4_m5x2_ck {
ti,set-rate-parent;
};
dpll4_m6_ck: dpll4_m6_ck {
dpll4_m6_ck: dpll4_m6_ck@1140 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll4_ck>;
......@@ -489,7 +489,7 @@ dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck {
clock-div = <1>;
};
dpll4_m6x2_ck: dpll4_m6x2_ck {
dpll4_m6x2_ck: dpll4_m6x2_ck@d00 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll4_m6x2_mul_ck>;
......@@ -506,7 +506,7 @@ emu_per_alwon_ck: emu_per_alwon_ck {
clock-div = <1>;
};
clkout2_src_gate_ck: clkout2_src_gate_ck {
clkout2_src_gate_ck: clkout2_src_gate_ck@d70 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clocks = <&core_ck>;
......@@ -514,7 +514,7 @@ clkout2_src_gate_ck: clkout2_src_gate_ck {
reg = <0x0d70>;
};
clkout2_src_mux_ck: clkout2_src_mux_ck {
clkout2_src_mux_ck: clkout2_src_mux_ck@d70 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;
......@@ -527,7 +527,7 @@ clkout2_src_ck: clkout2_src_ck {
clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>;
};
sys_clkout2: sys_clkout2 {
sys_clkout2: sys_clkout2@d70 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&clkout2_src_ck>;
......@@ -545,7 +545,7 @@ mpu_ck: mpu_ck {
clock-div = <1>;
};
arm_fck: arm_fck {
arm_fck: arm_fck@924 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mpu_ck>;
......@@ -561,7 +561,7 @@ emu_mpu_alwon_ck: emu_mpu_alwon_ck {
clock-div = <1>;
};
l3_ick: l3_ick {
l3_ick: l3_ick@a40 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&core_ck>;
......@@ -570,7 +570,7 @@ l3_ick: l3_ick {
ti,index-starts-at-one;
};
l4_ick: l4_ick {
l4_ick: l4_ick@a40 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&l3_ick>;
......@@ -580,7 +580,7 @@ l4_ick: l4_ick {
ti,index-starts-at-one;
};
rm_ick: rm_ick {
rm_ick: rm_ick@c40 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&l4_ick>;
......@@ -590,7 +590,7 @@ rm_ick: rm_ick {
ti,index-starts-at-one;
};
gpt10_gate_fck: gpt10_gate_fck {
gpt10_gate_fck: gpt10_gate_fck@a00 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&sys_ck>;
......@@ -598,7 +598,7 @@ gpt10_gate_fck: gpt10_gate_fck {
reg = <0x0a00>;
};
gpt10_mux_fck: gpt10_mux_fck {
gpt10_mux_fck: gpt10_mux_fck@a40 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&omap_32k_fck>, <&sys_ck>;
......@@ -612,7 +612,7 @@ gpt10_fck: gpt10_fck {
clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
};
gpt11_gate_fck: gpt11_gate_fck {
gpt11_gate_fck: gpt11_gate_fck@a00 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&sys_ck>;
......@@ -620,7 +620,7 @@ gpt11_gate_fck: gpt11_gate_fck {
reg = <0x0a00>;
};
gpt11_mux_fck: gpt11_mux_fck {
gpt11_mux_fck: gpt11_mux_fck@a40 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&omap_32k_fck>, <&sys_ck>;
......@@ -642,7 +642,7 @@ core_96m_fck: core_96m_fck {
clock-div = <1>;
};
mmchs2_fck: mmchs2_fck {
mmchs2_fck: mmchs2_fck@a00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_96m_fck>;
......@@ -650,7 +650,7 @@ mmchs2_fck: mmchs2_fck {
ti,bit-shift = <25>;
};
mmchs1_fck: mmchs1_fck {
mmchs1_fck: mmchs1_fck@a00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_96m_fck>;
......@@ -658,7 +658,7 @@ mmchs1_fck: mmchs1_fck {
ti,bit-shift = <24>;
};
i2c3_fck: i2c3_fck {
i2c3_fck: i2c3_fck@a00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_96m_fck>;
......@@ -666,7 +666,7 @@ i2c3_fck: i2c3_fck {
ti,bit-shift = <17>;
};
i2c2_fck: i2c2_fck {
i2c2_fck: i2c2_fck@a00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_96m_fck>;
......@@ -674,7 +674,7 @@ i2c2_fck: i2c2_fck {
ti,bit-shift = <16>;
};
i2c1_fck: i2c1_fck {
i2c1_fck: i2c1_fck@a00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_96m_fck>;
......@@ -682,7 +682,7 @@ i2c1_fck: i2c1_fck {
ti,bit-shift = <15>;
};
mcbsp5_gate_fck: mcbsp5_gate_fck {
mcbsp5_gate_fck: mcbsp5_gate_fck@a00 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&mcbsp_clks>;
......@@ -690,7 +690,7 @@ mcbsp5_gate_fck: mcbsp5_gate_fck {
reg = <0x0a00>;
};
mcbsp1_gate_fck: mcbsp1_gate_fck {
mcbsp1_gate_fck: mcbsp1_gate_fck@a00 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&mcbsp_clks>;
......@@ -706,7 +706,7 @@ core_48m_fck: core_48m_fck {
clock-div = <1>;
};
mcspi4_fck: mcspi4_fck {
mcspi4_fck: mcspi4_fck@a00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_48m_fck>;
......@@ -714,7 +714,7 @@ mcspi4_fck: mcspi4_fck {
ti,bit-shift = <21>;
};
mcspi3_fck: mcspi3_fck {
mcspi3_fck: mcspi3_fck@a00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_48m_fck>;
......@@ -722,7 +722,7 @@ mcspi3_fck: mcspi3_fck {
ti,bit-shift = <20>;
};
mcspi2_fck: mcspi2_fck {
mcspi2_fck: mcspi2_fck@a00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_48m_fck>;
......@@ -730,7 +730,7 @@ mcspi2_fck: mcspi2_fck {
ti,bit-shift = <19>;
};
mcspi1_fck: mcspi1_fck {
mcspi1_fck: mcspi1_fck@a00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_48m_fck>;
......@@ -738,7 +738,7 @@ mcspi1_fck: mcspi1_fck {
ti,bit-shift = <18>;
};
uart2_fck: uart2_fck {
uart2_fck: uart2_fck@a00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_48m_fck>;
......@@ -746,7 +746,7 @@ uart2_fck: uart2_fck {
ti,bit-shift = <14>;
};
uart1_fck: uart1_fck {
uart1_fck: uart1_fck@a00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_48m_fck>;
......@@ -762,7 +762,7 @@ core_12m_fck: core_12m_fck {
clock-div = <1>;
};
hdq_fck: hdq_fck {
hdq_fck: hdq_fck@a00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_12m_fck>;
......@@ -778,7 +778,7 @@ core_l3_ick: core_l3_ick {
clock-div = <1>;
};
sdrc_ick: sdrc_ick {
sdrc_ick: sdrc_ick@a10 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&core_l3_ick>;
......@@ -802,7 +802,7 @@ core_l4_ick: core_l4_ick {
clock-div = <1>;
};
mmchs2_ick: mmchs2_ick {
mmchs2_ick: mmchs2_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -810,7 +810,7 @@ mmchs2_ick: mmchs2_ick {
ti,bit-shift = <25>;
};
mmchs1_ick: mmchs1_ick {
mmchs1_ick: mmchs1_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -818,7 +818,7 @@ mmchs1_ick: mmchs1_ick {
ti,bit-shift = <24>;
};
hdq_ick: hdq_ick {
hdq_ick: hdq_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -826,7 +826,7 @@ hdq_ick: hdq_ick {
ti,bit-shift = <22>;
};
mcspi4_ick: mcspi4_ick {
mcspi4_ick: mcspi4_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -834,7 +834,7 @@ mcspi4_ick: mcspi4_ick {
ti,bit-shift = <21>;
};
mcspi3_ick: mcspi3_ick {
mcspi3_ick: mcspi3_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -842,7 +842,7 @@ mcspi3_ick: mcspi3_ick {
ti,bit-shift = <20>;
};
mcspi2_ick: mcspi2_ick {
mcspi2_ick: mcspi2_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -850,7 +850,7 @@ mcspi2_ick: mcspi2_ick {
ti,bit-shift = <19>;
};
mcspi1_ick: mcspi1_ick {
mcspi1_ick: mcspi1_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -858,7 +858,7 @@ mcspi1_ick: mcspi1_ick {
ti,bit-shift = <18>;
};
i2c3_ick: i2c3_ick {
i2c3_ick: i2c3_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -866,7 +866,7 @@ i2c3_ick: i2c3_ick {
ti,bit-shift = <17>;
};
i2c2_ick: i2c2_ick {
i2c2_ick: i2c2_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -874,7 +874,7 @@ i2c2_ick: i2c2_ick {
ti,bit-shift = <16>;
};
i2c1_ick: i2c1_ick {
i2c1_ick: i2c1_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -882,7 +882,7 @@ i2c1_ick: i2c1_ick {
ti,bit-shift = <15>;
};
uart2_ick: uart2_ick {
uart2_ick: uart2_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -890,7 +890,7 @@ uart2_ick: uart2_ick {
ti,bit-shift = <14>;
};
uart1_ick: uart1_ick {
uart1_ick: uart1_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -898,7 +898,7 @@ uart1_ick: uart1_ick {
ti,bit-shift = <13>;
};
gpt11_ick: gpt11_ick {
gpt11_ick: gpt11_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -906,7 +906,7 @@ gpt11_ick: gpt11_ick {
ti,bit-shift = <12>;
};
gpt10_ick: gpt10_ick {
gpt10_ick: gpt10_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -914,7 +914,7 @@ gpt10_ick: gpt10_ick {
ti,bit-shift = <11>;
};
mcbsp5_ick: mcbsp5_ick {
mcbsp5_ick: mcbsp5_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -922,7 +922,7 @@ mcbsp5_ick: mcbsp5_ick {
ti,bit-shift = <10>;
};
mcbsp1_ick: mcbsp1_ick {
mcbsp1_ick: mcbsp1_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -930,7 +930,7 @@ mcbsp1_ick: mcbsp1_ick {
ti,bit-shift = <9>;
};
omapctrl_ick: omapctrl_ick {
omapctrl_ick: omapctrl_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -938,7 +938,7 @@ omapctrl_ick: omapctrl_ick {
ti,bit-shift = <6>;
};
dss_tv_fck: dss_tv_fck {
dss_tv_fck: dss_tv_fck@e00 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&omap_54m_fck>;
......@@ -946,7 +946,7 @@ dss_tv_fck: dss_tv_fck {
ti,bit-shift = <2>;
};
dss_96m_fck: dss_96m_fck {
dss_96m_fck: dss_96m_fck@e00 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&omap_96m_fck>;
......@@ -954,7 +954,7 @@ dss_96m_fck: dss_96m_fck {
ti,bit-shift = <2>;
};
dss2_alwon_fck: dss2_alwon_fck {
dss2_alwon_fck: dss2_alwon_fck@e00 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_ck>;
......@@ -968,7 +968,7 @@ dummy_ck: dummy_ck {
clock-frequency = <0>;
};
gpt1_gate_fck: gpt1_gate_fck {
gpt1_gate_fck: gpt1_gate_fck@c00 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&sys_ck>;
......@@ -976,7 +976,7 @@ gpt1_gate_fck: gpt1_gate_fck {
reg = <0x0c00>;
};
gpt1_mux_fck: gpt1_mux_fck {
gpt1_mux_fck: gpt1_mux_fck@c40 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&omap_32k_fck>, <&sys_ck>;
......@@ -989,7 +989,7 @@ gpt1_fck: gpt1_fck {
clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
};
aes2_ick: aes2_ick {
aes2_ick: aes2_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -1005,7 +1005,7 @@ wkup_32k_fck: wkup_32k_fck {
clock-div = <1>;
};
gpio1_dbck: gpio1_dbck {
gpio1_dbck: gpio1_dbck@c00 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&wkup_32k_fck>;
......@@ -1013,7 +1013,7 @@ gpio1_dbck: gpio1_dbck {
ti,bit-shift = <3>;
};
sha12_ick: sha12_ick {
sha12_ick: sha12_ick@a10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&core_l4_ick>;
......@@ -1021,7 +1021,7 @@ sha12_ick: sha12_ick {
ti,bit-shift = <27>;
};
wdt2_fck: wdt2_fck {
wdt2_fck: wdt2_fck@c00 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&wkup_32k_fck>;
......@@ -1029,7 +1029,7 @@ wdt2_fck: wdt2_fck {
ti,bit-shift = <5>;
};
wdt2_ick: wdt2_ick {
wdt2_ick: wdt2_ick@c10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&wkup_l4_ick>;
......@@ -1037,7 +1037,7 @@ wdt2_ick: wdt2_ick {
ti,bit-shift = <5>;
};
wdt1_ick: wdt1_ick {
wdt1_ick: wdt1_ick@c10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&wkup_l4_ick>;
......@@ -1045,7 +1045,7 @@ wdt1_ick: wdt1_ick {
ti,bit-shift = <4>;
};
gpio1_ick: gpio1_ick {
gpio1_ick: gpio1_ick@c10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&wkup_l4_ick>;
......@@ -1053,7 +1053,7 @@ gpio1_ick: gpio1_ick {
ti,bit-shift = <3>;
};
omap_32ksync_ick: omap_32ksync_ick {
omap_32ksync_ick: omap_32ksync_ick@c10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&wkup_l4_ick>;
......@@ -1061,7 +1061,7 @@ omap_32ksync_ick: omap_32ksync_ick {
ti,bit-shift = <2>;
};
gpt12_ick: gpt12_ick {
gpt12_ick: gpt12_ick@c10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&wkup_l4_ick>;
......@@ -1069,7 +1069,7 @@ gpt12_ick: gpt12_ick {
ti,bit-shift = <1>;
};
gpt1_ick: gpt1_ick {
gpt1_ick: gpt1_ick@c10 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&wkup_l4_ick>;
......@@ -1093,7 +1093,7 @@ per_48m_fck: per_48m_fck {
clock-div = <1>;
};
uart3_fck: uart3_fck {
uart3_fck: uart3_fck@1000 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&per_48m_fck>;
......@@ -1101,7 +1101,7 @@ uart3_fck: uart3_fck {
ti,bit-shift = <11>;
};
gpt2_gate_fck: gpt2_gate_fck {
gpt2_gate_fck: gpt2_gate_fck@1000 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&sys_ck>;
......@@ -1109,7 +1109,7 @@ gpt2_gate_fck: gpt2_gate_fck {
reg = <0x1000>;
};
gpt2_mux_fck: gpt2_mux_fck {
gpt2_mux_fck: gpt2_mux_fck@1040 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&omap_32k_fck>, <&sys_ck>;
......@@ -1122,7 +1122,7 @@ gpt2_fck: gpt2_fck {
clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
};
gpt3_gate_fck: gpt3_gate_fck {
gpt3_gate_fck: gpt3_gate_fck@1000 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&sys_ck>;
......@@ -1130,7 +1130,7 @@ gpt3_gate_fck: gpt3_gate_fck {
reg = <0x1000>;
};
gpt3_mux_fck: gpt3_mux_fck {
gpt3_mux_fck: gpt3_mux_fck@1040 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&omap_32k_fck>, <&sys_ck>;
......@@ -1144,7 +1144,7 @@ gpt3_fck: gpt3_fck {
clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
};
gpt4_gate_fck: gpt4_gate_fck {
gpt4_gate_fck: gpt4_gate_fck@1000 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&sys_ck>;
......@@ -1152,7 +1152,7 @@ gpt4_gate_fck: gpt4_gate_fck {
reg = <0x1000>;
};
gpt4_mux_fck: gpt4_mux_fck {
gpt4_mux_fck: gpt4_mux_fck@1040 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&omap_32k_fck>, <&sys_ck>;
......@@ -1166,7 +1166,7 @@ gpt4_fck: gpt4_fck {
clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
};
gpt5_gate_fck: gpt5_gate_fck {
gpt5_gate_fck: gpt5_gate_fck@1000 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&sys_ck>;
......@@ -1174,7 +1174,7 @@ gpt5_gate_fck: gpt5_gate_fck {
reg = <0x1000>;
};
gpt5_mux_fck: gpt5_mux_fck {
gpt5_mux_fck: gpt5_mux_fck@1040 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&omap_32k_fck>, <&sys_ck>;
......@@ -1188,7 +1188,7 @@ gpt5_fck: gpt5_fck {
clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
};
gpt6_gate_fck: gpt6_gate_fck {
gpt6_gate_fck: gpt6_gate_fck@1000 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&sys_ck>;
......@@ -1196,7 +1196,7 @@ gpt6_gate_fck: gpt6_gate_fck {
reg = <0x1000>;
};
gpt6_mux_fck: gpt6_mux_fck {
gpt6_mux_fck: gpt6_mux_fck@1040 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&omap_32k_fck>, <&sys_ck>;
......@@ -1210,7 +1210,7 @@ gpt6_fck: gpt6_fck {
clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
};
gpt7_gate_fck: gpt7_gate_fck {
gpt7_gate_fck: gpt7_gate_fck@1000 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&sys_ck>;
......@@ -1218,7 +1218,7 @@ gpt7_gate_fck: gpt7_gate_fck {
reg = <0x1000>;
};
gpt7_mux_fck: gpt7_mux_fck {
gpt7_mux_fck: gpt7_mux_fck@1040 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&omap_32k_fck>, <&sys_ck>;
......@@ -1232,7 +1232,7 @@ gpt7_fck: gpt7_fck {
clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
};
gpt8_gate_fck: gpt8_gate_fck {
gpt8_gate_fck: gpt8_gate_fck@1000 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&sys_ck>;
......@@ -1240,7 +1240,7 @@ gpt8_gate_fck: gpt8_gate_fck {
reg = <0x1000>;
};
gpt8_mux_fck: gpt8_mux_fck {
gpt8_mux_fck: gpt8_mux_fck@1040 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&omap_32k_fck>, <&sys_ck>;
......@@ -1254,7 +1254,7 @@ gpt8_fck: gpt8_fck {
clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
};
gpt9_gate_fck: gpt9_gate_fck {
gpt9_gate_fck: gpt9_gate_fck@1000 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&sys_ck>;
......@@ -1262,7 +1262,7 @@ gpt9_gate_fck: gpt9_gate_fck {
reg = <0x1000>;
};
gpt9_mux_fck: gpt9_mux_fck {
gpt9_mux_fck: gpt9_mux_fck@1040 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&omap_32k_fck>, <&sys_ck>;
......@@ -1284,7 +1284,7 @@ per_32k_alwon_fck: per_32k_alwon_fck {
clock-div = <1>;
};
gpio6_dbck: gpio6_dbck {
gpio6_dbck: gpio6_dbck@1000 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&per_32k_alwon_fck>;
......@@ -1292,7 +1292,7 @@ gpio6_dbck: gpio6_dbck {
ti,bit-shift = <17>;
};
gpio5_dbck: gpio5_dbck {
gpio5_dbck: gpio5_dbck@1000 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&per_32k_alwon_fck>;
......@@ -1300,7 +1300,7 @@ gpio5_dbck: gpio5_dbck {
ti,bit-shift = <16>;
};
gpio4_dbck: gpio4_dbck {
gpio4_dbck: gpio4_dbck@1000 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&per_32k_alwon_fck>;
......@@ -1308,7 +1308,7 @@ gpio4_dbck: gpio4_dbck {
ti,bit-shift = <15>;
};
gpio3_dbck: gpio3_dbck {
gpio3_dbck: gpio3_dbck@1000 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&per_32k_alwon_fck>;
......@@ -1316,7 +1316,7 @@ gpio3_dbck: gpio3_dbck {
ti,bit-shift = <14>;
};
gpio2_dbck: gpio2_dbck {
gpio2_dbck: gpio2_dbck@1000 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&per_32k_alwon_fck>;
......@@ -1324,7 +1324,7 @@ gpio2_dbck: gpio2_dbck {
ti,bit-shift = <13>;
};
wdt3_fck: wdt3_fck {
wdt3_fck: wdt3_fck@1000 {
#clock-cells = <0>;
compatible = "ti,wait-gate-clock";
clocks = <&per_32k_alwon_fck>;
......@@ -1340,7 +1340,7 @@ per_l4_ick: per_l4_ick {
clock-div = <1>;
};
gpio6_ick: gpio6_ick {
gpio6_ick: gpio6_ick@1010 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&per_l4_ick>;
......@@ -1348,7 +1348,7 @@ gpio6_ick: gpio6_ick {
ti,bit-shift = <17>;
};
gpio5_ick: gpio5_ick {
gpio5_ick: gpio5_ick@1010 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&per_l4_ick>;
......@@ -1356,7 +1356,7 @@ gpio5_ick: gpio5_ick {
ti,bit-shift = <16>;
};
gpio4_ick: gpio4_ick {
gpio4_ick: gpio4_ick@1010 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&per_l4_ick>;
......@@ -1364,7 +1364,7 @@ gpio4_ick: gpio4_ick {
ti,bit-shift = <15>;
};
gpio3_ick: gpio3_ick {
gpio3_ick: gpio3_ick@1010 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&per_l4_ick>;
......@@ -1372,7 +1372,7 @@ gpio3_ick: gpio3_ick {
ti,bit-shift = <14>;
};
gpio2_ick: gpio2_ick {
gpio2_ick: gpio2_ick@1010 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&per_l4_ick>;
......@@ -1380,7 +1380,7 @@ gpio2_ick: gpio2_ick {
ti,bit-shift = <13>;
};
wdt3_ick: wdt3_ick {
wdt3_ick: wdt3_ick@1010 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&per_l4_ick>;
......@@ -1388,7 +1388,7 @@ wdt3_ick: wdt3_ick {
ti,bit-shift = <12>;
};
uart3_ick: uart3_ick {
uart3_ick: uart3_ick@1010 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&per_l4_ick>;
......@@ -1396,7 +1396,7 @@ uart3_ick: uart3_ick {
ti,bit-shift = <11>;
};
uart4_ick: uart4_ick {
uart4_ick: uart4_ick@1010 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&per_l4_ick>;
......@@ -1404,7 +1404,7 @@ uart4_ick: uart4_ick {
ti,bit-shift = <18>;
};
gpt9_ick: gpt9_ick {
gpt9_ick: gpt9_ick@1010 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&per_l4_ick>;
......@@ -1412,7 +1412,7 @@ gpt9_ick: gpt9_ick {
ti,bit-shift = <10>;
};
gpt8_ick: gpt8_ick {
gpt8_ick: gpt8_ick@1010 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&per_l4_ick>;
......@@ -1420,7 +1420,7 @@ gpt8_ick: gpt8_ick {
ti,bit-shift = <9>;
};
gpt7_ick: gpt7_ick {
gpt7_ick: gpt7_ick@1010 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&per_l4_ick>;
......@@ -1428,7 +1428,7 @@ gpt7_ick: gpt7_ick {
ti,bit-shift = <8>;
};
gpt6_ick: gpt6_ick {
gpt6_ick: gpt6_ick@1010 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&per_l4_ick>;
......@@ -1436,7 +1436,7 @@ gpt6_ick: gpt6_ick {
ti,bit-shift = <7>;
};
gpt5_ick: gpt5_ick {
gpt5_ick: gpt5_ick@1010 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&per_l4_ick>;
......@@ -1444,7 +1444,7 @@ gpt5_ick: gpt5_ick {
ti,bit-shift = <6>;
};
gpt4_ick: gpt4_ick {
gpt4_ick: gpt4_ick@1010 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&per_l4_ick>;
......@@ -1452,7 +1452,7 @@ gpt4_ick: gpt4_ick {
ti,bit-shift = <5>;
};
gpt3_ick: gpt3_ick {
gpt3_ick: gpt3_ick@1010 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&per_l4_ick>;
......@@ -1460,7 +1460,7 @@ gpt3_ick: gpt3_ick {
ti,bit-shift = <4>;
};
gpt2_ick: gpt2_ick {
gpt2_ick: gpt2_ick@1010 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&per_l4_ick>;
......@@ -1468,7 +1468,7 @@ gpt2_ick: gpt2_ick {
ti,bit-shift = <3>;
};
mcbsp2_ick: mcbsp2_ick {
mcbsp2_ick: mcbsp2_ick@1010 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&per_l4_ick>;
......@@ -1476,7 +1476,7 @@ mcbsp2_ick: mcbsp2_ick {
ti,bit-shift = <0>;
};
mcbsp3_ick: mcbsp3_ick {
mcbsp3_ick: mcbsp3_ick@1010 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&per_l4_ick>;
......@@ -1484,7 +1484,7 @@ mcbsp3_ick: mcbsp3_ick {
ti,bit-shift = <1>;
};
mcbsp4_ick: mcbsp4_ick {
mcbsp4_ick: mcbsp4_ick@1010 {
#clock-cells = <0>;
compatible = "ti,omap3-interface-clock";
clocks = <&per_l4_ick>;
......@@ -1492,7 +1492,7 @@ mcbsp4_ick: mcbsp4_ick {
ti,bit-shift = <2>;
};
mcbsp2_gate_fck: mcbsp2_gate_fck {
mcbsp2_gate_fck: mcbsp2_gate_fck@1000 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&mcbsp_clks>;
......@@ -1500,7 +1500,7 @@ mcbsp2_gate_fck: mcbsp2_gate_fck {
reg = <0x1000>;
};
mcbsp3_gate_fck: mcbsp3_gate_fck {
mcbsp3_gate_fck: mcbsp3_gate_fck@1000 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&mcbsp_clks>;
......@@ -1508,7 +1508,7 @@ mcbsp3_gate_fck: mcbsp3_gate_fck {
reg = <0x1000>;
};
mcbsp4_gate_fck: mcbsp4_gate_fck {
mcbsp4_gate_fck: mcbsp4_gate_fck@1000 {
#clock-cells = <0>;
compatible = "ti,composite-gate-clock";
clocks = <&mcbsp_clks>;
......@@ -1516,7 +1516,7 @@ mcbsp4_gate_fck: mcbsp4_gate_fck {
reg = <0x1000>;
};
emu_src_mux_ck: emu_src_mux_ck {
emu_src_mux_ck: emu_src_mux_ck@1140 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
......@@ -1529,7 +1529,7 @@ emu_src_ck: emu_src_ck {
clocks = <&emu_src_mux_ck>;
};
pclk_fck: pclk_fck {
pclk_fck: pclk_fck@1140 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&emu_src_ck>;
......@@ -1539,7 +1539,7 @@ pclk_fck: pclk_fck {
ti,index-starts-at-one;
};
pclkx2_fck: pclkx2_fck {
pclkx2_fck: pclkx2_fck@1140 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&emu_src_ck>;
......@@ -1549,7 +1549,7 @@ pclkx2_fck: pclkx2_fck {
ti,index-starts-at-one;
};
atclk_fck: atclk_fck {
atclk_fck: atclk_fck@1140 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&emu_src_ck>;
......@@ -1559,7 +1559,7 @@ atclk_fck: atclk_fck {
ti,index-starts-at-one;
};
traceclk_src_fck: traceclk_src_fck {
traceclk_src_fck: traceclk_src_fck@1140 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
......@@ -1567,7 +1567,7 @@ traceclk_src_fck: traceclk_src_fck {
reg = <0x1140>;
};
traceclk_fck: traceclk_fck {
traceclk_fck: traceclk_fck@1140 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&traceclk_src_fck>;
......
arch/arm/boot/dts/omap4-kc1.dts 0 → 100644
View file @ 1ea7c8b6
/*
* Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "omap443x.dtsi"
/ {
model = "Amazon Kindle Fire (first generation)";
compatible = "amazon,omap4-kc1", "ti,omap4430", "ti,omap4";
memory {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512 MB */
};
pwmleds {
compatible = "pwm-leds";
green {
label = "green";
pwms = <&twl_pwm 0 7812500>;
max-brightness = <127>;
};
orange {
label = "orange";
pwms = <&twl_pwm 1 7812500>;
max-brightness = <127>;
};
};
};
&omap4_pmx_core {
pinctrl-names = "default";
uart3_pins: pinmux_uart3_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx */
OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx */
>;
};
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */
>;
};
i2c2_pins: pinmux_i2c2_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */
OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */
>;
};
i2c3_pins: pinmux_i2c3_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */
OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */
>;
};
i2c4_pins: pinmux_i2c4_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */
OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */
>;
};
mmc2_pins: pinmux_mmc2_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x040, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat0 */
OMAP4_IOPAD(0x042, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat1 */
OMAP4_IOPAD(0x044, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat2 */
OMAP4_IOPAD(0x046, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat3 */
OMAP4_IOPAD(0x048, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat4 */
OMAP4_IOPAD(0x04a, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat5 */
OMAP4_IOPAD(0x04c, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat6 */
OMAP4_IOPAD(0x04e, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat7 */
OMAP4_IOPAD(0x082, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_clk */
OMAP4_IOPAD(0x084, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_cmd */
>;
};
usb_otg_hs_pins: pinmux_usb_otg_hs_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x194, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usba0_otg_ce */
OMAP4_IOPAD(0x196, PIN_INPUT | MUX_MODE0) /* usba0_otg_dp */
OMAP4_IOPAD(0x198, PIN_INPUT | MUX_MODE0) /* usba0_otg_dm */
>;
};
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
&omap4_pmx_core OMAP4_UART3_RX>;
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
twl: twl@48 {
reg = <0x48>;
/* IRQ# = 7 */
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
twl_power: power {
compatible = "ti,twl6030-power";
ti,system-power-controller;
};
};
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
clock-frequency = <400000>;
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
clock-frequency = <400000>;
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins>;
clock-frequency = <400000>;
};
&mmc1 {
status = "disabled";
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
vmmc-supply = <&vaux1>;
ti,non-removable;
bus-width = <8>;
};
&mmc3 {
status = "disabled";
};
&mmc4 {
status = "disabled";
};
&usb_otg_hs {
pinctrl-names = "default";
pinctrl-0 = <&usb_otg_hs_pins>;
interface-type = <1>;
mode = <3>;
power = <50>;
};
#include "twl6030.dtsi"
#include "twl6030_omap4.dtsi"
&twl_usb_comparator {
usb-supply = <&vusb>;
};
arch/arm/boot/dts/omap4-var-som-om44.dtsi
View file @ 1ea7c8b6
......@@ -17,7 +17,7 @@ memory {
reg = <0x80000000 0x40000000>; /* 1 GB */
};
sound: sound@0 {
sound: sound {
compatible = "ti,abe-twl6040";
ti,model = "VAR-SOM-OM44";
......
arch/arm/boot/dts/omap4.dtsi
View file @ 1ea7c8b6
......@@ -198,7 +198,7 @@ omap4_padconf_global: omap4_padconf_global@5a0 {
#size-cells = <1>;
ranges = <0 0x5a0 0x170>;
pbias_regulator: pbias_regulator {
pbias_regulator: pbias_regulator@60 {
compatible = "ti,pbias-omap4", "ti,pbias-omap";
reg = <0x60 0x4>;
syscon = <&omap4_padconf_global>;
......@@ -370,6 +370,10 @@ gpmc: gpmc@50000000 {
ti,no-idle-on-init;
clocks = <&l3_div_ck>;
clock-names = "fck";
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
};
uart1: serial@4806a000 {
......
arch/arm/boot/dts/omap443x-clocks.dtsi
View file @ 1ea7c8b6
......@@ -8,7 +8,7 @@
* published by the Free Software Foundation.
*/
&prm_clocks {
bandgap_fclk: bandgap_fclk {
bandgap_fclk: bandgap_fclk@1888 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......
arch/arm/boot/dts/omap443x.dtsi
View file @ 1ea7c8b6
......@@ -35,7 +35,7 @@ thermal-zones {
};
ocp {
bandgap: bandgap {
bandgap: bandgap@4a002260 {
reg = <0x4a002260 0x4
0x4a00232C 0x4>;
compatible = "ti,omap4430-bandgap";
......
arch/arm/boot/dts/omap4460.dtsi
View file @ 1ea7c8b6
......@@ -40,7 +40,7 @@ thermal-zones {
};
ocp {
bandgap: bandgap {
bandgap: bandgap@4a002260 {
reg = <0x4a002260 0x4
0x4a00232C 0x4
0x4a002378 0x18>;
......
arch/arm/boot/dts/omap446x-clocks.dtsi
View file @ 1ea7c8b6
......@@ -8,7 +8,7 @@
* published by the Free Software Foundation.
*/
&prm_clocks {
div_ts_ck: div_ts_ck {
div_ts_ck: div_ts_ck@1888 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&l4_wkup_clk_mux_ck>;
......@@ -17,7 +17,7 @@ div_ts_ck: div_ts_ck {
ti,dividers = <8>, <16>, <32>;
};
bandgap_ts_fclk: bandgap_ts_fclk {
bandgap_ts_fclk: bandgap_ts_fclk@1888 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&div_ts_ck>;
......
arch/arm/boot/dts/omap44xx-clocks.dtsi
View file @ 1ea7c8b6
......@@ -20,7 +20,7 @@ pad_clks_src_ck: pad_clks_src_ck {
clock-frequency = <12000000>;
};
pad_clks_ck: pad_clks_ck {
pad_clks_ck: pad_clks_ck@108 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&pad_clks_src_ck>;
......@@ -46,7 +46,7 @@ slimbus_src_clk: slimbus_src_clk {
clock-frequency = <12000000>;
};
slimbus_clk: slimbus_clk {
slimbus_clk: slimbus_clk@108 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&slimbus_src_clk>;
......@@ -132,21 +132,21 @@ xclk60motg_ck: xclk60motg_ck {
clock-frequency = <60000000>;
};
dpll_abe_ck: dpll_abe_ck {
dpll_abe_ck: dpll_abe_ck@1e0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-m4xen-clock";
clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
};
dpll_abe_x2_ck: dpll_abe_x2_ck {
dpll_abe_x2_ck: dpll_abe_x2_ck@1f0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
clocks = <&dpll_abe_ck>;
reg = <0x01f0>;
};
dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_x2_ck>;
......@@ -165,7 +165,7 @@ abe_24m_fclk: abe_24m_fclk {
clock-div = <8>;
};
abe_clk: abe_clk {
abe_clk: abe_clk@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2x2_ck>;
......@@ -174,7 +174,7 @@ abe_clk: abe_clk {
ti,index-power-of-two;
};
aess_fclk: aess_fclk {
aess_fclk: aess_fclk@528 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&abe_clk>;
......@@ -183,7 +183,7 @@ aess_fclk: aess_fclk {
reg = <0x0528>;
};
dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_x2_ck>;
......@@ -194,7 +194,7 @@ dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
ti,invert-autoidle-bit;
};
core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck {
core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@12c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
......@@ -202,7 +202,7 @@ core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck {
reg = <0x012c>;
};
dpll_core_ck: dpll_core_ck {
dpll_core_ck: dpll_core_ck@120 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-core-clock";
clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>;
......@@ -215,7 +215,7 @@ dpll_core_x2_ck: dpll_core_x2_ck {
clocks = <&dpll_core_ck>;
};
dpll_core_m6x2_ck: dpll_core_m6x2_ck {
dpll_core_m6x2_ck: dpll_core_m6x2_ck@140 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
......@@ -226,7 +226,7 @@ dpll_core_m6x2_ck: dpll_core_m6x2_ck {
ti,invert-autoidle-bit;
};
dpll_core_m2_ck: dpll_core_m2_ck {
dpll_core_m2_ck: dpll_core_m2_ck@130 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_ck>;
......@@ -245,7 +245,7 @@ ddrphy_ck: ddrphy_ck {
clock-div = <2>;
};
dpll_core_m5x2_ck: dpll_core_m5x2_ck {
dpll_core_m5x2_ck: dpll_core_m5x2_ck@13c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
......@@ -256,7 +256,7 @@ dpll_core_m5x2_ck: dpll_core_m5x2_ck {
ti,invert-autoidle-bit;
};
div_core_ck: div_core_ck {
div_core_ck: div_core_ck@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_m5x2_ck>;
......@@ -264,7 +264,7 @@ div_core_ck: div_core_ck {
ti,max-div = <2>;
};
div_iva_hs_clk: div_iva_hs_clk {
div_iva_hs_clk: div_iva_hs_clk@1dc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_m5x2_ck>;
......@@ -273,7 +273,7 @@ div_iva_hs_clk: div_iva_hs_clk {
ti,index-power-of-two;
};
div_mpu_hs_clk: div_mpu_hs_clk {
div_mpu_hs_clk: div_mpu_hs_clk@19c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_m5x2_ck>;
......@@ -282,7 +282,7 @@ div_mpu_hs_clk: div_mpu_hs_clk {
ti,index-power-of-two;
};
dpll_core_m4x2_ck: dpll_core_m4x2_ck {
dpll_core_m4x2_ck: dpll_core_m4x2_ck@138 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
......@@ -301,7 +301,7 @@ dll_clk_div_ck: dll_clk_div_ck {
clock-div = <2>;
};
dpll_abe_m2_ck: dpll_abe_m2_ck {
dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_ck>;
......@@ -310,7 +310,7 @@ dpll_abe_m2_ck: dpll_abe_m2_ck {
ti,index-starts-at-one;
};
dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck {
dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck@134 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clocks = <&dpll_core_x2_ck>;
......@@ -318,7 +318,7 @@ dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck {
reg = <0x0134>;
};
dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck {
dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@134 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&dpll_core_x2_ck>;
......@@ -333,7 +333,7 @@ dpll_core_m3x2_ck: dpll_core_m3x2_ck {
clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>;
};
dpll_core_m7x2_ck: dpll_core_m7x2_ck {
dpll_core_m7x2_ck: dpll_core_m7x2_ck@144 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
......@@ -344,7 +344,7 @@ dpll_core_m7x2_ck: dpll_core_m7x2_ck {
ti,invert-autoidle-bit;
};
iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck {
iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@1ac {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>;
......@@ -352,7 +352,7 @@ iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck {
reg = <0x01ac>;
};
dpll_iva_ck: dpll_iva_ck {
dpll_iva_ck: dpll_iva_ck@1a0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
......@@ -365,7 +365,7 @@ dpll_iva_x2_ck: dpll_iva_x2_ck {
clocks = <&dpll_iva_ck>;
};
dpll_iva_m4x2_ck: dpll_iva_m4x2_ck {
dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@1b8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_iva_x2_ck>;
......@@ -376,7 +376,7 @@ dpll_iva_m4x2_ck: dpll_iva_m4x2_ck {
ti,invert-autoidle-bit;
};
dpll_iva_m5x2_ck: dpll_iva_m5x2_ck {
dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_iva_x2_ck>;
......@@ -387,14 +387,14 @@ dpll_iva_m5x2_ck: dpll_iva_m5x2_ck {
ti,invert-autoidle-bit;
};
dpll_mpu_ck: dpll_mpu_ck {
dpll_mpu_ck: dpll_mpu_ck@160 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>;
reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
};
dpll_mpu_m2_ck: dpll_mpu_m2_ck {
dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_mpu_ck>;
......@@ -421,7 +421,7 @@ usb_hs_clk_div_ck: usb_hs_clk_div_ck {
clock-div = <3>;
};
l3_div_ck: l3_div_ck {
l3_div_ck: l3_div_ck@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&div_core_ck>;
......@@ -430,7 +430,7 @@ l3_div_ck: l3_div_ck {
reg = <0x0100>;
};
l4_div_ck: l4_div_ck {
l4_div_ck: l4_div_ck@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&l3_div_ck>;
......@@ -455,7 +455,7 @@ mpu_periphclk: mpu_periphclk {
clock-div = <2>;
};
ocp_abe_iclk: ocp_abe_iclk {
ocp_abe_iclk: ocp_abe_iclk@528 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&aess_fclk>;
......@@ -472,7 +472,7 @@ per_abe_24m_fclk: per_abe_24m_fclk {
clock-div = <4>;
};
dmic_sync_mux_ck: dmic_sync_mux_ck {
dmic_sync_mux_ck: dmic_sync_mux_ck@538 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
......@@ -480,7 +480,7 @@ dmic_sync_mux_ck: dmic_sync_mux_ck {
reg = <0x0538>;
};
func_dmic_abe_gfclk: func_dmic_abe_gfclk {
func_dmic_abe_gfclk: func_dmic_abe_gfclk@538 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
......@@ -488,7 +488,7 @@ func_dmic_abe_gfclk: func_dmic_abe_gfclk {
reg = <0x0538>;
};
mcasp_sync_mux_ck: mcasp_sync_mux_ck {
mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
......@@ -496,7 +496,7 @@ mcasp_sync_mux_ck: mcasp_sync_mux_ck {
reg = <0x0540>;
};
func_mcasp_abe_gfclk: func_mcasp_abe_gfclk {
func_mcasp_abe_gfclk: func_mcasp_abe_gfclk@540 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
......@@ -504,7 +504,7 @@ func_mcasp_abe_gfclk: func_mcasp_abe_gfclk {
reg = <0x0540>;
};
mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck {
mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@548 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
......@@ -512,7 +512,7 @@ mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck {
reg = <0x0548>;
};
func_mcbsp1_gfclk: func_mcbsp1_gfclk {
func_mcbsp1_gfclk: func_mcbsp1_gfclk@548 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
......@@ -520,7 +520,7 @@ func_mcbsp1_gfclk: func_mcbsp1_gfclk {
reg = <0x0548>;
};
mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck {
mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
......@@ -528,7 +528,7 @@ mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck {
reg = <0x0550>;
};
func_mcbsp2_gfclk: func_mcbsp2_gfclk {
func_mcbsp2_gfclk: func_mcbsp2_gfclk@550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
......@@ -536,7 +536,7 @@ func_mcbsp2_gfclk: func_mcbsp2_gfclk {
reg = <0x0550>;
};
mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck {
mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@558 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
......@@ -544,7 +544,7 @@ mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck {
reg = <0x0558>;
};
func_mcbsp3_gfclk: func_mcbsp3_gfclk {
func_mcbsp3_gfclk: func_mcbsp3_gfclk@558 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
......@@ -552,7 +552,7 @@ func_mcbsp3_gfclk: func_mcbsp3_gfclk {
reg = <0x0558>;
};
slimbus1_fclk_1: slimbus1_fclk_1 {
slimbus1_fclk_1: slimbus1_fclk_1@560 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&func_24m_clk>;
......@@ -560,7 +560,7 @@ slimbus1_fclk_1: slimbus1_fclk_1 {
reg = <0x0560>;
};
slimbus1_fclk_0: slimbus1_fclk_0 {
slimbus1_fclk_0: slimbus1_fclk_0@560 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&abe_24m_fclk>;
......@@ -568,7 +568,7 @@ slimbus1_fclk_0: slimbus1_fclk_0 {
reg = <0x0560>;
};
slimbus1_fclk_2: slimbus1_fclk_2 {
slimbus1_fclk_2: slimbus1_fclk_2@560 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&pad_clks_ck>;
......@@ -576,7 +576,7 @@ slimbus1_fclk_2: slimbus1_fclk_2 {
reg = <0x0560>;
};
slimbus1_slimbus_clk: slimbus1_slimbus_clk {
slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&slimbus_clk>;
......@@ -584,7 +584,7 @@ slimbus1_slimbus_clk: slimbus1_slimbus_clk {
reg = <0x0560>;
};
timer5_sync_mux: timer5_sync_mux {
timer5_sync_mux: timer5_sync_mux@568 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
......@@ -592,7 +592,7 @@ timer5_sync_mux: timer5_sync_mux {
reg = <0x0568>;
};
timer6_sync_mux: timer6_sync_mux {
timer6_sync_mux: timer6_sync_mux@570 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
......@@ -600,7 +600,7 @@ timer6_sync_mux: timer6_sync_mux {
reg = <0x0570>;
};
timer7_sync_mux: timer7_sync_mux {
timer7_sync_mux: timer7_sync_mux@578 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
......@@ -608,7 +608,7 @@ timer7_sync_mux: timer7_sync_mux {
reg = <0x0578>;
};
timer8_sync_mux: timer8_sync_mux {
timer8_sync_mux: timer8_sync_mux@580 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
......@@ -623,7 +623,7 @@ dummy_ck: dummy_ck {
};
};
&prm_clocks {
sys_clkin_ck: sys_clkin_ck {
sys_clkin_ck: sys_clkin_ck@110 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
......@@ -631,7 +631,7 @@ sys_clkin_ck: sys_clkin_ck {
ti,index-starts-at-one;
};
abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck {
abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
......@@ -639,7 +639,7 @@ abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck {
reg = <0x0108>;
};
abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck {
abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@10c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
......@@ -654,14 +654,14 @@ dbgclk_mux_ck: dbgclk_mux_ck {
clock-div = <1>;
};
l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck {
l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>;
reg = <0x0108>;
};
syc_clk_div_ck: syc_clk_div_ck {
syc_clk_div_ck: syc_clk_div_ck@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin_ck>;
......@@ -669,7 +669,7 @@ syc_clk_div_ck: syc_clk_div_ck {
ti,max-div = <2>;
};
gpio1_dbclk: gpio1_dbclk {
gpio1_dbclk: gpio1_dbclk@1838 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -677,7 +677,7 @@ gpio1_dbclk: gpio1_dbclk {
reg = <0x1838>;
};
dmt1_clk_mux: dmt1_clk_mux {
dmt1_clk_mux: dmt1_clk_mux@1840 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
......@@ -685,7 +685,7 @@ dmt1_clk_mux: dmt1_clk_mux {
reg = <0x1840>;
};
usim_ck: usim_ck {
usim_ck: usim_ck@1858 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_m4x2_ck>;
......@@ -694,7 +694,7 @@ usim_ck: usim_ck {
ti,dividers = <14>, <18>;
};
usim_fclk: usim_fclk {
usim_fclk: usim_fclk@1858 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&usim_ck>;
......@@ -702,7 +702,7 @@ usim_fclk: usim_fclk {
reg = <0x1858>;
};
pmd_stm_clock_mux_ck: pmd_stm_clock_mux_ck {
pmd_stm_clock_mux_ck: pmd_stm_clock_mux_ck@1a20 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
......@@ -710,7 +710,7 @@ pmd_stm_clock_mux_ck: pmd_stm_clock_mux_ck {
reg = <0x1a20>;
};
pmd_trace_clk_mux_ck: pmd_trace_clk_mux_ck {
pmd_trace_clk_mux_ck: pmd_trace_clk_mux_ck@1a20 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
......@@ -718,7 +718,7 @@ pmd_trace_clk_mux_ck: pmd_trace_clk_mux_ck {
reg = <0x1a20>;
};
stm_clk_div_ck: stm_clk_div_ck {
stm_clk_div_ck: stm_clk_div_ck@1a20 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&pmd_stm_clock_mux_ck>;
......@@ -728,7 +728,7 @@ stm_clk_div_ck: stm_clk_div_ck {
ti,index-power-of-two;
};
trace_clk_div_div_ck: trace_clk_div_div_ck {
trace_clk_div_div_ck: trace_clk_div_div_ck@1a20 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&pmd_trace_clk_mux_ck>;
......@@ -752,7 +752,7 @@ emu_sys_clkdm: emu_sys_clkdm {
};
&cm2_clocks {
per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck {
per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@14c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>;
......@@ -760,14 +760,14 @@ per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck {
reg = <0x014c>;
};
dpll_per_ck: dpll_per_ck {
dpll_per_ck: dpll_per_ck@140 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>;
reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
};
dpll_per_m2_ck: dpll_per_m2_ck {
dpll_per_m2_ck: dpll_per_m2_ck@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_ck>;
......@@ -776,14 +776,14 @@ dpll_per_m2_ck: dpll_per_m2_ck {
ti,index-starts-at-one;
};
dpll_per_x2_ck: dpll_per_x2_ck {
dpll_per_x2_ck: dpll_per_x2_ck@150 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-x2-clock";
clocks = <&dpll_per_ck>;
reg = <0x0150>;
};
dpll_per_m2x2_ck: dpll_per_m2x2_ck {
dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
......@@ -794,7 +794,7 @@ dpll_per_m2x2_ck: dpll_per_m2x2_ck {
ti,invert-autoidle-bit;
};
dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck {
dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck@154 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clocks = <&dpll_per_x2_ck>;
......@@ -802,7 +802,7 @@ dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck {
reg = <0x0154>;
};
dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck {
dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@154 {
#clock-cells = <0>;
compatible = "ti,composite-divider-clock";
clocks = <&dpll_per_x2_ck>;
......@@ -817,7 +817,7 @@ dpll_per_m3x2_ck: dpll_per_m3x2_ck {
clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>;
};
dpll_per_m4x2_ck: dpll_per_m4x2_ck {
dpll_per_m4x2_ck: dpll_per_m4x2_ck@158 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
......@@ -828,7 +828,7 @@ dpll_per_m4x2_ck: dpll_per_m4x2_ck {
ti,invert-autoidle-bit;
};
dpll_per_m5x2_ck: dpll_per_m5x2_ck {
dpll_per_m5x2_ck: dpll_per_m5x2_ck@15c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
......@@ -839,7 +839,7 @@ dpll_per_m5x2_ck: dpll_per_m5x2_ck {
ti,invert-autoidle-bit;
};
dpll_per_m6x2_ck: dpll_per_m6x2_ck {
dpll_per_m6x2_ck: dpll_per_m6x2_ck@160 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
......@@ -850,7 +850,7 @@ dpll_per_m6x2_ck: dpll_per_m6x2_ck {
ti,invert-autoidle-bit;
};
dpll_per_m7x2_ck: dpll_per_m7x2_ck {
dpll_per_m7x2_ck: dpll_per_m7x2_ck@164 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
......@@ -861,14 +861,14 @@ dpll_per_m7x2_ck: dpll_per_m7x2_ck {
ti,invert-autoidle-bit;
};
dpll_usb_ck: dpll_usb_ck {
dpll_usb_ck: dpll_usb_ck@180 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-j-type-clock";
clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>;
reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
};
dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck {
dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@1b4 {
#clock-cells = <0>;
compatible = "ti,fixed-factor-clock";
clocks = <&dpll_usb_ck>;
......@@ -879,7 +879,7 @@ dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck {
ti,invert-autoidle-bit;
};
dpll_usb_m2_ck: dpll_usb_m2_ck {
dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_usb_ck>;
......@@ -890,7 +890,7 @@ dpll_usb_m2_ck: dpll_usb_m2_ck {
ti,invert-autoidle-bit;
};
ducati_clk_mux_ck: ducati_clk_mux_ck {
ducati_clk_mux_ck: ducati_clk_mux_ck@100 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>;
......@@ -921,7 +921,7 @@ func_24mc_fclk: func_24mc_fclk {
clock-div = <8>;
};
func_48m_fclk: func_48m_fclk {
func_48m_fclk: func_48m_fclk@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_m2x2_ck>;
......@@ -937,7 +937,7 @@ func_48mc_fclk: func_48mc_fclk {
clock-div = <4>;
};
func_64m_fclk: func_64m_fclk {
func_64m_fclk: func_64m_fclk@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_m4x2_ck>;
......@@ -945,7 +945,7 @@ func_64m_fclk: func_64m_fclk {
ti,dividers = <2>, <4>;
};
func_96m_fclk: func_96m_fclk {
func_96m_fclk: func_96m_fclk@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_m2x2_ck>;
......@@ -953,7 +953,7 @@ func_96m_fclk: func_96m_fclk {
ti,dividers = <2>, <4>;
};
init_60m_fclk: init_60m_fclk {
init_60m_fclk: init_60m_fclk@104 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_usb_m2_ck>;
......@@ -961,7 +961,7 @@ init_60m_fclk: init_60m_fclk {
ti,dividers = <1>, <8>;
};
per_abe_nc_fclk: per_abe_nc_fclk {
per_abe_nc_fclk: per_abe_nc_fclk@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2_ck>;
......@@ -969,7 +969,7 @@ per_abe_nc_fclk: per_abe_nc_fclk {
ti,max-div = <2>;
};
aes1_fck: aes1_fck {
aes1_fck: aes1_fck@15a0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3_div_ck>;
......@@ -977,7 +977,7 @@ aes1_fck: aes1_fck {
reg = <0x15a0>;
};
aes2_fck: aes2_fck {
aes2_fck: aes2_fck@15a8 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3_div_ck>;
......@@ -985,7 +985,7 @@ aes2_fck: aes2_fck {
reg = <0x15a8>;
};
dss_sys_clk: dss_sys_clk {
dss_sys_clk: dss_sys_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&syc_clk_div_ck>;
......@@ -993,7 +993,7 @@ dss_sys_clk: dss_sys_clk {
reg = <0x1120>;
};
dss_tv_clk: dss_tv_clk {
dss_tv_clk: dss_tv_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&extalt_clkin_ck>;
......@@ -1001,7 +1001,7 @@ dss_tv_clk: dss_tv_clk {
reg = <0x1120>;
};
dss_dss_clk: dss_dss_clk {
dss_dss_clk: dss_dss_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_m5x2_ck>;
......@@ -1010,7 +1010,7 @@ dss_dss_clk: dss_dss_clk {
ti,set-rate-parent;
};
dss_48mhz_clk: dss_48mhz_clk {
dss_48mhz_clk: dss_48mhz_clk@1120 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&func_48mc_fclk>;
......@@ -1018,7 +1018,7 @@ dss_48mhz_clk: dss_48mhz_clk {
reg = <0x1120>;
};
fdif_fck: fdif_fck {
fdif_fck: fdif_fck@1028 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_m4x2_ck>;
......@@ -1028,7 +1028,7 @@ fdif_fck: fdif_fck {
ti,index-power-of-two;
};
gpio2_dbclk: gpio2_dbclk {
gpio2_dbclk: gpio2_dbclk@1460 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -1036,7 +1036,7 @@ gpio2_dbclk: gpio2_dbclk {
reg = <0x1460>;
};
gpio3_dbclk: gpio3_dbclk {
gpio3_dbclk: gpio3_dbclk@1468 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -1044,7 +1044,7 @@ gpio3_dbclk: gpio3_dbclk {
reg = <0x1468>;
};
gpio4_dbclk: gpio4_dbclk {
gpio4_dbclk: gpio4_dbclk@1470 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -1052,7 +1052,7 @@ gpio4_dbclk: gpio4_dbclk {
reg = <0x1470>;
};
gpio5_dbclk: gpio5_dbclk {
gpio5_dbclk: gpio5_dbclk@1478 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -1060,7 +1060,7 @@ gpio5_dbclk: gpio5_dbclk {
reg = <0x1478>;
};
gpio6_dbclk: gpio6_dbclk {
gpio6_dbclk: gpio6_dbclk@1480 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -1068,7 +1068,7 @@ gpio6_dbclk: gpio6_dbclk {
reg = <0x1480>;
};
sgx_clk_mux: sgx_clk_mux {
sgx_clk_mux: sgx_clk_mux@1220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_core_m7x2_ck>, <&dpll_per_m7x2_ck>;
......@@ -1076,7 +1076,7 @@ sgx_clk_mux: sgx_clk_mux {
reg = <0x1220>;
};
hsi_fck: hsi_fck {
hsi_fck: hsi_fck@1338 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_m2x2_ck>;
......@@ -1086,7 +1086,7 @@ hsi_fck: hsi_fck {
ti,index-power-of-two;
};
iss_ctrlclk: iss_ctrlclk {
iss_ctrlclk: iss_ctrlclk@1020 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&func_96m_fclk>;
......@@ -1094,7 +1094,7 @@ iss_ctrlclk: iss_ctrlclk {
reg = <0x1020>;
};
mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck {
mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck@14e0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_96m_fclk>, <&per_abe_nc_fclk>;
......@@ -1102,7 +1102,7 @@ mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck {
reg = <0x14e0>;
};
per_mcbsp4_gfclk: per_mcbsp4_gfclk {
per_mcbsp4_gfclk: per_mcbsp4_gfclk@14e0 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&mcbsp4_sync_mux_ck>, <&pad_clks_ck>;
......@@ -1110,7 +1110,7 @@ per_mcbsp4_gfclk: per_mcbsp4_gfclk {
reg = <0x14e0>;
};
hsmmc1_fclk: hsmmc1_fclk {
hsmmc1_fclk: hsmmc1_fclk@1328 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_64m_fclk>, <&func_96m_fclk>;
......@@ -1118,7 +1118,7 @@ hsmmc1_fclk: hsmmc1_fclk {
reg = <0x1328>;
};
hsmmc2_fclk: hsmmc2_fclk {
hsmmc2_fclk: hsmmc2_fclk@1330 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_64m_fclk>, <&func_96m_fclk>;
......@@ -1126,7 +1126,7 @@ hsmmc2_fclk: hsmmc2_fclk {
reg = <0x1330>;
};
ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m {
ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m@13e0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&func_48m_fclk>;
......@@ -1134,7 +1134,7 @@ ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m {
reg = <0x13e0>;
};
sha2md5_fck: sha2md5_fck {
sha2md5_fck: sha2md5_fck@15c8 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3_div_ck>;
......@@ -1142,7 +1142,7 @@ sha2md5_fck: sha2md5_fck {
reg = <0x15c8>;
};
slimbus2_fclk_1: slimbus2_fclk_1 {
slimbus2_fclk_1: slimbus2_fclk_1@1538 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&per_abe_24m_fclk>;
......@@ -1150,7 +1150,7 @@ slimbus2_fclk_1: slimbus2_fclk_1 {
reg = <0x1538>;
};
slimbus2_fclk_0: slimbus2_fclk_0 {
slimbus2_fclk_0: slimbus2_fclk_0@1538 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&func_24mc_fclk>;
......@@ -1158,7 +1158,7 @@ slimbus2_fclk_0: slimbus2_fclk_0 {
reg = <0x1538>;
};
slimbus2_slimbus_clk: slimbus2_slimbus_clk {
slimbus2_slimbus_clk: slimbus2_slimbus_clk@1538 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&pad_slimbus_core_clks_ck>;
......@@ -1166,7 +1166,7 @@ slimbus2_slimbus_clk: slimbus2_slimbus_clk {
reg = <0x1538>;
};
smartreflex_core_fck: smartreflex_core_fck {
smartreflex_core_fck: smartreflex_core_fck@638 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l4_wkup_clk_mux_ck>;
......@@ -1174,7 +1174,7 @@ smartreflex_core_fck: smartreflex_core_fck {
reg = <0x0638>;
};
smartreflex_iva_fck: smartreflex_iva_fck {
smartreflex_iva_fck: smartreflex_iva_fck@630 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l4_wkup_clk_mux_ck>;
......@@ -1182,7 +1182,7 @@ smartreflex_iva_fck: smartreflex_iva_fck {
reg = <0x0630>;
};
smartreflex_mpu_fck: smartreflex_mpu_fck {
smartreflex_mpu_fck: smartreflex_mpu_fck@628 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l4_wkup_clk_mux_ck>;
......@@ -1190,7 +1190,7 @@ smartreflex_mpu_fck: smartreflex_mpu_fck {
reg = <0x0628>;
};
cm2_dm10_mux: cm2_dm10_mux {
cm2_dm10_mux: cm2_dm10_mux@1428 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
......@@ -1198,7 +1198,7 @@ cm2_dm10_mux: cm2_dm10_mux {
reg = <0x1428>;
};
cm2_dm11_mux: cm2_dm11_mux {
cm2_dm11_mux: cm2_dm11_mux@1430 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
......@@ -1206,7 +1206,7 @@ cm2_dm11_mux: cm2_dm11_mux {
reg = <0x1430>;
};
cm2_dm2_mux: cm2_dm2_mux {
cm2_dm2_mux: cm2_dm2_mux@1438 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
......@@ -1214,7 +1214,7 @@ cm2_dm2_mux: cm2_dm2_mux {
reg = <0x1438>;
};
cm2_dm3_mux: cm2_dm3_mux {
cm2_dm3_mux: cm2_dm3_mux@1440 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
......@@ -1222,7 +1222,7 @@ cm2_dm3_mux: cm2_dm3_mux {
reg = <0x1440>;
};
cm2_dm4_mux: cm2_dm4_mux {
cm2_dm4_mux: cm2_dm4_mux@1448 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
......@@ -1230,7 +1230,7 @@ cm2_dm4_mux: cm2_dm4_mux {
reg = <0x1448>;
};
cm2_dm9_mux: cm2_dm9_mux {
cm2_dm9_mux: cm2_dm9_mux@1450 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
......@@ -1238,7 +1238,7 @@ cm2_dm9_mux: cm2_dm9_mux {
reg = <0x1450>;
};
usb_host_fs_fck: usb_host_fs_fck {
usb_host_fs_fck: usb_host_fs_fck@13d0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&func_48mc_fclk>;
......@@ -1246,7 +1246,7 @@ usb_host_fs_fck: usb_host_fs_fck {
reg = <0x13d0>;
};
utmi_p1_gfclk: utmi_p1_gfclk {
utmi_p1_gfclk: utmi_p1_gfclk@1358 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&init_60m_fclk>, <&xclk60mhsp1_ck>;
......@@ -1254,7 +1254,7 @@ utmi_p1_gfclk: utmi_p1_gfclk {
reg = <0x1358>;
};
usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk {
usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@1358 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&utmi_p1_gfclk>;
......@@ -1262,7 +1262,7 @@ usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk {
reg = <0x1358>;
};
utmi_p2_gfclk: utmi_p2_gfclk {
utmi_p2_gfclk: utmi_p2_gfclk@1358 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&init_60m_fclk>, <&xclk60mhsp2_ck>;
......@@ -1270,7 +1270,7 @@ utmi_p2_gfclk: utmi_p2_gfclk {
reg = <0x1358>;
};
usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk {
usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@1358 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&utmi_p2_gfclk>;
......@@ -1278,7 +1278,7 @@ usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk {
reg = <0x1358>;
};
usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk {
usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@1358 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&init_60m_fclk>;
......@@ -1286,7 +1286,7 @@ usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk {
reg = <0x1358>;
};
usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk {
usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@1358 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_usb_m2_ck>;
......@@ -1294,7 +1294,7 @@ usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk {
reg = <0x1358>;
};
usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk {
usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@1358 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&init_60m_fclk>;
......@@ -1302,7 +1302,7 @@ usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk {
reg = <0x1358>;
};
usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk {
usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@1358 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&init_60m_fclk>;
......@@ -1310,7 +1310,7 @@ usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk {
reg = <0x1358>;
};
usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk {
usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@1358 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_usb_m2_ck>;
......@@ -1318,7 +1318,7 @@ usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk {
reg = <0x1358>;
};
usb_host_hs_func48mclk: usb_host_hs_func48mclk {
usb_host_hs_func48mclk: usb_host_hs_func48mclk@1358 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&func_48mc_fclk>;
......@@ -1326,7 +1326,7 @@ usb_host_hs_func48mclk: usb_host_hs_func48mclk {
reg = <0x1358>;
};
usb_host_hs_fck: usb_host_hs_fck {
usb_host_hs_fck: usb_host_hs_fck@1358 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&init_60m_fclk>;
......@@ -1334,7 +1334,7 @@ usb_host_hs_fck: usb_host_hs_fck {
reg = <0x1358>;
};
otg_60m_gfclk: otg_60m_gfclk {
otg_60m_gfclk: otg_60m_gfclk@1360 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&utmi_phy_clkout_ck>, <&xclk60motg_ck>;
......@@ -1342,7 +1342,7 @@ otg_60m_gfclk: otg_60m_gfclk {
reg = <0x1360>;
};
usb_otg_hs_xclk: usb_otg_hs_xclk {
usb_otg_hs_xclk: usb_otg_hs_xclk@1360 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&otg_60m_gfclk>;
......@@ -1350,7 +1350,7 @@ usb_otg_hs_xclk: usb_otg_hs_xclk {
reg = <0x1360>;
};
usb_otg_hs_ick: usb_otg_hs_ick {
usb_otg_hs_ick: usb_otg_hs_ick@1360 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3_div_ck>;
......@@ -1358,7 +1358,7 @@ usb_otg_hs_ick: usb_otg_hs_ick {
reg = <0x1360>;
};
usb_phy_cm_clk32k: usb_phy_cm_clk32k {
usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -1366,7 +1366,7 @@ usb_phy_cm_clk32k: usb_phy_cm_clk32k {
reg = <0x0640>;
};
usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk {
usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@1368 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&init_60m_fclk>;
......@@ -1374,7 +1374,7 @@ usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk {
reg = <0x1368>;
};
usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk {
usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@1368 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&init_60m_fclk>;
......@@ -1382,7 +1382,7 @@ usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk {
reg = <0x1368>;
};
usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk {
usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@1368 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&init_60m_fclk>;
......@@ -1390,7 +1390,7 @@ usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk {
reg = <0x1368>;
};
usb_tll_hs_ick: usb_tll_hs_ick {
usb_tll_hs_ick: usb_tll_hs_ick@1368 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l4_div_ck>;
......@@ -1407,7 +1407,7 @@ l3_init_clkdm: l3_init_clkdm {
};
&scrm_clocks {
auxclk0_src_gate_ck: auxclk0_src_gate_ck {
auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clocks = <&dpll_core_m3x2_ck>;
......@@ -1415,7 +1415,7 @@ auxclk0_src_gate_ck: auxclk0_src_gate_ck {
reg = <0x0310>;
};
auxclk0_src_mux_ck: auxclk0_src_mux_ck {
auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
......@@ -1429,7 +1429,7 @@ auxclk0_src_ck: auxclk0_src_ck {
clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
};
auxclk0_ck: auxclk0_ck {
auxclk0_ck: auxclk0_ck@310 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&auxclk0_src_ck>;
......@@ -1438,7 +1438,7 @@ auxclk0_ck: auxclk0_ck {
reg = <0x0310>;
};
auxclk1_src_gate_ck: auxclk1_src_gate_ck {
auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clocks = <&dpll_core_m3x2_ck>;
......@@ -1446,7 +1446,7 @@ auxclk1_src_gate_ck: auxclk1_src_gate_ck {
reg = <0x0314>;
};
auxclk1_src_mux_ck: auxclk1_src_mux_ck {
auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
......@@ -1460,7 +1460,7 @@ auxclk1_src_ck: auxclk1_src_ck {
clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
};
auxclk1_ck: auxclk1_ck {
auxclk1_ck: auxclk1_ck@314 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&auxclk1_src_ck>;
......@@ -1469,7 +1469,7 @@ auxclk1_ck: auxclk1_ck {
reg = <0x0314>;
};
auxclk2_src_gate_ck: auxclk2_src_gate_ck {
auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clocks = <&dpll_core_m3x2_ck>;
......@@ -1477,7 +1477,7 @@ auxclk2_src_gate_ck: auxclk2_src_gate_ck {
reg = <0x0318>;
};
auxclk2_src_mux_ck: auxclk2_src_mux_ck {
auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
......@@ -1491,7 +1491,7 @@ auxclk2_src_ck: auxclk2_src_ck {
clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
};
auxclk2_ck: auxclk2_ck {
auxclk2_ck: auxclk2_ck@318 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&auxclk2_src_ck>;
......@@ -1500,7 +1500,7 @@ auxclk2_ck: auxclk2_ck {
reg = <0x0318>;
};
auxclk3_src_gate_ck: auxclk3_src_gate_ck {
auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clocks = <&dpll_core_m3x2_ck>;
......@@ -1508,7 +1508,7 @@ auxclk3_src_gate_ck: auxclk3_src_gate_ck {
reg = <0x031c>;
};
auxclk3_src_mux_ck: auxclk3_src_mux_ck {
auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
......@@ -1522,7 +1522,7 @@ auxclk3_src_ck: auxclk3_src_ck {
clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
};
auxclk3_ck: auxclk3_ck {
auxclk3_ck: auxclk3_ck@31c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&auxclk3_src_ck>;
......@@ -1531,7 +1531,7 @@ auxclk3_ck: auxclk3_ck {
reg = <0x031c>;
};
auxclk4_src_gate_ck: auxclk4_src_gate_ck {
auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clocks = <&dpll_core_m3x2_ck>;
......@@ -1539,7 +1539,7 @@ auxclk4_src_gate_ck: auxclk4_src_gate_ck {
reg = <0x0320>;
};
auxclk4_src_mux_ck: auxclk4_src_mux_ck {
auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
......@@ -1553,7 +1553,7 @@ auxclk4_src_ck: auxclk4_src_ck {
clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
};
auxclk4_ck: auxclk4_ck {
auxclk4_ck: auxclk4_ck@320 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&auxclk4_src_ck>;
......@@ -1562,7 +1562,7 @@ auxclk4_ck: auxclk4_ck {
reg = <0x0320>;
};
auxclk5_src_gate_ck: auxclk5_src_gate_ck {
auxclk5_src_gate_ck: auxclk5_src_gate_ck@324 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clocks = <&dpll_core_m3x2_ck>;
......@@ -1570,7 +1570,7 @@ auxclk5_src_gate_ck: auxclk5_src_gate_ck {
reg = <0x0324>;
};
auxclk5_src_mux_ck: auxclk5_src_mux_ck {
auxclk5_src_mux_ck: auxclk5_src_mux_ck@324 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
......@@ -1584,7 +1584,7 @@ auxclk5_src_ck: auxclk5_src_ck {
clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>;
};
auxclk5_ck: auxclk5_ck {
auxclk5_ck: auxclk5_ck@324 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&auxclk5_src_ck>;
......@@ -1593,7 +1593,7 @@ auxclk5_ck: auxclk5_ck {
reg = <0x0324>;
};
auxclkreq0_ck: auxclkreq0_ck {
auxclkreq0_ck: auxclkreq0_ck@210 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
......@@ -1601,7 +1601,7 @@ auxclkreq0_ck: auxclkreq0_ck {
reg = <0x0210>;
};
auxclkreq1_ck: auxclkreq1_ck {
auxclkreq1_ck: auxclkreq1_ck@214 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
......@@ -1609,7 +1609,7 @@ auxclkreq1_ck: auxclkreq1_ck {
reg = <0x0214>;
};
auxclkreq2_ck: auxclkreq2_ck {
auxclkreq2_ck: auxclkreq2_ck@218 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
......@@ -1617,7 +1617,7 @@ auxclkreq2_ck: auxclkreq2_ck {
reg = <0x0218>;
};
auxclkreq3_ck: auxclkreq3_ck {
auxclkreq3_ck: auxclkreq3_ck@21c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
......@@ -1625,7 +1625,7 @@ auxclkreq3_ck: auxclkreq3_ck {
reg = <0x021c>;
};
auxclkreq4_ck: auxclkreq4_ck {
auxclkreq4_ck: auxclkreq4_ck@220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
......@@ -1633,7 +1633,7 @@ auxclkreq4_ck: auxclkreq4_ck {
reg = <0x0220>;
};
auxclkreq5_ck: auxclkreq5_ck {
auxclkreq5_ck: auxclkreq5_ck@224 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
......
arch/arm/boot/dts/omap5.dtsi
View file @ 1ea7c8b6
......@@ -187,7 +187,7 @@ omap5_padconf_global: omap5_padconf_global@5a0 {
#size-cells = <1>;
ranges = <0 0x5a0 0xec>;
pbias_regulator: pbias_regulator {
pbias_regulator: pbias_regulator@60 {
compatible = "ti,pbias-omap5", "ti,pbias-omap";
reg = <0x60 0x4>;
syscon = <&omap5_padconf_global>;
......@@ -398,6 +398,10 @@ gpmc: gpmc@50000000 {
ti,hwmods = "gpmc";
clocks = <&l3_iclk_div>;
clock-names = "fck";
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
};
i2c1: i2c@48070000 {
......
arch/arm/boot/dts/omap54xx-clocks.dtsi
View file @ 1ea7c8b6
......@@ -14,7 +14,7 @@ pad_clks_src_ck: pad_clks_src_ck {
clock-frequency = <12000000>;
};
pad_clks_ck: pad_clks_ck {
pad_clks_ck: pad_clks_ck@108 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&pad_clks_src_ck>;
......@@ -34,7 +34,7 @@ slimbus_src_clk: slimbus_src_clk {
clock-frequency = <12000000>;
};
slimbus_clk: slimbus_clk {
slimbus_clk: slimbus_clk@108 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&slimbus_src_clk>;
......@@ -102,7 +102,7 @@ xclk60mhsp2_ck: xclk60mhsp2_ck {
clock-frequency = <60000000>;
};
dpll_abe_ck: dpll_abe_ck {
dpll_abe_ck: dpll_abe_ck@1e0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-m4xen-clock";
clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
......@@ -115,7 +115,7 @@ dpll_abe_x2_ck: dpll_abe_x2_ck {
clocks = <&dpll_abe_ck>;
};
dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_x2_ck>;
......@@ -132,7 +132,7 @@ abe_24m_fclk: abe_24m_fclk {
clock-div = <8>;
};
abe_clk: abe_clk {
abe_clk: abe_clk@108 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_m2x2_ck>;
......@@ -141,7 +141,7 @@ abe_clk: abe_clk {
ti,index-power-of-two;
};
abe_iclk: abe_iclk {
abe_iclk: abe_iclk@528 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&aess_fclk>;
......@@ -158,7 +158,7 @@ abe_lp_clk_div: abe_lp_clk_div {
clock-div = <16>;
};
dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_abe_x2_ck>;
......@@ -167,7 +167,7 @@ dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
ti,index-starts-at-one;
};
dpll_core_byp_mux: dpll_core_byp_mux {
dpll_core_byp_mux: dpll_core_byp_mux@12c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
......@@ -175,7 +175,7 @@ dpll_core_byp_mux: dpll_core_byp_mux {
reg = <0x012c>;
};
dpll_core_ck: dpll_core_ck {
dpll_core_ck: dpll_core_ck@120 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-core-clock";
clocks = <&sys_clkin>, <&dpll_core_byp_mux>;
......@@ -188,7 +188,7 @@ dpll_core_x2_ck: dpll_core_x2_ck {
clocks = <&dpll_core_ck>;
};
dpll_core_h21x2_ck: dpll_core_h21x2_ck {
dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
......@@ -213,7 +213,7 @@ c2c_iclk: c2c_iclk {
clock-div = <2>;
};
dpll_core_h11x2_ck: dpll_core_h11x2_ck {
dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
......@@ -222,7 +222,7 @@ dpll_core_h11x2_ck: dpll_core_h11x2_ck {
ti,index-starts-at-one;
};
dpll_core_h12x2_ck: dpll_core_h12x2_ck {
dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
......@@ -231,7 +231,7 @@ dpll_core_h12x2_ck: dpll_core_h12x2_ck {
ti,index-starts-at-one;
};
dpll_core_h13x2_ck: dpll_core_h13x2_ck {
dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
......@@ -240,7 +240,7 @@ dpll_core_h13x2_ck: dpll_core_h13x2_ck {
ti,index-starts-at-one;
};
dpll_core_h14x2_ck: dpll_core_h14x2_ck {
dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
......@@ -249,7 +249,7 @@ dpll_core_h14x2_ck: dpll_core_h14x2_ck {
ti,index-starts-at-one;
};
dpll_core_h22x2_ck: dpll_core_h22x2_ck {
dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
......@@ -258,7 +258,7 @@ dpll_core_h22x2_ck: dpll_core_h22x2_ck {
ti,index-starts-at-one;
};
dpll_core_h23x2_ck: dpll_core_h23x2_ck {
dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
......@@ -267,7 +267,7 @@ dpll_core_h23x2_ck: dpll_core_h23x2_ck {
ti,index-starts-at-one;
};
dpll_core_h24x2_ck: dpll_core_h24x2_ck {
dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
......@@ -276,7 +276,7 @@ dpll_core_h24x2_ck: dpll_core_h24x2_ck {
ti,index-starts-at-one;
};
dpll_core_m2_ck: dpll_core_m2_ck {
dpll_core_m2_ck: dpll_core_m2_ck@130 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_ck>;
......@@ -285,7 +285,7 @@ dpll_core_m2_ck: dpll_core_m2_ck {
ti,index-starts-at-one;
};
dpll_core_m3x2_ck: dpll_core_m3x2_ck {
dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
......@@ -302,7 +302,7 @@ iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
clock-div = <1>;
};
dpll_iva_byp_mux: dpll_iva_byp_mux {
dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
......@@ -310,7 +310,7 @@ dpll_iva_byp_mux: dpll_iva_byp_mux {
reg = <0x01ac>;
};
dpll_iva_ck: dpll_iva_ck {
dpll_iva_ck: dpll_iva_ck@1a0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin>, <&dpll_iva_byp_mux>;
......@@ -323,7 +323,7 @@ dpll_iva_x2_ck: dpll_iva_x2_ck {
clocks = <&dpll_iva_ck>;
};
dpll_iva_h11x2_ck: dpll_iva_h11x2_ck {
dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_iva_x2_ck>;
......@@ -332,7 +332,7 @@ dpll_iva_h11x2_ck: dpll_iva_h11x2_ck {
ti,index-starts-at-one;
};
dpll_iva_h12x2_ck: dpll_iva_h12x2_ck {
dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_iva_x2_ck>;
......@@ -349,14 +349,14 @@ mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
clock-div = <1>;
};
dpll_mpu_ck: dpll_mpu_ck {
dpll_mpu_ck: dpll_mpu_ck@160 {
#clock-cells = <0>;
compatible = "ti,omap5-mpu-dpll-clock";
clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
};
dpll_mpu_m2_ck: dpll_mpu_m2_ck {
dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_mpu_ck>;
......@@ -381,7 +381,7 @@ usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
clock-div = <3>;
};
l3_iclk_div: l3_iclk_div {
l3_iclk_div: l3_iclk_div@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
ti,max-div = <2>;
......@@ -399,7 +399,7 @@ gpu_l3_iclk: gpu_l3_iclk {
clock-div = <1>;
};
l4_root_clk_div: l4_root_clk_div {
l4_root_clk_div: l4_root_clk_div@100 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
ti,max-div = <2>;
......@@ -409,7 +409,7 @@ l4_root_clk_div: l4_root_clk_div {
ti,index-power-of-two;
};
slimbus1_slimbus_clk: slimbus1_slimbus_clk {
slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&slimbus_clk>;
......@@ -417,7 +417,7 @@ slimbus1_slimbus_clk: slimbus1_slimbus_clk {
reg = <0x0560>;
};
aess_fclk: aess_fclk {
aess_fclk: aess_fclk@528 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&abe_clk>;
......@@ -426,7 +426,7 @@ aess_fclk: aess_fclk {
reg = <0x0528>;
};
dmic_sync_mux_ck: dmic_sync_mux_ck {
dmic_sync_mux_ck: dmic_sync_mux_ck@538 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
......@@ -434,7 +434,7 @@ dmic_sync_mux_ck: dmic_sync_mux_ck {
reg = <0x0538>;
};
dmic_gfclk: dmic_gfclk {
dmic_gfclk: dmic_gfclk@538 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
......@@ -442,7 +442,7 @@ dmic_gfclk: dmic_gfclk {
reg = <0x0538>;
};
mcasp_sync_mux_ck: mcasp_sync_mux_ck {
mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
......@@ -450,7 +450,7 @@ mcasp_sync_mux_ck: mcasp_sync_mux_ck {
reg = <0x0540>;
};
mcasp_gfclk: mcasp_gfclk {
mcasp_gfclk: mcasp_gfclk@540 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
......@@ -458,7 +458,7 @@ mcasp_gfclk: mcasp_gfclk {
reg = <0x0540>;
};
mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck {
mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@548 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
......@@ -466,7 +466,7 @@ mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck {
reg = <0x0548>;
};
mcbsp1_gfclk: mcbsp1_gfclk {
mcbsp1_gfclk: mcbsp1_gfclk@548 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
......@@ -474,7 +474,7 @@ mcbsp1_gfclk: mcbsp1_gfclk {
reg = <0x0548>;
};
mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck {
mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
......@@ -482,7 +482,7 @@ mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck {
reg = <0x0550>;
};
mcbsp2_gfclk: mcbsp2_gfclk {
mcbsp2_gfclk: mcbsp2_gfclk@550 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
......@@ -490,7 +490,7 @@ mcbsp2_gfclk: mcbsp2_gfclk {
reg = <0x0550>;
};
mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck {
mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@558 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
......@@ -498,7 +498,7 @@ mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck {
reg = <0x0558>;
};
mcbsp3_gfclk: mcbsp3_gfclk {
mcbsp3_gfclk: mcbsp3_gfclk@558 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
......@@ -506,7 +506,7 @@ mcbsp3_gfclk: mcbsp3_gfclk {
reg = <0x0558>;
};
timer5_gfclk_mux: timer5_gfclk_mux {
timer5_gfclk_mux: timer5_gfclk_mux@568 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
......@@ -514,7 +514,7 @@ timer5_gfclk_mux: timer5_gfclk_mux {
reg = <0x0568>;
};
timer6_gfclk_mux: timer6_gfclk_mux {
timer6_gfclk_mux: timer6_gfclk_mux@570 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
......@@ -522,7 +522,7 @@ timer6_gfclk_mux: timer6_gfclk_mux {
reg = <0x0570>;
};
timer7_gfclk_mux: timer7_gfclk_mux {
timer7_gfclk_mux: timer7_gfclk_mux@578 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
......@@ -530,7 +530,7 @@ timer7_gfclk_mux: timer7_gfclk_mux {
reg = <0x0578>;
};
timer8_gfclk_mux: timer8_gfclk_mux {
timer8_gfclk_mux: timer8_gfclk_mux@580 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
......@@ -545,7 +545,7 @@ dummy_ck: dummy_ck {
};
};
&prm_clocks {
sys_clkin: sys_clkin {
sys_clkin: sys_clkin@110 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
......@@ -553,14 +553,14 @@ sys_clkin: sys_clkin {
ti,index-starts-at-one;
};
abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin>, <&sys_32k_ck>;
reg = <0x0108>;
};
abe_dpll_clk_mux: abe_dpll_clk_mux {
abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin>, <&sys_32k_ck>;
......@@ -583,7 +583,7 @@ dss_syc_gfclk_div: dss_syc_gfclk_div {
clock-div = <1>;
};
wkupaon_iclk_mux: wkupaon_iclk_mux {
wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin>, <&abe_lp_clk_div>;
......@@ -598,7 +598,7 @@ l3instr_ts_gclk_div: l3instr_ts_gclk_div {
clock-div = <1>;
};
gpio1_dbclk: gpio1_dbclk {
gpio1_dbclk: gpio1_dbclk@1938 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -606,7 +606,7 @@ gpio1_dbclk: gpio1_dbclk {
reg = <0x1938>;
};
timer1_gfclk_mux: timer1_gfclk_mux {
timer1_gfclk_mux: timer1_gfclk_mux@1940 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin>, <&sys_32k_ck>;
......@@ -616,7 +616,7 @@ timer1_gfclk_mux: timer1_gfclk_mux {
};
&cm_core_clocks {
dpll_per_byp_mux: dpll_per_byp_mux {
dpll_per_byp_mux: dpll_per_byp_mux@14c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
......@@ -624,7 +624,7 @@ dpll_per_byp_mux: dpll_per_byp_mux {
reg = <0x014c>;
};
dpll_per_ck: dpll_per_ck {
dpll_per_ck: dpll_per_ck@140 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin>, <&dpll_per_byp_mux>;
......@@ -637,7 +637,7 @@ dpll_per_x2_ck: dpll_per_x2_ck {
clocks = <&dpll_per_ck>;
};
dpll_per_h11x2_ck: dpll_per_h11x2_ck {
dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
......@@ -646,7 +646,7 @@ dpll_per_h11x2_ck: dpll_per_h11x2_ck {
ti,index-starts-at-one;
};
dpll_per_h12x2_ck: dpll_per_h12x2_ck {
dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
......@@ -655,7 +655,7 @@ dpll_per_h12x2_ck: dpll_per_h12x2_ck {
ti,index-starts-at-one;
};
dpll_per_h14x2_ck: dpll_per_h14x2_ck {
dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
......@@ -664,7 +664,7 @@ dpll_per_h14x2_ck: dpll_per_h14x2_ck {
ti,index-starts-at-one;
};
dpll_per_m2_ck: dpll_per_m2_ck {
dpll_per_m2_ck: dpll_per_m2_ck@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_ck>;
......@@ -673,7 +673,7 @@ dpll_per_m2_ck: dpll_per_m2_ck {
ti,index-starts-at-one;
};
dpll_per_m2x2_ck: dpll_per_m2x2_ck {
dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
......@@ -682,7 +682,7 @@ dpll_per_m2x2_ck: dpll_per_m2x2_ck {
ti,index-starts-at-one;
};
dpll_per_m3x2_ck: dpll_per_m3x2_ck {
dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_x2_ck>;
......@@ -691,7 +691,7 @@ dpll_per_m3x2_ck: dpll_per_m3x2_ck {
ti,index-starts-at-one;
};
dpll_unipro1_ck: dpll_unipro1_ck {
dpll_unipro1_ck: dpll_unipro1_ck@200 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin>, <&sys_clkin>;
......@@ -706,7 +706,7 @@ dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
clock-div = <1>;
};
dpll_unipro1_m2_ck: dpll_unipro1_m2_ck {
dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_unipro1_ck>;
......@@ -715,7 +715,7 @@ dpll_unipro1_m2_ck: dpll_unipro1_m2_ck {
ti,index-starts-at-one;
};
dpll_unipro2_ck: dpll_unipro2_ck {
dpll_unipro2_ck: dpll_unipro2_ck@1c0 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-clock";
clocks = <&sys_clkin>, <&sys_clkin>;
......@@ -730,7 +730,7 @@ dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
clock-div = <1>;
};
dpll_unipro2_m2_ck: dpll_unipro2_m2_ck {
dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_unipro2_ck>;
......@@ -739,7 +739,7 @@ dpll_unipro2_m2_ck: dpll_unipro2_m2_ck {
ti,index-starts-at-one;
};
dpll_usb_byp_mux: dpll_usb_byp_mux {
dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
......@@ -747,7 +747,7 @@ dpll_usb_byp_mux: dpll_usb_byp_mux {
reg = <0x018c>;
};
dpll_usb_ck: dpll_usb_ck {
dpll_usb_ck: dpll_usb_ck@180 {
#clock-cells = <0>;
compatible = "ti,omap4-dpll-j-type-clock";
clocks = <&sys_clkin>, <&dpll_usb_byp_mux>;
......@@ -762,7 +762,7 @@ dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
clock-div = <1>;
};
dpll_usb_m2_ck: dpll_usb_m2_ck {
dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_usb_ck>;
......@@ -811,7 +811,7 @@ func_96m_fclk: func_96m_fclk {
clock-div = <2>;
};
l3init_60m_fclk: l3init_60m_fclk {
l3init_60m_fclk: l3init_60m_fclk@104 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_usb_m2_ck>;
......@@ -819,7 +819,7 @@ l3init_60m_fclk: l3init_60m_fclk {
ti,dividers = <1>, <8>;
};
dss_32khz_clk: dss_32khz_clk {
dss_32khz_clk: dss_32khz_clk@1420 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -827,7 +827,7 @@ dss_32khz_clk: dss_32khz_clk {
reg = <0x1420>;
};
dss_48mhz_clk: dss_48mhz_clk {
dss_48mhz_clk: dss_48mhz_clk@1420 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&func_48m_fclk>;
......@@ -835,7 +835,7 @@ dss_48mhz_clk: dss_48mhz_clk {
reg = <0x1420>;
};
dss_dss_clk: dss_dss_clk {
dss_dss_clk: dss_dss_clk@1420 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_h12x2_ck>;
......@@ -844,7 +844,7 @@ dss_dss_clk: dss_dss_clk {
ti,set-rate-parent;
};
dss_sys_clk: dss_sys_clk {
dss_sys_clk: dss_sys_clk@1420 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dss_syc_gfclk_div>;
......@@ -852,7 +852,7 @@ dss_sys_clk: dss_sys_clk {
reg = <0x1420>;
};
gpio2_dbclk: gpio2_dbclk {
gpio2_dbclk: gpio2_dbclk@1060 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -860,7 +860,7 @@ gpio2_dbclk: gpio2_dbclk {
reg = <0x1060>;
};
gpio3_dbclk: gpio3_dbclk {
gpio3_dbclk: gpio3_dbclk@1068 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -868,7 +868,7 @@ gpio3_dbclk: gpio3_dbclk {
reg = <0x1068>;
};
gpio4_dbclk: gpio4_dbclk {
gpio4_dbclk: gpio4_dbclk@1070 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -876,7 +876,7 @@ gpio4_dbclk: gpio4_dbclk {
reg = <0x1070>;
};
gpio5_dbclk: gpio5_dbclk {
gpio5_dbclk: gpio5_dbclk@1078 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -884,7 +884,7 @@ gpio5_dbclk: gpio5_dbclk {
reg = <0x1078>;
};
gpio6_dbclk: gpio6_dbclk {
gpio6_dbclk: gpio6_dbclk@1080 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -892,7 +892,7 @@ gpio6_dbclk: gpio6_dbclk {
reg = <0x1080>;
};
gpio7_dbclk: gpio7_dbclk {
gpio7_dbclk: gpio7_dbclk@1110 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -900,7 +900,7 @@ gpio7_dbclk: gpio7_dbclk {
reg = <0x1110>;
};
gpio8_dbclk: gpio8_dbclk {
gpio8_dbclk: gpio8_dbclk@1118 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -908,7 +908,7 @@ gpio8_dbclk: gpio8_dbclk {
reg = <0x1118>;
};
iss_ctrlclk: iss_ctrlclk {
iss_ctrlclk: iss_ctrlclk@1320 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&func_96m_fclk>;
......@@ -916,7 +916,7 @@ iss_ctrlclk: iss_ctrlclk {
reg = <0x1320>;
};
lli_txphy_clk: lli_txphy_clk {
lli_txphy_clk: lli_txphy_clk@f20 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_unipro1_clkdcoldo>;
......@@ -924,7 +924,7 @@ lli_txphy_clk: lli_txphy_clk {
reg = <0x0f20>;
};
lli_txphy_ls_clk: lli_txphy_ls_clk {
lli_txphy_ls_clk: lli_txphy_ls_clk@f20 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_unipro1_m2_ck>;
......@@ -932,7 +932,7 @@ lli_txphy_ls_clk: lli_txphy_ls_clk {
reg = <0x0f20>;
};
mmc1_32khz_clk: mmc1_32khz_clk {
mmc1_32khz_clk: mmc1_32khz_clk@1628 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -940,7 +940,7 @@ mmc1_32khz_clk: mmc1_32khz_clk {
reg = <0x1628>;
};
sata_ref_clk: sata_ref_clk {
sata_ref_clk: sata_ref_clk@1688 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_clkin>;
......@@ -948,7 +948,7 @@ sata_ref_clk: sata_ref_clk {
reg = <0x1688>;
};
usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk {
usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@1658 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_usb_m2_ck>;
......@@ -956,7 +956,7 @@ usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk {
reg = <0x1658>;
};
usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk {
usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@1658 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_usb_m2_ck>;
......@@ -964,7 +964,7 @@ usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk {
reg = <0x1658>;
};
usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk {
usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk@1658 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_usb_m2_ck>;
......@@ -972,7 +972,7 @@ usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk {
reg = <0x1658>;
};
usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk {
usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@1658 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3init_60m_fclk>;
......@@ -980,7 +980,7 @@ usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk {
reg = <0x1658>;
};
usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk {
usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@1658 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3init_60m_fclk>;
......@@ -988,7 +988,7 @@ usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk {
reg = <0x1658>;
};
usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk {
usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk@1658 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3init_60m_fclk>;
......@@ -996,7 +996,7 @@ usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk {
reg = <0x1658>;
};
utmi_p1_gfclk: utmi_p1_gfclk {
utmi_p1_gfclk: utmi_p1_gfclk@1658 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>;
......@@ -1004,7 +1004,7 @@ utmi_p1_gfclk: utmi_p1_gfclk {
reg = <0x1658>;
};
usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk {
usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@1658 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&utmi_p1_gfclk>;
......@@ -1012,7 +1012,7 @@ usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk {
reg = <0x1658>;
};
utmi_p2_gfclk: utmi_p2_gfclk {
utmi_p2_gfclk: utmi_p2_gfclk@1658 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>;
......@@ -1020,7 +1020,7 @@ utmi_p2_gfclk: utmi_p2_gfclk {
reg = <0x1658>;
};
usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk {
usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@1658 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&utmi_p2_gfclk>;
......@@ -1028,7 +1028,7 @@ usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk {
reg = <0x1658>;
};
usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk {
usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@1658 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3init_60m_fclk>;
......@@ -1036,7 +1036,7 @@ usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk {
reg = <0x1658>;
};
usb_otg_ss_refclk960m: usb_otg_ss_refclk960m {
usb_otg_ss_refclk960m: usb_otg_ss_refclk960m@16f0 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_usb_clkdcoldo>;
......@@ -1044,7 +1044,7 @@ usb_otg_ss_refclk960m: usb_otg_ss_refclk960m {
reg = <0x16f0>;
};
usb_phy_cm_clk32k: usb_phy_cm_clk32k {
usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
......@@ -1052,7 +1052,7 @@ usb_phy_cm_clk32k: usb_phy_cm_clk32k {
reg = <0x0640>;
};
usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk {
usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@1668 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3init_60m_fclk>;
......@@ -1060,7 +1060,7 @@ usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk {
reg = <0x1668>;
};
usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk {
usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@1668 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3init_60m_fclk>;
......@@ -1068,7 +1068,7 @@ usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk {
reg = <0x1668>;
};
usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk {
usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@1668 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3init_60m_fclk>;
......@@ -1076,7 +1076,7 @@ usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk {
reg = <0x1668>;
};
fdif_fclk: fdif_fclk {
fdif_fclk: fdif_fclk@1328 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_h11x2_ck>;
......@@ -1085,7 +1085,7 @@ fdif_fclk: fdif_fclk {
reg = <0x1328>;
};
gpu_core_gclk_mux: gpu_core_gclk_mux {
gpu_core_gclk_mux: gpu_core_gclk_mux@1520 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
......@@ -1093,7 +1093,7 @@ gpu_core_gclk_mux: gpu_core_gclk_mux {
reg = <0x1520>;
};
gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
......@@ -1101,7 +1101,7 @@ gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
reg = <0x1520>;
};
hsi_fclk: hsi_fclk {
hsi_fclk: hsi_fclk@1638 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_m2x2_ck>;
......@@ -1110,7 +1110,7 @@ hsi_fclk: hsi_fclk {
reg = <0x1638>;
};
mmc1_fclk_mux: mmc1_fclk_mux {
mmc1_fclk_mux: mmc1_fclk_mux@1628 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
......@@ -1118,7 +1118,7 @@ mmc1_fclk_mux: mmc1_fclk_mux {
reg = <0x1628>;
};
mmc1_fclk: mmc1_fclk {
mmc1_fclk: mmc1_fclk@1628 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc1_fclk_mux>;
......@@ -1127,7 +1127,7 @@ mmc1_fclk: mmc1_fclk {
reg = <0x1628>;
};
mmc2_fclk_mux: mmc2_fclk_mux {
mmc2_fclk_mux: mmc2_fclk_mux@1630 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
......@@ -1135,7 +1135,7 @@ mmc2_fclk_mux: mmc2_fclk_mux {
reg = <0x1630>;
};
mmc2_fclk: mmc2_fclk {
mmc2_fclk: mmc2_fclk@1630 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&mmc2_fclk_mux>;
......@@ -1144,7 +1144,7 @@ mmc2_fclk: mmc2_fclk {
reg = <0x1630>;
};
timer10_gfclk_mux: timer10_gfclk_mux {
timer10_gfclk_mux: timer10_gfclk_mux@1028 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin>, <&sys_32k_ck>;
......@@ -1152,7 +1152,7 @@ timer10_gfclk_mux: timer10_gfclk_mux {
reg = <0x1028>;
};
timer11_gfclk_mux: timer11_gfclk_mux {
timer11_gfclk_mux: timer11_gfclk_mux@1030 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin>, <&sys_32k_ck>;
......@@ -1160,7 +1160,7 @@ timer11_gfclk_mux: timer11_gfclk_mux {
reg = <0x1030>;
};
timer2_gfclk_mux: timer2_gfclk_mux {
timer2_gfclk_mux: timer2_gfclk_mux@1038 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin>, <&sys_32k_ck>;
......@@ -1168,7 +1168,7 @@ timer2_gfclk_mux: timer2_gfclk_mux {
reg = <0x1038>;
};
timer3_gfclk_mux: timer3_gfclk_mux {
timer3_gfclk_mux: timer3_gfclk_mux@1040 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin>, <&sys_32k_ck>;
......@@ -1176,7 +1176,7 @@ timer3_gfclk_mux: timer3_gfclk_mux {
reg = <0x1040>;
};
timer4_gfclk_mux: timer4_gfclk_mux {
timer4_gfclk_mux: timer4_gfclk_mux@1048 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin>, <&sys_32k_ck>;
......@@ -1184,7 +1184,7 @@ timer4_gfclk_mux: timer4_gfclk_mux {
reg = <0x1048>;
};
timer9_gfclk_mux: timer9_gfclk_mux {
timer9_gfclk_mux: timer9_gfclk_mux@1050 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin>, <&sys_32k_ck>;
......@@ -1201,7 +1201,7 @@ l3init_clkdm: l3init_clkdm {
};
&scrm_clocks {
auxclk0_src_gate_ck: auxclk0_src_gate_ck {
auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clocks = <&dpll_core_m3x2_ck>;
......@@ -1209,7 +1209,7 @@ auxclk0_src_gate_ck: auxclk0_src_gate_ck {
reg = <0x0310>;
};
auxclk0_src_mux_ck: auxclk0_src_mux_ck {
auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
......@@ -1223,7 +1223,7 @@ auxclk0_src_ck: auxclk0_src_ck {
clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
};
auxclk0_ck: auxclk0_ck {
auxclk0_ck: auxclk0_ck@310 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&auxclk0_src_ck>;
......@@ -1232,7 +1232,7 @@ auxclk0_ck: auxclk0_ck {
reg = <0x0310>;
};
auxclk1_src_gate_ck: auxclk1_src_gate_ck {
auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clocks = <&dpll_core_m3x2_ck>;
......@@ -1240,7 +1240,7 @@ auxclk1_src_gate_ck: auxclk1_src_gate_ck {
reg = <0x0314>;
};
auxclk1_src_mux_ck: auxclk1_src_mux_ck {
auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
......@@ -1254,7 +1254,7 @@ auxclk1_src_ck: auxclk1_src_ck {
clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
};
auxclk1_ck: auxclk1_ck {
auxclk1_ck: auxclk1_ck@314 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&auxclk1_src_ck>;
......@@ -1263,7 +1263,7 @@ auxclk1_ck: auxclk1_ck {
reg = <0x0314>;
};
auxclk2_src_gate_ck: auxclk2_src_gate_ck {
auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clocks = <&dpll_core_m3x2_ck>;
......@@ -1271,7 +1271,7 @@ auxclk2_src_gate_ck: auxclk2_src_gate_ck {
reg = <0x0318>;
};
auxclk2_src_mux_ck: auxclk2_src_mux_ck {
auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
......@@ -1285,7 +1285,7 @@ auxclk2_src_ck: auxclk2_src_ck {
clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
};
auxclk2_ck: auxclk2_ck {
auxclk2_ck: auxclk2_ck@318 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&auxclk2_src_ck>;
......@@ -1294,7 +1294,7 @@ auxclk2_ck: auxclk2_ck {
reg = <0x0318>;
};
auxclk3_src_gate_ck: auxclk3_src_gate_ck {
auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clocks = <&dpll_core_m3x2_ck>;
......@@ -1302,7 +1302,7 @@ auxclk3_src_gate_ck: auxclk3_src_gate_ck {
reg = <0x031c>;
};
auxclk3_src_mux_ck: auxclk3_src_mux_ck {
auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
......@@ -1316,7 +1316,7 @@ auxclk3_src_ck: auxclk3_src_ck {
clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
};
auxclk3_ck: auxclk3_ck {
auxclk3_ck: auxclk3_ck@31c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&auxclk3_src_ck>;
......@@ -1325,7 +1325,7 @@ auxclk3_ck: auxclk3_ck {
reg = <0x031c>;
};
auxclk4_src_gate_ck: auxclk4_src_gate_ck {
auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
#clock-cells = <0>;
compatible = "ti,composite-no-wait-gate-clock";
clocks = <&dpll_core_m3x2_ck>;
......@@ -1333,7 +1333,7 @@ auxclk4_src_gate_ck: auxclk4_src_gate_ck {
reg = <0x0320>;
};
auxclk4_src_mux_ck: auxclk4_src_mux_ck {
auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
......@@ -1347,7 +1347,7 @@ auxclk4_src_ck: auxclk4_src_ck {
clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
};
auxclk4_ck: auxclk4_ck {
auxclk4_ck: auxclk4_ck@320 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&auxclk4_src_ck>;
......@@ -1356,7 +1356,7 @@ auxclk4_ck: auxclk4_ck {
reg = <0x0320>;
};
auxclkreq0_ck: auxclkreq0_ck {
auxclkreq0_ck: auxclkreq0_ck@210 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
......@@ -1364,7 +1364,7 @@ auxclkreq0_ck: auxclkreq0_ck {
reg = <0x0210>;
};
auxclkreq1_ck: auxclkreq1_ck {
auxclkreq1_ck: auxclkreq1_ck@214 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
......@@ -1372,7 +1372,7 @@ auxclkreq1_ck: auxclkreq1_ck {
reg = <0x0214>;
};
auxclkreq2_ck: auxclkreq2_ck {
auxclkreq2_ck: auxclkreq2_ck@218 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
......@@ -1380,7 +1380,7 @@ auxclkreq2_ck: auxclkreq2_ck {
reg = <0x0218>;
};
auxclkreq3_ck: auxclkreq3_ck {
auxclkreq3_ck: auxclkreq3_ck@21c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
......
drivers/clk/ti/clk-7xx.c
View file @ 1ea7c8b6
......@@ -223,7 +223,7 @@ static struct ti_dt_clk dra7xx_clks[] = {
DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "mcasp6_aux_gfclk_mux"),
DT_CLK(NULL, "mcasp7_ahclkx_mux", "mcasp7_ahclkx_mux"),
DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "mcasp7_aux_gfclk_mux"),
DT_CLK(NULL, "mcasp8_ahclk_mux", "mcasp8_ahclk_mux"),
DT_CLK(NULL, "mcasp8_ahclkx_mux", "mcasp8_ahclkx_mux"),
DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "mcasp8_aux_gfclk_mux"),
DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"),
DT_CLK(NULL, "mmc1_fclk_div", "mmc1_fclk_div"),
......
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